arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries.
   4  */
   5
   6 /dts-v1/;
   7 #include "sparx5_pcb_common.dtsi"
   8
   9 /{
  10         aliases {
  11             i2c0   = &i2c0;
  12             i2c152 = &i2c152;
  13             i2c153 = &i2c153;
  14             i2c154 = &i2c154;
  15             i2c155 = &i2c155;
  16         };
  17
  18         gpio-restart {
  19                 compatible = "gpio-restart";
  20                 gpios = <&gpio 37 GPIO_ACTIVE_LOW>;
  21                 priority = <200>;
  22         };
  23 };
  24
  25 &gpio {
  26         i2cmux_pins_i: i2cmux-pins-i {
  27                pins = "GPIO_35", "GPIO_36",
  28                       "GPIO_50", "GPIO_51";
  29                 function = "twi_scl_m";
  30                 output-low;
  31         };
  32         i2cmux_s29: i2cmux-0 {
  33                 pins = "GPIO_35";
  34                 function = "twi_scl_m";
  35                 output-high;
  36         };
  37         i2cmux_s30: i2cmux-1 {
  38                 pins = "GPIO_36";
  39                 function = "twi_scl_m";
  40                 output-high;
  41         };
  42         i2cmux_s31: i2cmux-2 {
  43                 pins = "GPIO_50";
  44                 function = "twi_scl_m";
  45                 output-high;
  46         };
  47         i2cmux_s32: i2cmux-3 {
  48                 pins = "GPIO_51";
  49                 function = "twi_scl_m";
  50                 output-high;
  51         };
  52 };
  53
  54 &spi0 {
  55         status = "okay";
  56         spi@0 {
  57                 compatible = "spi-mux";
  58                 mux-controls = <&mux>;
  59                 #address-cells = <1>;
  60                 #size-cells = <0>;
  61                 reg = <0>; /* CS0 */
  62                 spi-flash@9 {
  63                         compatible = "jedec,spi-nor";
  64                         spi-max-frequency = <8000000>;
  65                         reg = <0x9>; /* SPI */
  66                 };
  67         };
  68 };
  69
  70 &spi0 {
  71         status = "okay";
  72         spi@0 {
  73                 compatible = "spi-mux";
  74                 mux-controls = <&mux>;
  75                 #address-cells = <1>;
  76                 #size-cells = <0>;
  77                 reg = <0>; /* CS0 */
  78                 spi-flash@9 {
  79                         compatible = "jedec,spi-nor";
  80                         spi-max-frequency = <8000000>;
  81                         reg = <0x9>; /* SPI */
  82                 };
  83         };
  84 };
  85
  86 &axi {
  87         i2c0_imux: i2c0-imux@0 {
  88                 compatible = "i2c-mux-pinctrl";
  89                 #address-cells = <1>;
  90                 #size-cells = <0>;
  91                 i2c-parent = <&i2c0>;
  92         };
  93 };
  94
  95 &i2c0_imux {
  96         pinctrl-names =
  97                 "i2c152", "i2c153", "i2c154", "i2c155",
  98                 "idle";
  99         pinctrl-0 = <&i2cmux_s29>;
 100         pinctrl-1 = <&i2cmux_s30>;
 101         pinctrl-2 = <&i2cmux_s31>;
 102         pinctrl-3 = <&i2cmux_s32>;
 103         pinctrl-4 = <&i2cmux_pins_i>;
 104         i2c152: i2c_sfp1 {
 105                 reg = <0x0>;
 106                 #address-cells = <1>;
 107                 #size-cells = <0>;
 108         };
 109         i2c153: i2c_sfp2 {
 110                 reg = <0x1>;
 111                 #address-cells = <1>;
 112                 #size-cells = <0>;
 113         };
 114         i2c154: i2c_sfp3 {
 115                 reg = <0x2>;
 116                 #address-cells = <1>;
 117                 #size-cells = <0>;
 118         };
 119         i2c155: i2c_sfp4 {
 120                 reg = <0x3>;
 121                 #address-cells = <1>;
 122                 #size-cells = <0>;
 123         };
 124 };