arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries.
   4  */
   5
   6 /dts-v1/;
   7 #include "sparx5_pcb_common.dtsi"
   8
   9 /{
  10         gpio-restart {
  11                 compatible = "gpio-restart";
  12                 gpios = <&gpio 37 GPIO_ACTIVE_LOW>;
  13                 priority = <200>;
  14         };
  15
  16         leds {
  17                 compatible = "gpio-leds";
  18                 led@0 {
  19                         label = "eth60:yellow";
  20                         gpios = <&sgpio_out1 28 0 GPIO_ACTIVE_LOW>;
  21                         default-state = "off";
  22                 };
  23                 led@1 {
  24                         label = "eth60:green";
  25                         gpios = <&sgpio_out1 28 1 GPIO_ACTIVE_LOW>;
  26                         default-state = "off";
  27                 };
  28                 led@2 {
  29                         label = "eth61:yellow";
  30                         gpios = <&sgpio_out1 29 0 GPIO_ACTIVE_LOW>;
  31                         default-state = "off";
  32                 };
  33                 led@3 {
  34                         label = "eth61:green";
  35                         gpios = <&sgpio_out1 29 1 GPIO_ACTIVE_LOW>;
  36                         default-state = "off";
  37                 };
  38                 led@4 {
  39                         label = "eth62:yellow";
  40                         gpios = <&sgpio_out1 30 0 GPIO_ACTIVE_LOW>;
  41                         default-state = "off";
  42                 };
  43                 led@5 {
  44                         label = "eth62:green";
  45                         gpios = <&sgpio_out1 30 1 GPIO_ACTIVE_LOW>;
  46                         default-state = "off";
  47                 };
  48                 led@6 {
  49                         label = "eth63:yellow";
  50                         gpios = <&sgpio_out1 31 0 GPIO_ACTIVE_LOW>;
  51                         default-state = "off";
  52                 };
  53                 led@7 {
  54                         label = "eth63:green";
  55                         gpios = <&sgpio_out1 31 1 GPIO_ACTIVE_LOW>;
  56                         default-state = "off";
  57                 };
  58         };
  59 };
  60
  61 &gpio {
  62         i2cmux_pins_i: i2cmux-pins-i {
  63                pins = "GPIO_35", "GPIO_36",
  64                       "GPIO_50", "GPIO_51";
  65                 function = "twi_scl_m";
  66                 output-low;
  67         };
  68         i2cmux_s29: i2cmux-0 {
  69                 pins = "GPIO_35";
  70                 function = "twi_scl_m";
  71                 output-high;
  72         };
  73         i2cmux_s30: i2cmux-1 {
  74                 pins = "GPIO_36";
  75                 function = "twi_scl_m";
  76                 output-high;
  77         };
  78         i2cmux_s31: i2cmux-2 {
  79                 pins = "GPIO_50";
  80                 function = "twi_scl_m";
  81                 output-high;
  82         };
  83         i2cmux_s32: i2cmux-3 {
  84                 pins = "GPIO_51";
  85                 function = "twi_scl_m";
  86                 output-high;
  87         };
  88 };
  89
  90 &spi0 {
  91         status = "okay";
  92         spi-flash@0 {
  93                 compatible = "jedec,spi-nor";
  94                 spi-max-frequency = <8000000>;
  95                 reg = <0>;
  96         };
  97 };
  98
  99 &spi0 {
 100         status = "okay";
 101         spi@0 {
 102                 compatible = "spi-mux";
 103                 mux-controls = <&mux>;
 104                 #address-cells = <1>;
 105                 #size-cells = <0>;
 106                 reg = <0>; /* CS0 */
 107                 spi-flash@9 {
 108                         compatible = "jedec,spi-nor";
 109                         spi-max-frequency = <8000000>;
 110                         reg = <0x9>; /* SPI */
 111                 };
 112         };
 113 };
 114
 115 &sgpio1 {
 116         status = "okay";
 117         microchip,sgpio-port-ranges = <24 31>;
 118         gpio@0 {
 119                 ngpios = <64>;
 120         };
 121         gpio@1 {
 122                 ngpios = <64>;
 123         };
 124 };
 125
 126 &sgpio2 {
 127         status = "okay";
 128         microchip,sgpio-port-ranges = <0 0>, <16 18>, <28 31>;
 129 };
 130
 131 &axi {
 132         i2c0_imux: i2c0-imux@0 {
 133                 compatible = "i2c-mux-pinctrl";
 134                 #address-cells = <1>;
 135                 #size-cells = <0>;
 136                 i2c-parent = <&i2c0>;
 137         };
 138 };
 139
 140 &i2c0_imux {
 141         pinctrl-names =
 142                 "i2c_sfp1", "i2c_sfp2", "i2c_sfp3", "i2c_sfp4",
 143                 "idle";
 144         pinctrl-0 = <&i2cmux_s29>;
 145         pinctrl-1 = <&i2cmux_s30>;
 146         pinctrl-2 = <&i2cmux_s31>;
 147         pinctrl-3 = <&i2cmux_s32>;
 148         pinctrl-4 = <&i2cmux_pins_i>;
 149         i2c_sfp1: i2c_sfp1 {
 150                 reg = <0x0>;
 151                 #address-cells = <1>;
 152                 #size-cells = <0>;
 153         };
 154         i2c_sfp2: i2c_sfp2 {
 155                 reg = <0x1>;
 156                 #address-cells = <1>;
 157                 #size-cells = <0>;
 158         };
 159         i2c_sfp3: i2c_sfp3 {
 160                 reg = <0x2>;
 161                 #address-cells = <1>;
 162                 #size-cells = <0>;
 163         };
 164         i2c_sfp4: i2c_sfp4 {
 165                 reg = <0x3>;
 166                 #address-cells = <1>;
 167                 #size-cells = <0>;
 168         };
 169 };
 170
 171 &axi {
 172         sfp_eth60: sfp-eth60 {
 173                 compatible         = "sff,sfp";
 174                 i2c-bus            = <&i2c_sfp1>;
 175                 tx-disable-gpios   = <&sgpio_out2 28 0 GPIO_ACTIVE_LOW>;
 176                 rate-select0-gpios = <&sgpio_out2 28 1 GPIO_ACTIVE_HIGH>;
 177                 los-gpios          = <&sgpio_in2 28 0 GPIO_ACTIVE_HIGH>;
 178                 mod-def0-gpios     = <&sgpio_in2 28 1 GPIO_ACTIVE_LOW>;
 179                 tx-fault-gpios     = <&sgpio_in2 28 2 GPIO_ACTIVE_HIGH>;
 180         };
 181         sfp_eth61: sfp-eth61 {
 182                 compatible         = "sff,sfp";
 183                 i2c-bus            = <&i2c_sfp2>;
 184                 tx-disable-gpios   = <&sgpio_out2 29 0 GPIO_ACTIVE_LOW>;
 185                 rate-select0-gpios = <&sgpio_out2 29 1 GPIO_ACTIVE_HIGH>;
 186                 los-gpios          = <&sgpio_in2 29 0 GPIO_ACTIVE_HIGH>;
 187                 mod-def0-gpios     = <&sgpio_in2 29 1 GPIO_ACTIVE_LOW>;
 188                 tx-fault-gpios     = <&sgpio_in2 29 2 GPIO_ACTIVE_HIGH>;
 189         };
 190         sfp_eth62: sfp-eth62 {
 191                 compatible         = "sff,sfp";
 192                 i2c-bus            = <&i2c_sfp3>;
 193                 tx-disable-gpios   = <&sgpio_out2 30 0 GPIO_ACTIVE_LOW>;
 194                 rate-select0-gpios = <&sgpio_out2 30 1 GPIO_ACTIVE_HIGH>;
 195                 los-gpios          = <&sgpio_in2 30 0 GPIO_ACTIVE_HIGH>;
 196                 mod-def0-gpios     = <&sgpio_in2 30 1 GPIO_ACTIVE_LOW>;
 197                 tx-fault-gpios     = <&sgpio_in2 30 2 GPIO_ACTIVE_HIGH>;
 198         };
 199         sfp_eth63: sfp-eth63 {
 200                 compatible         = "sff,sfp";
 201                 i2c-bus            = <&i2c_sfp4>;
 202                 tx-disable-gpios   = <&sgpio_out2 31 0 GPIO_ACTIVE_LOW>;
 203                 rate-select0-gpios = <&sgpio_out2 31 1 GPIO_ACTIVE_HIGH>;
 204                 los-gpios          = <&sgpio_in2 31 0 GPIO_ACTIVE_HIGH>;
 205                 mod-def0-gpios     = <&sgpio_in2 31 1 GPIO_ACTIVE_LOW>;
 206                 tx-fault-gpios     = <&sgpio_in2 31 2 GPIO_ACTIVE_HIGH>;
 207         };
 208 };
 209
 210 &mdio0 {
 211         status = "ok";
 212         phy0: ethernet-phy@0 {
 213                 reg = <0>;
 214         };
 215         phy1: ethernet-phy@1 {
 216                 reg = <1>;
 217         };
 218         phy2: ethernet-phy@2 {
 219                 reg = <2>;
 220         };
 221         phy3: ethernet-phy@3 {
 222                 reg = <3>;
 223         };
 224         phy4: ethernet-phy@4 {
 225                 reg = <4>;
 226         };
 227         phy5: ethernet-phy@5 {
 228                 reg = <5>;
 229         };
 230         phy6: ethernet-phy@6 {
 231                 reg = <6>;
 232         };
 233         phy7: ethernet-phy@7 {
 234                 reg = <7>;
 235         };
 236         phy8: ethernet-phy@8 {
 237                 reg = <8>;
 238         };
 239         phy9: ethernet-phy@9 {
 240                 reg = <9>;
 241         };
 242         phy10: ethernet-phy@10 {
 243                 reg = <10>;
 244         };
 245         phy11: ethernet-phy@11 {
 246                 reg = <11>;
 247         };
 248         phy12: ethernet-phy@12 {
 249                 reg = <12>;
 250         };
 251         phy13: ethernet-phy@13 {
 252                 reg = <13>;
 253         };
 254         phy14: ethernet-phy@14 {
 255                 reg = <14>;
 256         };
 257         phy15: ethernet-phy@15 {
 258                 reg = <15>;
 259         };
 260         phy16: ethernet-phy@16 {
 261                 reg = <16>;
 262         };
 263         phy17: ethernet-phy@17 {
 264                 reg = <17>;
 265         };
 266         phy18: ethernet-phy@18 {
 267                 reg = <18>;
 268         };
 269         phy19: ethernet-phy@19 {
 270                 reg = <19>;
 271         };
 272         phy20: ethernet-phy@20 {
 273                 reg = <20>;
 274         };
 275         phy21: ethernet-phy@21 {
 276                 reg = <21>;
 277         };
 278         phy22: ethernet-phy@22 {
 279                 reg = <22>;
 280         };
 281         phy23: ethernet-phy@23 {
 282                 reg = <23>;
 283         };
 284 };
 285
 286 &mdio1 {
 287         status = "ok";
 288         phy24: ethernet-phy@24 {
 289                 reg = <0>;
 290         };
 291         phy25: ethernet-phy@25 {
 292                 reg = <1>;
 293         };
 294         phy26: ethernet-phy@26 {
 295                 reg = <2>;
 296         };
 297         phy27: ethernet-phy@27 {
 298                 reg = <3>;
 299         };
 300         phy28: ethernet-phy@28 {
 301                 reg = <4>;
 302         };
 303         phy29: ethernet-phy@29 {
 304                 reg = <5>;
 305         };
 306         phy30: ethernet-phy@30 {
 307                 reg = <6>;
 308         };
 309         phy31: ethernet-phy@31 {
 310                 reg = <7>;
 311         };
 312         phy32: ethernet-phy@32 {
 313                 reg = <8>;
 314         };
 315         phy33: ethernet-phy@33 {
 316                 reg = <9>;
 317         };
 318         phy34: ethernet-phy@34 {
 319                 reg = <10>;
 320         };
 321         phy35: ethernet-phy@35 {
 322                 reg = <11>;
 323         };
 324         phy36: ethernet-phy@36 {
 325                 reg = <12>;
 326         };
 327         phy37: ethernet-phy@37 {
 328                 reg = <13>;
 329         };
 330         phy38: ethernet-phy@38 {
 331                 reg = <14>;
 332         };
 333         phy39: ethernet-phy@39 {
 334                 reg = <15>;
 335         };
 336         phy40: ethernet-phy@40 {
 337                 reg = <16>;
 338         };
 339         phy41: ethernet-phy@41 {
 340                 reg = <17>;
 341         };
 342         phy42: ethernet-phy@42 {
 343                 reg = <18>;
 344         };
 345         phy43: ethernet-phy@43 {
 346                 reg = <19>;
 347         };
 348         phy44: ethernet-phy@44 {
 349                 reg = <20>;
 350         };
 351         phy45: ethernet-phy@45 {
 352                 reg = <21>;
 353         };
 354         phy46: ethernet-phy@46 {
 355                 reg = <22>;
 356         };
 357         phy47: ethernet-phy@47 {
 358                 reg = <23>;
 359         };
 360 };
 361
 362 &mdio3 {
 363         status = "ok";
 364         phy64: ethernet-phy@64 {
 365                 reg = <28>;
 366         };
 367 };
 368
 369 &switch {
 370         ethernet-ports {
 371                 #address-cells = <1>;
 372                 #size-cells = <0>;
 373
 374                 port0: port@0 {
 375                         reg = <0>;
 376                         microchip,bandwidth = <1000>;
 377                         phys = <&serdes 13>;
 378                         phy-handle = <&phy0>;
 379                         phy-mode = "qsgmii";
 380                 };
 381                 port1: port@1 {
 382                         reg = <1>;
 383                         microchip,bandwidth = <1000>;
 384                         phys = <&serdes 13>;
 385                         phy-handle = <&phy1>;
 386                         phy-mode = "qsgmii";
 387                 };
 388                 port2: port@2 {
 389                         reg = <2>;
 390                         microchip,bandwidth = <1000>;
 391                         phys = <&serdes 13>;
 392                         phy-handle = <&phy2>;
 393                         phy-mode = "qsgmii";
 394                 };
 395                 port3: port@3 {
 396                         reg = <3>;
 397                         microchip,bandwidth = <1000>;
 398                         phys = <&serdes 13>;
 399                         phy-handle = <&phy3>;
 400                         phy-mode = "qsgmii";
 401                 };
 402                 port4: port@4 {
 403                         reg = <4>;
 404                         microchip,bandwidth = <1000>;
 405                         phys = <&serdes 14>;
 406                         phy-handle = <&phy4>;
 407                         phy-mode = "qsgmii";
 408                 };
 409                 port5: port@5 {
 410                         reg = <5>;
 411                         microchip,bandwidth = <1000>;
 412                         phys = <&serdes 14>;
 413                         phy-handle = <&phy5>;
 414                         phy-mode = "qsgmii";
 415                 };
 416                 port6: port@6 {
 417                         reg = <6>;
 418                         microchip,bandwidth = <1000>;
 419                         phys = <&serdes 14>;
 420                         phy-handle = <&phy6>;
 421                         phy-mode = "qsgmii";
 422                 };
 423                 port7: port@7 {
 424                         reg = <7>;
 425                         microchip,bandwidth = <1000>;
 426                         phys = <&serdes 14>;
 427                         phy-handle = <&phy7>;
 428                         phy-mode = "qsgmii";
 429                 };
 430                 port8: port@8 {
 431                         reg = <8>;
 432                         microchip,bandwidth = <1000>;
 433                         phys = <&serdes 15>;
 434                         phy-handle = <&phy8>;
 435                         phy-mode = "qsgmii";
 436                 };
 437                 port9: port@9 {
 438                         reg = <9>;
 439                         microchip,bandwidth = <1000>;
 440                         phys = <&serdes 15>;
 441                         phy-handle = <&phy9>;
 442                         phy-mode = "qsgmii";
 443                 };
 444                 port10: port@10 {
 445                         reg = <10>;
 446                         microchip,bandwidth = <1000>;
 447                         phys = <&serdes 15>;
 448                         phy-handle = <&phy10>;
 449                         phy-mode = "qsgmii";
 450                 };
 451                 port11: port@11 {
 452                         reg = <11>;
 453                         microchip,bandwidth = <1000>;
 454                         phys = <&serdes 15>;
 455                         phy-handle = <&phy11>;
 456                         phy-mode = "qsgmii";
 457                 };
 458                 port12: port@12 {
 459                         reg = <12>;
 460                         microchip,bandwidth = <1000>;
 461                         phys = <&serdes 16>;
 462                         phy-handle = <&phy12>;
 463                         phy-mode = "qsgmii";
 464                 };
 465                 port13: port@13 {
 466                         reg = <13>;
 467                         microchip,bandwidth = <1000>;
 468                         phys = <&serdes 16>;
 469                         phy-handle = <&phy13>;
 470                         phy-mode = "qsgmii";
 471                 };
 472                 port14: port@14 {
 473                         reg = <14>;
 474                         microchip,bandwidth = <1000>;
 475                         phys = <&serdes 16>;
 476                         phy-handle = <&phy14>;
 477                         phy-mode = "qsgmii";
 478                 };
 479                 port15: port@15 {
 480                         reg = <15>;
 481                         microchip,bandwidth = <1000>;
 482                         phys = <&serdes 16>;
 483                         phy-handle = <&phy15>;
 484                         phy-mode = "qsgmii";
 485                 };
 486                 port16: port@16 {
 487                         reg = <16>;
 488                         microchip,bandwidth = <1000>;
 489                         phys = <&serdes 17>;
 490                         phy-handle = <&phy16>;
 491                         phy-mode = "qsgmii";
 492                 };
 493                 port17: port@17 {
 494                         reg = <17>;
 495                         microchip,bandwidth = <1000>;
 496                         phys = <&serdes 17>;
 497                         phy-handle = <&phy17>;
 498                         phy-mode = "qsgmii";
 499                 };
 500                 port18: port@18 {
 501                         reg = <18>;
 502                         microchip,bandwidth = <1000>;
 503                         phys = <&serdes 17>;
 504                         phy-handle = <&phy18>;
 505                         phy-mode = "qsgmii";
 506                 };
 507                 port19: port@19 {
 508                         reg = <19>;
 509                         microchip,bandwidth = <1000>;
 510                         phys = <&serdes 17>;
 511                         phy-handle = <&phy19>;
 512                         phy-mode = "qsgmii";
 513                 };
 514                 port20: port@20 {
 515                         reg = <20>;
 516                         microchip,bandwidth = <1000>;
 517                         phys = <&serdes 18>;
 518                         phy-handle = <&phy20>;
 519                         phy-mode = "qsgmii";
 520                 };
 521                 port21: port@21 {
 522                         reg = <21>;
 523                         microchip,bandwidth = <1000>;
 524                         phys = <&serdes 18>;
 525                         phy-handle = <&phy21>;
 526                         phy-mode = "qsgmii";
 527                 };
 528                 port22: port@22 {
 529                         reg = <22>;
 530                         microchip,bandwidth = <1000>;
 531                         phys = <&serdes 18>;
 532                         phy-handle = <&phy22>;
 533                         phy-mode = "qsgmii";
 534                 };
 535                 port23: port@23 {
 536                         reg = <23>;
 537                         microchip,bandwidth = <1000>;
 538                         phys = <&serdes 18>;
 539                         phy-handle = <&phy23>;
 540                         phy-mode = "qsgmii";
 541                 };
 542                 port24: port@24 {
 543                         reg = <24>;
 544                         microchip,bandwidth = <1000>;
 545                         phys = <&serdes 19>;
 546                         phy-handle = <&phy24>;
 547                         phy-mode = "qsgmii";
 548                 };
 549                 port25: port@25 {
 550                         reg = <25>;
 551                         microchip,bandwidth = <1000>;
 552                         phys = <&serdes 19>;
 553                         phy-handle = <&phy25>;
 554                         phy-mode = "qsgmii";
 555                 };
 556                 port26: port@26 {
 557                         reg = <26>;
 558                         microchip,bandwidth = <1000>;
 559                         phys = <&serdes 19>;
 560                         phy-handle = <&phy26>;
 561                         phy-mode = "qsgmii";
 562                 };
 563                 port27: port@27 {
 564                         reg = <27>;
 565                         microchip,bandwidth = <1000>;
 566                         phys = <&serdes 19>;
 567                         phy-handle = <&phy27>;
 568                         phy-mode = "qsgmii";
 569                 };
 570                 port28: port@28 {
 571                         reg = <28>;
 572                         microchip,bandwidth = <1000>;
 573                         phys = <&serdes 20>;
 574                         phy-handle = <&phy28>;
 575                         phy-mode = "qsgmii";
 576                 };
 577                 port29: port@29 {
 578                         reg = <29>;
 579                         microchip,bandwidth = <1000>;
 580                         phys = <&serdes 20>;
 581                         phy-handle = <&phy29>;
 582                         phy-mode = "qsgmii";
 583                 };
 584                 port30: port@30 {
 585                         reg = <30>;
 586                         microchip,bandwidth = <1000>;
 587                         phys = <&serdes 20>;
 588                         phy-handle = <&phy30>;
 589                         phy-mode = "qsgmii";
 590                 };
 591                 port31: port@31 {
 592                         reg = <31>;
 593                         microchip,bandwidth = <1000>;
 594                         phys = <&serdes 20>;
 595                         phy-handle = <&phy31>;
 596                         phy-mode = "qsgmii";
 597                 };
 598                 port32: port@32 {
 599                         reg = <32>;
 600                         microchip,bandwidth = <1000>;
 601                         phys = <&serdes 21>;
 602                         phy-handle = <&phy32>;
 603                         phy-mode = "qsgmii";
 604                 };
 605                 port33: port@33 {
 606                         reg = <33>;
 607                         microchip,bandwidth = <1000>;
 608                         phys = <&serdes 21>;
 609                         phy-handle = <&phy33>;
 610                         phy-mode = "qsgmii";
 611                 };
 612                 port34: port@34 {
 613                         reg = <34>;
 614                         microchip,bandwidth = <1000>;
 615                         phys = <&serdes 21>;
 616                         phy-handle = <&phy34>;
 617                         phy-mode = "qsgmii";
 618                 };
 619                 port35: port@35 {
 620                         reg = <35>;
 621                         microchip,bandwidth = <1000>;
 622                         phys = <&serdes 21>;
 623                         phy-handle = <&phy35>;
 624                         phy-mode = "qsgmii";
 625                 };
 626                 port36: port@36 {
 627                         reg = <36>;
 628                         microchip,bandwidth = <1000>;
 629                         phys = <&serdes 22>;
 630                         phy-handle = <&phy36>;
 631                         phy-mode = "qsgmii";
 632                 };
 633                 port37: port@37 {
 634                         reg = <37>;
 635                         microchip,bandwidth = <1000>;
 636                         phys = <&serdes 22>;
 637                         phy-handle = <&phy37>;
 638                         phy-mode = "qsgmii";
 639                 };
 640                 port38: port@38 {
 641                         reg = <38>;
 642                         microchip,bandwidth = <1000>;
 643                         phys = <&serdes 22>;
 644                         phy-handle = <&phy38>;
 645                         phy-mode = "qsgmii";
 646                 };
 647                 port39: port@39 {
 648                         reg = <39>;
 649                         microchip,bandwidth = <1000>;
 650                         phys = <&serdes 22>;
 651                         phy-handle = <&phy39>;
 652                         phy-mode = "qsgmii";
 653                 };
 654                 port40: port@40 {
 655                         reg = <40>;
 656                         microchip,bandwidth = <1000>;
 657                         phys = <&serdes 23>;
 658                         phy-handle = <&phy40>;
 659                         phy-mode = "qsgmii";
 660                 };
 661                 port41: port@41 {
 662                         reg = <41>;
 663                         microchip,bandwidth = <1000>;
 664                         phys = <&serdes 23>;
 665                         phy-handle = <&phy41>;
 666                         phy-mode = "qsgmii";
 667                 };
 668                 port42: port@42 {
 669                         reg = <42>;
 670                         microchip,bandwidth = <1000>;
 671                         phys = <&serdes 23>;
 672                         phy-handle = <&phy42>;
 673                         phy-mode = "qsgmii";
 674                 };
 675                 port43: port@43 {
 676                         reg = <43>;
 677                         microchip,bandwidth = <1000>;
 678                         phys = <&serdes 23>;
 679                         phy-handle = <&phy43>;
 680                         phy-mode = "qsgmii";
 681                 };
 682                 port44: port@44 {
 683                         reg = <44>;
 684                         microchip,bandwidth = <1000>;
 685                         phys = <&serdes 24>;
 686                         phy-handle = <&phy44>;
 687                         phy-mode = "qsgmii";
 688                 };
 689                 port45: port@45 {
 690                         reg = <45>;
 691                         microchip,bandwidth = <1000>;
 692                         phys = <&serdes 24>;
 693                         phy-handle = <&phy45>;
 694                         phy-mode = "qsgmii";
 695                 };
 696                 port46: port@46 {
 697                         reg = <46>;
 698                         microchip,bandwidth = <1000>;
 699                         phys = <&serdes 24>;
 700                         phy-handle = <&phy46>;
 701                         phy-mode = "qsgmii";
 702                 };
 703                 port47: port@47 {
 704                         reg = <47>;
 705                         microchip,bandwidth = <1000>;
 706                         phys = <&serdes 24>;
 707                         phy-handle = <&phy47>;
 708                         phy-mode = "qsgmii";
 709                 };
 710                 /* Then the 25G interfaces */
 711                 port60: port@60 {
 712                         reg = <60>;
 713                         microchip,bandwidth = <25000>;
 714                         phys = <&serdes 29>;
 715                         phy-mode = "10gbase-r";
 716                         sfp = <&sfp_eth60>;
 717                         managed = "in-band-status";
 718                 };
 719                 port61: port@61 {
 720                         reg = <61>;
 721                         microchip,bandwidth = <25000>;
 722                         phys = <&serdes 30>;
 723                         phy-mode = "10gbase-r";
 724                         sfp = <&sfp_eth61>;
 725                         managed = "in-band-status";
 726                 };
 727                 port62: port@62 {
 728                         reg = <62>;
 729                         microchip,bandwidth = <25000>;
 730                         phys = <&serdes 31>;
 731                         phy-mode = "10gbase-r";
 732                         sfp = <&sfp_eth62>;
 733                         managed = "in-band-status";
 734                 };
 735                 port63: port@63 {
 736                         reg = <63>;
 737                         microchip,bandwidth = <25000>;
 738                         phys = <&serdes 32>;
 739                         phy-mode = "10gbase-r";
 740                         sfp = <&sfp_eth63>;
 741                         managed = "in-band-status";
 742                 };
 743                 /* Finally the Management interface */
 744                 port64: port@64 {
 745                         reg = <64>;
 746                         microchip,bandwidth = <1000>;
 747                         phys = <&serdes 0>;
 748                         phy-handle = <&phy64>;
 749                         phy-mode = "sgmii";
 750                 };
 751         };
 752 };