arch/arm64/boot/dts/microchip/sparx5.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries.
   4  */
   5
   6 #include <dt-bindings/gpio/gpio.h>
   7 #include <dt-bindings/interrupt-controller/arm-gic.h>
   8 #include <dt-bindings/clock/microchip,sparx5.h>
   9
  10 / {
  11         compatible = "microchip,sparx5";
  12         interrupt-parent = <&gic>;
  13         #address-cells = <2>;
  14         #size-cells = <1>;
  15
  16         aliases {
  17                 spi0 = &spi0;
  18                 serial0 = &uart0;
  19                 serial1 = &uart1;
  20         };
  21
  22         chosen {
  23                 stdout-path = "serial0:115200n8";
  24         };
  25
  26         cpus {
  27                 #address-cells = <2>;
  28                 #size-cells = <0>;
  29                 cpu-map {
  30                         cluster0 {
  31                                 core0 {
  32                                         cpu = <&cpu0>;
  33                                 };
  34                                 core1 {
  35                                         cpu = <&cpu1>;
  36                                 };
  37                         };
  38                 };
  39                 cpu0: cpu@0 {
  40                         compatible = "arm,cortex-a53";
  41                         device_type = "cpu";
  42                         reg = <0x0 0x0>;
  43                         enable-method = "psci";
  44                         next-level-cache = <&L2_0>;
  45                 };
  46                 cpu1: cpu@1 {
  47                         compatible = "arm,cortex-a53";
  48                         device_type = "cpu";
  49                         reg = <0x0 0x1>;
  50                         enable-method = "psci";
  51                         next-level-cache = <&L2_0>;
  52                 };
  53                 L2_0: l2-cache0 {
  54                         compatible = "cache";
  55                 };
  56         };
  57
  58         arm-pmu {
  59                 compatible = "arm,cortex-a53-pmu";
  60                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
  61                 interrupt-affinity = <&cpu0>, <&cpu1>;
  62         };
  63
  64         psci {
  65                 compatible = "arm,psci-0.2";
  66                 method = "smc";
  67         };
  68
  69         timer {
  70                 compatible = "arm,armv8-timer";
  71                 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
  72                              <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
  73                              <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
  74                              <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
  75         };
  76
  77         lcpll_clk: lcpll-clk {
  78                 compatible = "fixed-clock";
  79                 #clock-cells = <0>;
  80                 clock-frequency = <2500000000>;
  81         };
  82
  83         clks: clock-controller@61110000c {
  84                 compatible = "microchip,sparx5-dpll";
  85                 #clock-cells = <1>;
  86                 clocks = <&lcpll_clk>;
  87                 reg = <0x6 0x1110000c 0x24>;
  88         };
  89
  90         ahb_clk: ahb-clk {
  91                 compatible = "fixed-clock";
  92                 #clock-cells = <0>;
  93                 clock-frequency = <250000000>;
  94         };
  95
  96         sys_clk: sys-clk {
  97                 compatible = "fixed-clock";
  98                 #clock-cells = <0>;
  99                 clock-frequency = <625000000>;
 100         };
 101
 102         axi: axi@600000000 {
 103                 compatible = "simple-bus";
 104                 #address-cells = <2>;
 105                 #size-cells = <1>;
 106                 ranges;
 107
 108                 gic: interrupt-controller@600300000 {
 109                         compatible = "arm,gic-v3";
 110                         #interrupt-cells = <3>;
 111                         #address-cells = <2>;
 112                         #size-cells = <2>;
 113                         interrupt-controller;
 114                         reg = <0x6 0x00300000 0x10000>, /* GIC Dist */
 115                               <0x6 0x00340000 0xc0000>, /* GICR */
 116                               <0x6 0x00200000 0x2000>,  /* GICC */
 117                               <0x6 0x00210000 0x2000>,  /* GICV */
 118                               <0x6 0x00220000 0x2000>;  /* GICH */
 119                         interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
 120                 };
 121
 122                 cpu_ctrl: syscon@600000000 {
 123                         compatible = "microchip,sparx5-cpu-syscon", "syscon",
 124                                      "simple-mfd";
 125                         reg = <0x6 0x00000000 0xd0>;
 126                         mux: mux-controller {
 127                                 compatible = "mmio-mux";
 128                                 #mux-control-cells = <0>;
 129                                 /*
 130                                  * SI_OWNER and SI2_OWNER in GENERAL_CTRL
 131                                  * SPI:  value 9 - (SIMC,SIBM) = 0b1001
 132                                  * SPI2: value 6 - (SIBM,SIMC) = 0b0110
 133                                  */
 134                                 mux-reg-masks = <0x88 0xf0>;
 135                         };
 136                 };
 137
 138                 reset@611010008 {
 139                         compatible = "microchip,sparx5-chip-reset";
 140                         reg = <0x6 0x11010008 0x4>;
 141                 };
 142
 143                 uart0: serial@600100000 {
 144                         pinctrl-0 = <&uart_pins>;
 145                         pinctrl-names = "default";
 146                         compatible = "ns16550a";
 147                         reg = <0x6 0x00100000 0x20>;
 148                         clocks = <&ahb_clk>;
 149                         reg-io-width = <4>;
 150                         reg-shift = <2>;
 151                         interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
 152
 153                         status = "disabled";
 154                 };
 155
 156                 uart1: serial@600102000 {
 157                         pinctrl-0 = <&uart2_pins>;
 158                         pinctrl-names = "default";
 159                         compatible = "ns16550a";
 160                         reg = <0x6 0x00102000 0x20>;
 161                         clocks = <&ahb_clk>;
 162                         reg-io-width = <4>;
 163                         reg-shift = <2>;
 164                         interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 165
 166                         status = "disabled";
 167                 };
 168
 169                 spi0: spi@600104000 {
 170                         #address-cells = <1>;
 171                         #size-cells = <0>;
 172                         compatible = "microchip,sparx5-spi";
 173                         reg = <0x6 0x00104000 0x40>;
 174                         num-cs = <16>;
 175                         reg-io-width = <4>;
 176                         reg-shift = <2>;
 177                         clocks = <&ahb_clk>;
 178                         interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 179                         status = "disabled";
 180                 };
 181
 182                 timer1: timer@600105000 {
 183                         compatible = "snps,dw-apb-timer";
 184                         reg = <0x6 0x00105000 0x1000>;
 185                         clocks = <&ahb_clk>;
 186                         clock-names = "timer";
 187                         interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
 188                 };
 189
 190                 sdhci0: mmc@600800000 {
 191                         compatible = "microchip,dw-sparx5-sdhci";
 192                         status = "disabled";
 193                         reg = <0x6 0x00800000 0x1000>;
 194                         pinctrl-0 = <&emmc_pins>;
 195                         pinctrl-names = "default";
 196                         clocks = <&clks CLK_ID_AUX1>;
 197                         clock-names = "core";
 198                         assigned-clocks = <&clks CLK_ID_AUX1>;
 199                         assigned-clock-rates = <800000000>;
 200                         interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 201                         bus-width = <8>;
 202                 };
 203
 204                 gpio: pinctrl@6110101e0 {
 205                         compatible = "microchip,sparx5-pinctrl";
 206                         reg = <0x6 0x110101e0 0x90>, <0x6 0x10508010 0x100>;
 207                         gpio-controller;
 208                         #gpio-cells = <2>;
 209                         gpio-ranges = <&gpio 0 0 64>;
 210                         interrupt-controller;
 211                         interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 212                         #interrupt-cells = <2>;
 213
 214                         cs1_pins: cs1-pins {
 215                                 pins = "GPIO_16";
 216                                 function = "si";
 217                         };
 218
 219                         cs2_pins: cs2-pins {
 220                                 pins = "GPIO_17";
 221                                 function = "si";
 222                         };
 223
 224                         cs3_pins: cs3-pins {
 225                                 pins = "GPIO_18";
 226                                 function = "si";
 227                         };
 228
 229                         si2_pins: si2-pins {
 230                                 pins = "GPIO_39", "GPIO_40", "GPIO_41";
 231                                 function = "si2";
 232                         };
 233
 234                         sgpio0_pins: sgpio-pins {
 235                                 pins = "GPIO_0", "GPIO_1", "GPIO_2", "GPIO_3";
 236                                 function = "sg0";
 237                         };
 238
 239                         sgpio1_pins: sgpio1-pins {
 240                                 pins = "GPIO_4", "GPIO_5", "GPIO_12", "GPIO_13";
 241                                 function = "sg1";
 242                         };
 243
 244                         sgpio2_pins: sgpio2-pins {
 245                                 pins = "GPIO_30", "GPIO_31", "GPIO_32",
 246                                        "GPIO_33";
 247                                 function = "sg2";
 248                         };
 249
 250                         uart_pins: uart-pins {
 251                                 pins = "GPIO_10", "GPIO_11";
 252                                 function = "uart";
 253                         };
 254
 255                         uart2_pins: uart2-pins {
 256                                 pins = "GPIO_26", "GPIO_27";
 257                                 function = "uart2";
 258                         };
 259
 260                         i2c_pins: i2c-pins {
 261                                 pins = "GPIO_14", "GPIO_15";
 262                                 function = "twi";
 263                         };
 264
 265                         i2c2_pins: i2c2-pins {
 266                                 pins = "GPIO_28", "GPIO_29";
 267                                 function = "twi2";
 268                         };
 269
 270                         emmc_pins: emmc-pins {
 271                                 pins = "GPIO_34", "GPIO_35", "GPIO_36",
 272                                         "GPIO_37", "GPIO_38", "GPIO_39",
 273                                         "GPIO_40", "GPIO_41", "GPIO_42",
 274                                         "GPIO_43", "GPIO_44", "GPIO_45",
 275                                         "GPIO_46", "GPIO_47";
 276                                 function = "emmc";
 277                         };
 278                 };
 279
 280                 sgpio0: gpio@61101036c {
 281                         #address-cells = <1>;
 282                         #size-cells = <0>;
 283                         compatible = "microchip,sparx5-sgpio";
 284                         status = "disabled";
 285                         clocks = <&sys_clk>;
 286                         pinctrl-0 = <&sgpio0_pins>;
 287                         pinctrl-names = "default";
 288                         reg = <0x6 0x1101036c 0x100>;
 289                         sgpio_in0: gpio@0 {
 290                                 compatible = "microchip,sparx5-sgpio-bank";
 291                                 reg = <0>;
 292                                 gpio-controller;
 293                                 #gpio-cells = <3>;
 294                                 ngpios = <96>;
 295                         };
 296                         sgpio_out0: gpio@1 {
 297                                 compatible = "microchip,sparx5-sgpio-bank";
 298                                 reg = <1>;
 299                                 gpio-controller;
 300                                 #gpio-cells = <3>;
 301                                 ngpios = <96>;
 302                         };
 303                 };
 304
 305                 sgpio1: gpio@611010484 {
 306                         #address-cells = <1>;
 307                         #size-cells = <0>;
 308                         compatible = "microchip,sparx5-sgpio";
 309                         status = "disabled";
 310                         clocks = <&sys_clk>;
 311                         pinctrl-0 = <&sgpio1_pins>;
 312                         pinctrl-names = "default";
 313                         reg = <0x6 0x11010484 0x100>;
 314                         sgpio_in1: gpio@0 {
 315                                 compatible = "microchip,sparx5-sgpio-bank";
 316                                 reg = <0>;
 317                                 gpio-controller;
 318                                 #gpio-cells = <3>;
 319                                 ngpios = <96>;
 320                         };
 321                         sgpio_out1: gpio@1 {
 322                                 compatible = "microchip,sparx5-sgpio-bank";
 323                                 reg = <1>;
 324                                 gpio-controller;
 325                                 #gpio-cells = <3>;
 326                                 ngpios = <96>;
 327                         };
 328                 };
 329
 330                 sgpio2: gpio@61101059c {
 331                         #address-cells = <1>;
 332                         #size-cells = <0>;
 333                         compatible = "microchip,sparx5-sgpio";
 334                         status = "disabled";
 335                         clocks = <&sys_clk>;
 336                         pinctrl-0 = <&sgpio2_pins>;
 337                         pinctrl-names = "default";
 338                         reg = <0x6 0x1101059c 0x100>;
 339                         sgpio_in2: gpio@0 {
 340                                 reg = <0>;
 341                                 compatible = "microchip,sparx5-sgpio-bank";
 342                                 gpio-controller;
 343                                 #gpio-cells = <3>;
 344                                 ngpios = <96>;
 345                         };
 346                         sgpio_out2: gpio@1 {
 347                                 compatible = "microchip,sparx5-sgpio-bank";
 348                                 reg = <1>;
 349                                 gpio-controller;
 350                                 #gpio-cells = <3>;
 351                                 ngpios = <96>;
 352                         };
 353                 };
 354
 355                 i2c0: i2c@600101000 {
 356                         compatible = "snps,designware-i2c";
 357                         status = "disabled";
 358                         pinctrl-0 = <&i2c_pins>;
 359                         pinctrl-names = "default";
 360                         reg = <0x6 0x00101000 0x100>;
 361                         #address-cells = <1>;
 362                         #size-cells = <0>;
 363                         interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 364                         i2c-sda-hold-time-ns = <300>;
 365                         clock-frequency = <100000>;
 366                         clocks = <&ahb_clk>;
 367                 };
 368
 369                 i2c1: i2c@600103000 {
 370                         compatible = "snps,designware-i2c";
 371                         status = "disabled";
 372                         pinctrl-0 = <&i2c2_pins>;
 373                         pinctrl-names = "default";
 374                         reg = <0x6 0x00103000 0x100>;
 375                         #address-cells = <1>;
 376                         #size-cells = <0>;
 377                         interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 378                         i2c-sda-hold-time-ns = <300>;
 379                         clock-frequency = <100000>;
 380                         clocks = <&ahb_clk>;
 381                 };
 382
 383                 tmon0: tmon@610508110 {
 384                         compatible = "microchip,sparx5-temp";
 385                         reg = <0x6 0x10508110 0xc>;
 386                         #thermal-sensor-cells = <0>;
 387                         clocks = <&ahb_clk>;
 388                 };
 389         };
 390 };