arch/arm64/boot/dts/mediatek/mt7622.dtsi

   1 /*
   2  * Copyright (c) 2017 MediaTek Inc.
   3  * Author: Ming Huang <ming.huang@mediatek.com>
   4  *         Sean Wang <sean.wang@mediatek.com>
   5  *
   6  * SPDX-License-Identifier: (GPL-2.0 OR MIT)
   7  */
   8
   9 #include <dt-bindings/interrupt-controller/irq.h>
  10 #include <dt-bindings/interrupt-controller/arm-gic.h>
  11 #include <dt-bindings/clock/mt7622-clk.h>
  12 #include <dt-bindings/phy/phy.h>
  13 #include <dt-bindings/power/mt7622-power.h>
  14 #include <dt-bindings/reset/mt7622-reset.h>
  15 #include <dt-bindings/thermal/thermal.h>
  16
  17 / {
  18         compatible = "mediatek,mt7622";
  19         interrupt-parent = <&sysirq>;
  20         #address-cells = <2>;
  21         #size-cells = <2>;
  22
  23         cpu_opp_table: opp-table {
  24                 compatible = "operating-points-v2";
  25                 opp-shared;
  26                 opp-300000000 {
  27                         opp-hz = /bits/ 64 <30000000>;
  28                         opp-microvolt = <950000>;
  29                 };
  30
  31                 opp-437500000 {
  32                         opp-hz = /bits/ 64 <437500000>;
  33                         opp-microvolt = <1000000>;
  34                 };
  35
  36                 opp-600000000 {
  37                         opp-hz = /bits/ 64 <600000000>;
  38                         opp-microvolt = <1050000>;
  39                 };
  40
  41                 opp-812500000 {
  42                         opp-hz = /bits/ 64 <812500000>;
  43                         opp-microvolt = <1100000>;
  44                 };
  45
  46                 opp-1025000000 {
  47                         opp-hz = /bits/ 64 <1025000000>;
  48                         opp-microvolt = <1150000>;
  49                 };
  50
  51                 opp-1137500000 {
  52                         opp-hz = /bits/ 64 <1137500000>;
  53                         opp-microvolt = <1200000>;
  54                 };
  55
  56                 opp-1262500000 {
  57                         opp-hz = /bits/ 64 <1262500000>;
  58                         opp-microvolt = <1250000>;
  59                 };
  60
  61                 opp-1350000000 {
  62                         opp-hz = /bits/ 64 <1350000000>;
  63                         opp-microvolt = <1310000>;
  64                 };
  65         };
  66
  67         cpus {
  68                 #address-cells = <2>;
  69                 #size-cells = <0>;
  70
  71                 cpu0: cpu@0 {
  72                         device_type = "cpu";
  73                         compatible = "arm,cortex-a53";
  74                         reg = <0x0 0x0>;
  75                         clocks = <&infracfg CLK_INFRA_MUX1_SEL>,
  76                                  <&apmixedsys CLK_APMIXED_MAIN_CORE_EN>;
  77                         clock-names = "cpu", "intermediate";
  78                         operating-points-v2 = <&cpu_opp_table>;
  79                         #cooling-cells = <2>;
  80                         enable-method = "psci";
  81                         clock-frequency = <1300000000>;
  82                         cci-control-port = <&cci_control2>;
  83                 };
  84
  85                 cpu1: cpu@1 {
  86                         device_type = "cpu";
  87                         compatible = "arm,cortex-a53";
  88                         reg = <0x0 0x1>;
  89                         clocks = <&infracfg CLK_INFRA_MUX1_SEL>,
  90                                  <&apmixedsys CLK_APMIXED_MAIN_CORE_EN>;
  91                         clock-names = "cpu", "intermediate";
  92                         operating-points-v2 = <&cpu_opp_table>;
  93                         #cooling-cells = <2>;
  94                         enable-method = "psci";
  95                         clock-frequency = <1300000000>;
  96                         cci-control-port = <&cci_control2>;
  97                 };
  98         };
  99
 100         pwrap_clk: dummy40m {
 101                 compatible = "fixed-clock";
 102                 clock-frequency = <40000000>;
 103                 #clock-cells = <0>;
 104         };
 105
 106         clk25m: oscillator {
 107                 compatible = "fixed-clock";
 108                 #clock-cells = <0>;
 109                 clock-frequency = <25000000>;
 110                 clock-output-names = "clkxtal";
 111         };
 112
 113         psci {
 114                 compatible  = "arm,psci-0.2";
 115                 method      = "smc";
 116         };
 117
 118         pmu {
 119                 compatible = "arm,cortex-a53-pmu";
 120                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_LOW>,
 121                              <GIC_SPI 9 IRQ_TYPE_LEVEL_LOW>;
 122                 interrupt-affinity = <&cpu0>, <&cpu1>;
 123         };
 124
 125         reserved-memory {
 126                 #address-cells = <2>;
 127                 #size-cells = <2>;
 128                 ranges;
 129
 130                 /* 192 KiB reserved for ARM Trusted Firmware (BL31) */
 131                 secmon_reserved: secmon@43000000 {
 132                         reg = <0 0x43000000 0 0x30000>;
 133                         no-map;
 134                 };
 135         };
 136
 137         thermal-zones {
 138                 cpu_thermal: cpu-thermal {
 139                         polling-delay-passive = <1000>;
 140                         polling-delay = <1000>;
 141
 142                         thermal-sensors = <&thermal 0>;
 143
 144                         trips {
 145                                 cpu_passive: cpu-passive {
 146                                         temperature = <47000>;
 147                                         hysteresis = <2000>;
 148                                         type = "passive";
 149                                 };
 150
 151                                 cpu_active: cpu-active {
 152                                         temperature = <67000>;
 153                                         hysteresis = <2000>;
 154                                         type = "active";
 155                                 };
 156
 157                                 cpu_hot: cpu-hot {
 158                                         temperature = <87000>;
 159                                         hysteresis = <2000>;
 160                                         type = "hot";
 161                                 };
 162
 163                                 cpu-crit {
 164                                         temperature = <107000>;
 165                                         hysteresis = <2000>;
 166                                         type = "critical";
 167                                 };
 168                         };
 169
 170                         cooling-maps {
 171                                 map0 {
 172                                         trip = <&cpu_passive>;
 173                                         cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 174                                                          <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 175                                 };
 176
 177                                 map1 {
 178                                         trip = <&cpu_active>;
 179                                         cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 180                                                          <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 181                                 };
 182
 183                                 map2 {
 184                                         trip = <&cpu_hot>;
 185                                         cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 186                                                          <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 187                                 };
 188                         };
 189                 };
 190         };
 191
 192         timer {
 193                 compatible = "arm,armv8-timer";
 194                 interrupt-parent = <&gic>;
 195                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
 196                               IRQ_TYPE_LEVEL_HIGH)>,
 197                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) |
 198                               IRQ_TYPE_LEVEL_HIGH)>,
 199                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) |
 200                               IRQ_TYPE_LEVEL_HIGH)>,
 201                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) |
 202                               IRQ_TYPE_LEVEL_HIGH)>;
 203         };
 204
 205         infracfg: infracfg@10000000 {
 206                 compatible = "mediatek,mt7622-infracfg",
 207                              "syscon";
 208                 reg = <0 0x10000000 0 0x1000>;
 209                 #clock-cells = <1>;
 210                 #reset-cells = <1>;
 211         };
 212
 213         pwrap: pwrap@10001000 {
 214                 compatible = "mediatek,mt7622-pwrap";
 215                 reg = <0 0x10001000 0 0x250>;
 216                 reg-names = "pwrap";
 217                 clocks = <&infracfg CLK_INFRA_PMIC_PD>, <&pwrap_clk>;
 218                 clock-names = "spi", "wrap";
 219                 resets = <&infracfg MT7622_INFRA_PMIC_WRAP_RST>;
 220                 reset-names = "pwrap";
 221                 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
 222                 status = "disabled";
 223         };
 224
 225         pericfg: pericfg@10002000 {
 226                 compatible = "mediatek,mt7622-pericfg",
 227                              "syscon";
 228                 reg = <0 0x10002000 0 0x1000>;
 229                 #clock-cells = <1>;
 230                 #reset-cells = <1>;
 231         };
 232
 233         scpsys: power-controller@10006000 {
 234                 compatible = "mediatek,mt7622-scpsys",
 235                              "syscon";
 236                 #power-domain-cells = <1>;
 237                 reg = <0 0x10006000 0 0x1000>;
 238                 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_LOW>,
 239                              <GIC_SPI 166 IRQ_TYPE_LEVEL_LOW>,
 240                              <GIC_SPI 167 IRQ_TYPE_LEVEL_LOW>,
 241                              <GIC_SPI 168 IRQ_TYPE_LEVEL_LOW>;
 242                 infracfg = <&infracfg>;
 243                 clocks = <&topckgen CLK_TOP_HIF_SEL>;
 244                 clock-names = "hif_sel";
 245         };
 246
 247         cir: cir@10009000 {
 248                 compatible = "mediatek,mt7622-cir";
 249                 reg = <0 0x10009000 0 0x1000>;
 250                 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_LOW>;
 251                 clocks = <&infracfg CLK_INFRA_IRRX_PD>,
 252                          <&topckgen CLK_TOP_AXI_SEL>;
 253                 clock-names = "clk", "bus";
 254                 status = "disabled";
 255         };
 256
 257         sysirq: interrupt-controller@10200620 {
 258                 compatible = "mediatek,mt7622-sysirq",
 259                              "mediatek,mt6577-sysirq";
 260                 interrupt-controller;
 261                 #interrupt-cells = <3>;
 262                 interrupt-parent = <&gic>;
 263                 reg = <0 0x10200620 0 0x20>;
 264         };
 265
 266         efuse: efuse@10206000 {
 267                 compatible = "mediatek,mt7622-efuse",
 268                              "mediatek,efuse";
 269                 reg = <0 0x10206000 0 0x1000>;
 270                 #address-cells = <1>;
 271                 #size-cells = <1>;
 272
 273                 thermal_calibration: calib@198 {
 274                         reg = <0x198 0xc>;
 275                 };
 276         };
 277
 278         apmixedsys: apmixedsys@10209000 {
 279                 compatible = "mediatek,mt7622-apmixedsys",
 280                              "syscon";
 281                 reg = <0 0x10209000 0 0x1000>;
 282                 #clock-cells = <1>;
 283         };
 284
 285         topckgen: topckgen@10210000 {
 286                 compatible = "mediatek,mt7622-topckgen",
 287                              "syscon";
 288                 reg = <0 0x10210000 0 0x1000>;
 289                 #clock-cells = <1>;
 290         };
 291
 292         rng: rng@1020f000 {
 293                 compatible = "mediatek,mt7622-rng",
 294                              "mediatek,mt7623-rng";
 295                 reg = <0 0x1020f000 0 0x1000>;
 296                 clocks = <&infracfg CLK_INFRA_TRNG>;
 297                 clock-names = "rng";
 298         };
 299
 300         pio: pinctrl@10211000 {
 301                 compatible = "mediatek,mt7622-pinctrl";
 302                 reg = <0 0x10211000 0 0x1000>,
 303                       <0 0x10005000 0 0x1000>;
 304                 reg-names = "base", "eint";
 305                 gpio-controller;
 306                 #gpio-cells = <2>;
 307                 gpio-ranges = <&pio 0 0 103>;
 308                 interrupt-controller;
 309                 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
 310                 interrupt-parent = <&gic>;
 311                 #interrupt-cells = <2>;
 312         };
 313
 314         watchdog: watchdog@10212000 {
 315                 compatible = "mediatek,mt7622-wdt",
 316                              "mediatek,mt6589-wdt";
 317                 reg = <0 0x10212000 0 0x800>;
 318         };
 319
 320         rtc: rtc@10212800 {
 321                 compatible = "mediatek,mt7622-rtc",
 322                              "mediatek,soc-rtc";
 323                 reg = <0 0x10212800 0 0x200>;
 324                 interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_LOW>;
 325                 clocks = <&topckgen CLK_TOP_RTC>;
 326                 clock-names = "rtc";
 327         };
 328
 329         gic: interrupt-controller@10300000 {
 330                 compatible = "arm,gic-400";
 331                 interrupt-controller;
 332                 #interrupt-cells = <3>;
 333                 interrupt-parent = <&gic>;
 334                 reg = <0 0x10310000 0 0x1000>,
 335                       <0 0x10320000 0 0x1000>,
 336                       <0 0x10340000 0 0x2000>,
 337                       <0 0x10360000 0 0x2000>;
 338         };
 339
 340         cci: cci@10390000 {
 341                 compatible = "arm,cci-400";
 342                 #address-cells = <1>;
 343                 #size-cells = <1>;
 344                 reg = <0 0x10390000 0 0x1000>;
 345                 ranges = <0 0 0x10390000 0x10000>;
 346
 347                 cci_control0: slave-if@1000 {
 348                         compatible = "arm,cci-400-ctrl-if";
 349                         interface-type = "ace-lite";
 350                         reg = <0x1000 0x1000>;
 351                 };
 352
 353                 cci_control1: slave-if@4000 {
 354                         compatible = "arm,cci-400-ctrl-if";
 355                         interface-type = "ace";
 356                         reg = <0x4000 0x1000>;
 357                 };
 358
 359                 cci_control2: slave-if@5000 {
 360                         compatible = "arm,cci-400-ctrl-if";
 361                         interface-type = "ace";
 362                         reg = <0x5000 0x1000>;
 363                 };
 364
 365                 pmu@9000 {
 366                         compatible = "arm,cci-400-pmu,r1";
 367                         reg = <0x9000 0x5000>;
 368                         interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
 369                                      <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
 370                                      <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
 371                                      <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
 372                                      <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 373                 };
 374         };
 375
 376         auxadc: adc@11001000 {
 377                 compatible = "mediatek,mt7622-auxadc";
 378                 reg = <0 0x11001000 0 0x1000>;
 379                 clocks = <&pericfg CLK_PERI_AUXADC_PD>;
 380                 clock-names = "main";
 381                 #io-channel-cells = <1>;
 382         };
 383
 384         uart0: serial@11002000 {
 385                 compatible = "mediatek,mt7622-uart",
 386                              "mediatek,mt6577-uart";
 387                 reg = <0 0x11002000 0 0x400>;
 388                 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
 389                 clocks = <&topckgen CLK_TOP_UART_SEL>,
 390                          <&pericfg CLK_PERI_UART0_PD>;
 391                 clock-names = "baud", "bus";
 392                 status = "disabled";
 393         };
 394
 395         uart1: serial@11003000 {
 396                 compatible = "mediatek,mt7622-uart",
 397                              "mediatek,mt6577-uart";
 398                 reg = <0 0x11003000 0 0x400>;
 399                 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>;
 400                 clocks = <&topckgen CLK_TOP_UART_SEL>,
 401                          <&pericfg CLK_PERI_UART1_PD>;
 402                 clock-names = "baud", "bus";
 403                 status = "disabled";
 404         };
 405
 406         uart2: serial@11004000 {
 407                 compatible = "mediatek,mt7622-uart",
 408                              "mediatek,mt6577-uart";
 409                 reg = <0 0x11004000 0 0x400>;
 410                 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>;
 411                 clocks = <&topckgen CLK_TOP_UART_SEL>,
 412                          <&pericfg CLK_PERI_UART2_PD>;
 413                 clock-names = "baud", "bus";
 414                 status = "disabled";
 415         };
 416
 417         uart3: serial@11005000 {
 418                 compatible = "mediatek,mt7622-uart",
 419                              "mediatek,mt6577-uart";
 420                 reg = <0 0x11005000 0 0x400>;
 421                 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_LOW>;
 422                 clocks = <&topckgen CLK_TOP_UART_SEL>,
 423                          <&pericfg CLK_PERI_UART3_PD>;
 424                 clock-names = "baud", "bus";
 425                 status = "disabled";
 426         };
 427
 428         pwm: pwm@11006000 {
 429                 compatible = "mediatek,mt7622-pwm";
 430                 reg = <0 0x11006000 0 0x1000>;
 431                 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>;
 432                 clocks = <&topckgen CLK_TOP_PWM_SEL>,
 433                          <&pericfg CLK_PERI_PWM_PD>,
 434                          <&pericfg CLK_PERI_PWM1_PD>,
 435                          <&pericfg CLK_PERI_PWM2_PD>,
 436                          <&pericfg CLK_PERI_PWM3_PD>,
 437                          <&pericfg CLK_PERI_PWM4_PD>,
 438                          <&pericfg CLK_PERI_PWM5_PD>,
 439                          <&pericfg CLK_PERI_PWM6_PD>;
 440                 clock-names = "top", "main", "pwm1", "pwm2", "pwm3", "pwm4",
 441                               "pwm5", "pwm6";
 442                 status = "disabled";
 443         };
 444
 445         i2c0: i2c@11007000 {
 446                 compatible = "mediatek,mt7622-i2c";
 447                 reg = <0 0x11007000 0 0x90>,
 448                       <0 0x11000100 0 0x80>;
 449                 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>;
 450                 clock-div = <16>;
 451                 clocks = <&pericfg CLK_PERI_I2C0_PD>,
 452                          <&pericfg CLK_PERI_AP_DMA_PD>;
 453                 clock-names = "main", "dma";
 454                 #address-cells = <1>;
 455                 #size-cells = <0>;
 456                 status = "disabled";
 457         };
 458
 459         i2c1: i2c@11008000 {
 460                 compatible = "mediatek,mt7622-i2c";
 461                 reg = <0 0x11008000 0 0x90>,
 462                       <0 0x11000180 0 0x80>;
 463                 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>;
 464                 clock-div = <16>;
 465                 clocks = <&pericfg CLK_PERI_I2C1_PD>,
 466                          <&pericfg CLK_PERI_AP_DMA_PD>;
 467                 clock-names = "main", "dma";
 468                 #address-cells = <1>;
 469                 #size-cells = <0>;
 470                 status = "disabled";
 471         };
 472
 473         i2c2: i2c@11009000 {
 474                 compatible = "mediatek,mt7622-i2c";
 475                 reg = <0 0x11009000 0 0x90>,
 476                       <0 0x11000200 0 0x80>;
 477                 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>;
 478                 clock-div = <16>;
 479                 clocks = <&pericfg CLK_PERI_I2C2_PD>,
 480                          <&pericfg CLK_PERI_AP_DMA_PD>;
 481                 clock-names = "main", "dma";
 482                 #address-cells = <1>;
 483                 #size-cells = <0>;
 484                 status = "disabled";
 485         };
 486
 487         spi0: spi@1100a000 {
 488                 compatible = "mediatek,mt7622-spi";
 489                 reg = <0 0x1100a000 0 0x100>;
 490                 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_LOW>;
 491                 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
 492                          <&topckgen CLK_TOP_SPI0_SEL>,
 493                          <&pericfg CLK_PERI_SPI0_PD>;
 494                 clock-names = "parent-clk", "sel-clk", "spi-clk";
 495                 #address-cells = <1>;
 496                 #size-cells = <0>;
 497                 status = "disabled";
 498         };
 499
 500         thermal: thermal@1100b000 {
 501                 #thermal-sensor-cells = <1>;
 502                 compatible = "mediatek,mt7622-thermal";
 503                 reg = <0 0x1100b000 0 0x1000>;
 504                 interrupts = <0 78 IRQ_TYPE_LEVEL_LOW>;
 505                 clocks = <&pericfg CLK_PERI_THERM_PD>,
 506                          <&pericfg CLK_PERI_AUXADC_PD>;
 507                 clock-names = "therm", "auxadc";
 508                 resets = <&pericfg MT7622_PERI_THERM_SW_RST>;
 509                 reset-names = "therm";
 510                 mediatek,auxadc = <&auxadc>;
 511                 mediatek,apmixedsys = <&apmixedsys>;
 512                 nvmem-cells = <&thermal_calibration>;
 513                 nvmem-cell-names = "calibration-data";
 514         };
 515
 516         btif: serial@1100c000 {
 517                 compatible = "mediatek,mt7622-btif",
 518                              "mediatek,mtk-btif";
 519                 reg = <0 0x1100c000 0 0x1000>;
 520                 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_LOW>;
 521                 clocks = <&pericfg CLK_PERI_BTIF_PD>;
 522                 clock-names = "main";
 523                 reg-shift = <2>;
 524                 reg-io-width = <4>;
 525                 status = "disabled";
 526
 527                 bluetooth {
 528                         compatible = "mediatek,mt7622-bluetooth";
 529                         power-domains = <&scpsys MT7622_POWER_DOMAIN_WB>;
 530                         clocks = <&clk25m>;
 531                         clock-names = "ref";
 532                 };
 533         };
 534
 535         nandc: nfi@1100d000 {
 536                 compatible = "mediatek,mt7622-nfc";
 537                 reg = <0 0x1100D000 0 0x1000>;
 538                 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_LOW>;
 539                 clocks = <&pericfg CLK_PERI_NFI_PD>,
 540                          <&pericfg CLK_PERI_SNFI_PD>;
 541                 clock-names = "nfi_clk", "pad_clk";
 542                 ecc-engine = <&bch>;
 543                 #address-cells = <1>;
 544                 #size-cells = <0>;
 545                 status = "disabled";
 546         };
 547
 548         bch: ecc@1100e000 {
 549                 compatible = "mediatek,mt7622-ecc";
 550                 reg = <0 0x1100e000 0 0x1000>;
 551                 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_LOW>;
 552                 clocks = <&pericfg CLK_PERI_NFIECC_PD>;
 553                 clock-names = "nfiecc_clk";
 554                 status = "disabled";
 555         };
 556
 557         nor_flash: spi@11014000 {
 558                 compatible = "mediatek,mt7622-nor",
 559                              "mediatek,mt8173-nor";
 560                 reg = <0 0x11014000 0 0xe0>;
 561                 clocks = <&pericfg CLK_PERI_FLASH_PD>,
 562                          <&topckgen CLK_TOP_FLASH_SEL>;
 563                 clock-names = "spi", "sf";
 564                 #address-cells = <1>;
 565                 #size-cells = <0>;
 566                 status = "disabled";
 567         };
 568
 569         spi1: spi@11016000 {
 570                 compatible = "mediatek,mt7622-spi";
 571                 reg = <0 0x11016000 0 0x100>;
 572                 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_LOW>;
 573                 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
 574                          <&topckgen CLK_TOP_SPI1_SEL>,
 575                          <&pericfg CLK_PERI_SPI1_PD>;
 576                 clock-names = "parent-clk", "sel-clk", "spi-clk";
 577                 #address-cells = <1>;
 578                 #size-cells = <0>;
 579                 status = "disabled";
 580         };
 581
 582         uart4: serial@11019000 {
 583                 compatible = "mediatek,mt7622-uart",
 584                              "mediatek,mt6577-uart";
 585                 reg = <0 0x11019000 0 0x400>;
 586                 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_LOW>;
 587                 clocks = <&topckgen CLK_TOP_UART_SEL>,
 588                          <&pericfg CLK_PERI_UART4_PD>;
 589                 clock-names = "baud", "bus";
 590                 status = "disabled";
 591         };
 592
 593         audsys: clock-controller@11220000 {
 594                 compatible = "mediatek,mt7622-audsys", "syscon";
 595                 reg = <0 0x11220000 0 0x2000>;
 596                 #clock-cells = <1>;
 597
 598                 afe: audio-controller {
 599                         compatible = "mediatek,mt7622-audio";
 600                         interrupts =  <GIC_SPI 144 IRQ_TYPE_LEVEL_LOW>,
 601                                       <GIC_SPI 145 IRQ_TYPE_LEVEL_LOW>;
 602                         interrupt-names = "afe", "asys";
 603
 604                         clocks = <&infracfg CLK_INFRA_AUDIO_PD>,
 605                                  <&topckgen CLK_TOP_AUD1_SEL>,
 606                                  <&topckgen CLK_TOP_AUD2_SEL>,
 607                                  <&topckgen CLK_TOP_A1SYS_HP_DIV_PD>,
 608                                  <&topckgen CLK_TOP_A2SYS_HP_DIV_PD>,
 609                                  <&topckgen CLK_TOP_I2S0_MCK_SEL>,
 610                                  <&topckgen CLK_TOP_I2S1_MCK_SEL>,
 611                                  <&topckgen CLK_TOP_I2S2_MCK_SEL>,
 612                                  <&topckgen CLK_TOP_I2S3_MCK_SEL>,
 613                                  <&topckgen CLK_TOP_I2S0_MCK_DIV>,
 614                                  <&topckgen CLK_TOP_I2S1_MCK_DIV>,
 615                                  <&topckgen CLK_TOP_I2S2_MCK_DIV>,
 616                                  <&topckgen CLK_TOP_I2S3_MCK_DIV>,
 617                                  <&topckgen CLK_TOP_I2S0_MCK_DIV_PD>,
 618                                  <&topckgen CLK_TOP_I2S1_MCK_DIV_PD>,
 619                                  <&topckgen CLK_TOP_I2S2_MCK_DIV_PD>,
 620                                  <&topckgen CLK_TOP_I2S3_MCK_DIV_PD>,
 621                                  <&audsys CLK_AUDIO_I2SO1>,
 622                                  <&audsys CLK_AUDIO_I2SO2>,
 623                                  <&audsys CLK_AUDIO_I2SO3>,
 624                                  <&audsys CLK_AUDIO_I2SO4>,
 625                                  <&audsys CLK_AUDIO_I2SIN1>,
 626                                  <&audsys CLK_AUDIO_I2SIN2>,
 627                                  <&audsys CLK_AUDIO_I2SIN3>,
 628                                  <&audsys CLK_AUDIO_I2SIN4>,
 629                                  <&audsys CLK_AUDIO_ASRCO1>,
 630                                  <&audsys CLK_AUDIO_ASRCO2>,
 631                                  <&audsys CLK_AUDIO_ASRCO3>,
 632                                  <&audsys CLK_AUDIO_ASRCO4>,
 633                                  <&audsys CLK_AUDIO_AFE>,
 634                                  <&audsys CLK_AUDIO_AFE_CONN>,
 635                                  <&audsys CLK_AUDIO_A1SYS>,
 636                                  <&audsys CLK_AUDIO_A2SYS>;
 637
 638                         clock-names = "infra_sys_audio_clk",
 639                                       "top_audio_mux1_sel",
 640                                       "top_audio_mux2_sel",
 641                                       "top_audio_a1sys_hp",
 642                                       "top_audio_a2sys_hp",
 643                                       "i2s0_src_sel",
 644                                       "i2s1_src_sel",
 645                                       "i2s2_src_sel",
 646                                       "i2s3_src_sel",
 647                                       "i2s0_src_div",
 648                                       "i2s1_src_div",
 649                                       "i2s2_src_div",
 650                                       "i2s3_src_div",
 651                                       "i2s0_mclk_en",
 652                                       "i2s1_mclk_en",
 653                                       "i2s2_mclk_en",
 654                                       "i2s3_mclk_en",
 655                                       "i2so0_hop_ck",
 656                                       "i2so1_hop_ck",
 657                                       "i2so2_hop_ck",
 658                                       "i2so3_hop_ck",
 659                                       "i2si0_hop_ck",
 660                                       "i2si1_hop_ck",
 661                                       "i2si2_hop_ck",
 662                                       "i2si3_hop_ck",
 663                                       "asrc0_out_ck",
 664                                       "asrc1_out_ck",
 665                                       "asrc2_out_ck",
 666                                       "asrc3_out_ck",
 667                                       "audio_afe_pd",
 668                                       "audio_afe_conn_pd",
 669                                       "audio_a1sys_pd",
 670                                       "audio_a2sys_pd";
 671
 672                         assigned-clocks = <&topckgen CLK_TOP_A1SYS_HP_SEL>,
 673                                           <&topckgen CLK_TOP_A2SYS_HP_SEL>,
 674                                           <&topckgen CLK_TOP_A1SYS_HP_DIV>,
 675                                           <&topckgen CLK_TOP_A2SYS_HP_DIV>;
 676                         assigned-clock-parents = <&topckgen CLK_TOP_AUD1PLL>,
 677                                                  <&topckgen CLK_TOP_AUD2PLL>;
 678                         assigned-clock-rates = <0>, <0>, <49152000>, <45158400>;
 679                 };
 680         };
 681
 682         mmc0: mmc@11230000 {
 683                 compatible = "mediatek,mt7622-mmc";
 684                 reg = <0 0x11230000 0 0x1000>;
 685                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>;
 686                 clocks = <&pericfg CLK_PERI_MSDC30_0_PD>,
 687                          <&topckgen CLK_TOP_MSDC50_0_SEL>;
 688                 clock-names = "source", "hclk";
 689                 resets = <&pericfg MT7622_PERI_MSDC0_SW_RST>;
 690                 reset-names = "hrst";
 691                 status = "disabled";
 692         };
 693
 694         mmc1: mmc@11240000 {
 695                 compatible = "mediatek,mt7622-mmc";
 696                 reg = <0 0x11240000 0 0x1000>;
 697                 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_LOW>;
 698                 clocks = <&pericfg CLK_PERI_MSDC30_1_PD>,
 699                          <&topckgen CLK_TOP_AXI_SEL>;
 700                 clock-names = "source", "hclk";
 701                 resets = <&pericfg MT7622_PERI_MSDC1_SW_RST>;
 702                 reset-names = "hrst";
 703                 status = "disabled";
 704         };
 705
 706         wmac: wmac@18000000 {
 707                 compatible = "mediatek,mt7622-wmac";
 708                 reg = <0 0x18000000 0 0x100000>;
 709                 interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_LOW>;
 710
 711                 mediatek,infracfg = <&infracfg>;
 712                 status = "disabled";
 713
 714                 power-domains = <&scpsys MT7622_POWER_DOMAIN_WB>;
 715         };
 716
 717         ssusbsys: ssusbsys@1a000000 {
 718                 compatible = "mediatek,mt7622-ssusbsys",
 719                              "syscon";
 720                 reg = <0 0x1a000000 0 0x1000>;
 721                 #clock-cells = <1>;
 722                 #reset-cells = <1>;
 723         };
 724
 725         ssusb: usb@1a0c0000 {
 726                 compatible = "mediatek,mt7622-xhci",
 727                              "mediatek,mtk-xhci";
 728                 reg = <0 0x1a0c0000 0 0x01000>,
 729                       <0 0x1a0c4700 0 0x0100>;
 730                 reg-names = "mac", "ippc";
 731                 interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_LOW>;
 732                 power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF1>;
 733                 clocks = <&ssusbsys CLK_SSUSB_SYS_EN>,
 734                          <&ssusbsys CLK_SSUSB_REF_EN>,
 735                          <&ssusbsys CLK_SSUSB_MCU_EN>,
 736                          <&ssusbsys CLK_SSUSB_DMA_EN>;
 737                 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck";
 738                 phys = <&u2port0 PHY_TYPE_USB2>,
 739                        <&u3port0 PHY_TYPE_USB3>,
 740                        <&u2port1 PHY_TYPE_USB2>;
 741
 742                 status = "disabled";
 743         };
 744
 745         u3phy: t-phy@1a0c4000 {
 746                 compatible = "mediatek,mt7622-tphy",
 747                              "mediatek,generic-tphy-v1";
 748                 reg = <0 0x1a0c4000 0 0x700>;
 749                 #address-cells = <2>;
 750                 #size-cells = <2>;
 751                 ranges;
 752                 status = "disabled";
 753
 754                 u2port0: usb-phy@1a0c4800 {
 755                         reg = <0 0x1a0c4800 0 0x0100>;
 756                         #phy-cells = <1>;
 757                         clocks = <&ssusbsys CLK_SSUSB_U2_PHY_EN>;
 758                         clock-names = "ref";
 759                 };
 760
 761                 u3port0: usb-phy@1a0c4900 {
 762                         reg = <0 0x1a0c4900 0 0x0700>;
 763                         #phy-cells = <1>;
 764                         clocks = <&clk25m>;
 765                         clock-names = "ref";
 766                 };
 767
 768                 u2port1: usb-phy@1a0c5000 {
 769                         reg = <0 0x1a0c5000 0 0x0100>;
 770                         #phy-cells = <1>;
 771                         clocks = <&ssusbsys CLK_SSUSB_U2_PHY_1P_EN>;
 772                         clock-names = "ref";
 773                 };
 774         };
 775
 776         pciesys: pciesys@1a100800 {
 777                 compatible = "mediatek,mt7622-pciesys",
 778                              "syscon";
 779                 reg = <0 0x1a100800 0 0x1000>;
 780                 #clock-cells = <1>;
 781                 #reset-cells = <1>;
 782         };
 783
 784         pcie: pcie@1a140000 {
 785                 compatible = "mediatek,mt7622-pcie";
 786                 device_type = "pci";
 787                 reg = <0 0x1a140000 0 0x1000>,
 788                       <0 0x1a143000 0 0x1000>,
 789                       <0 0x1a145000 0 0x1000>;
 790                 reg-names = "subsys", "port0", "port1";
 791                 #address-cells = <3>;
 792                 #size-cells = <2>;
 793                 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_LOW>,
 794                              <GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>;
 795                 clocks = <&pciesys CLK_PCIE_P0_MAC_EN>,
 796                          <&pciesys CLK_PCIE_P1_MAC_EN>,
 797                          <&pciesys CLK_PCIE_P0_AHB_EN>,
 798                          <&pciesys CLK_PCIE_P0_AHB_EN>,
 799                          <&pciesys CLK_PCIE_P0_AUX_EN>,
 800                          <&pciesys CLK_PCIE_P1_AUX_EN>,
 801                          <&pciesys CLK_PCIE_P0_AXI_EN>,
 802                          <&pciesys CLK_PCIE_P1_AXI_EN>,
 803                          <&pciesys CLK_PCIE_P0_OBFF_EN>,
 804                          <&pciesys CLK_PCIE_P1_OBFF_EN>,
 805                          <&pciesys CLK_PCIE_P0_PIPE_EN>,
 806                          <&pciesys CLK_PCIE_P1_PIPE_EN>;
 807                 clock-names = "sys_ck0", "sys_ck1", "ahb_ck0", "ahb_ck1",
 808                               "aux_ck0", "aux_ck1", "axi_ck0", "axi_ck1",
 809                               "obff_ck0", "obff_ck1", "pipe_ck0", "pipe_ck1";
 810                 power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>;
 811                 bus-range = <0x00 0xff>;
 812                 ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x10000000>;
 813                 status = "disabled";
 814
 815                 pcie0: pcie@0,0 {
 816                         reg = <0x0000 0 0 0 0>;
 817                         #address-cells = <3>;
 818                         #size-cells = <2>;
 819                         #interrupt-cells = <1>;
 820                         ranges;
 821                         status = "disabled";
 822
 823                         interrupt-map-mask = <0 0 0 7>;
 824                         interrupt-map = <0 0 0 1 &pcie_intc0 0>,
 825                                         <0 0 0 2 &pcie_intc0 1>,
 826                                         <0 0 0 3 &pcie_intc0 2>,
 827                                         <0 0 0 4 &pcie_intc0 3>;
 828                         pcie_intc0: interrupt-controller {
 829                                 interrupt-controller;
 830                                 #address-cells = <0>;
 831                                 #interrupt-cells = <1>;
 832                         };
 833                 };
 834
 835                 pcie1: pcie@1,0 {
 836                         reg = <0x0800 0 0 0 0>;
 837                         #address-cells = <3>;
 838                         #size-cells = <2>;
 839                         #interrupt-cells = <1>;
 840                         ranges;
 841                         status = "disabled";
 842
 843                         interrupt-map-mask = <0 0 0 7>;
 844                         interrupt-map = <0 0 0 1 &pcie_intc1 0>,
 845                                         <0 0 0 2 &pcie_intc1 1>,
 846                                         <0 0 0 3 &pcie_intc1 2>,
 847                                         <0 0 0 4 &pcie_intc1 3>;
 848                         pcie_intc1: interrupt-controller {
 849                                 interrupt-controller;
 850                                 #address-cells = <0>;
 851                                 #interrupt-cells = <1>;
 852                         };
 853                 };
 854         };
 855
 856         sata: sata@1a200000 {
 857                 compatible = "mediatek,mt7622-ahci",
 858                              "mediatek,mtk-ahci";
 859                 reg = <0 0x1a200000 0 0x1100>;
 860                 interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>;
 861                 interrupt-names = "hostc";
 862                 clocks = <&pciesys CLK_SATA_AHB_EN>,
 863                          <&pciesys CLK_SATA_AXI_EN>,
 864                          <&pciesys CLK_SATA_ASIC_EN>,
 865                          <&pciesys CLK_SATA_RBC_EN>,
 866                          <&pciesys CLK_SATA_PM_EN>;
 867                 clock-names = "ahb", "axi", "asic", "rbc", "pm";
 868                 phys = <&sata_port PHY_TYPE_SATA>;
 869                 phy-names = "sata-phy";
 870                 ports-implemented = <0x1>;
 871                 power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>;
 872                 resets = <&pciesys MT7622_SATA_AXI_BUS_RST>,
 873                          <&pciesys MT7622_SATA_PHY_SW_RST>,
 874                          <&pciesys MT7622_SATA_PHY_REG_RST>;
 875                 reset-names = "axi", "sw", "reg";
 876                 mediatek,phy-mode = <&pciesys>;
 877                 status = "disabled";
 878         };
 879
 880         sata_phy: t-phy@1a243000 {
 881                 compatible = "mediatek,mt7622-tphy",
 882                              "mediatek,generic-tphy-v1";
 883                 #address-cells = <2>;
 884                 #size-cells = <2>;
 885                 ranges;
 886                 status = "disabled";
 887
 888                 sata_port: sata-phy@1a243000 {
 889                         reg = <0 0x1a243000 0 0x0100>;
 890                         clocks = <&topckgen CLK_TOP_ETH_500M>;
 891                         clock-names = "ref";
 892                         #phy-cells = <1>;
 893                 };
 894         };
 895
 896         ethsys: syscon@1b000000 {
 897                 compatible = "mediatek,mt7622-ethsys",
 898                              "syscon";
 899                 reg = <0 0x1b000000 0 0x1000>;
 900                 #clock-cells = <1>;
 901                 #reset-cells = <1>;
 902         };
 903
 904         hsdma: dma-controller@1b007000 {
 905                 compatible = "mediatek,mt7622-hsdma";
 906                 reg = <0 0x1b007000 0 0x1000>;
 907                 interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_LOW>;
 908                 clocks = <&ethsys CLK_ETH_HSDMA_EN>;
 909                 clock-names = "hsdma";
 910                 power-domains = <&scpsys MT7622_POWER_DOMAIN_ETHSYS>;
 911                 #dma-cells = <1>;
 912         };
 913
 914         eth: ethernet@1b100000 {
 915                 compatible = "mediatek,mt7622-eth",
 916                              "mediatek,mt2701-eth",
 917                              "syscon";
 918                 reg = <0 0x1b100000 0 0x20000>;
 919                 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_LOW>,
 920                              <GIC_SPI 224 IRQ_TYPE_LEVEL_LOW>,
 921                              <GIC_SPI 225 IRQ_TYPE_LEVEL_LOW>;
 922                 clocks = <&topckgen CLK_TOP_ETH_SEL>,
 923                          <&ethsys CLK_ETH_ESW_EN>,
 924                          <&ethsys CLK_ETH_GP0_EN>,
 925                          <&ethsys CLK_ETH_GP1_EN>,
 926                          <&ethsys CLK_ETH_GP2_EN>,
 927                          <&sgmiisys CLK_SGMII_TX250M_EN>,
 928                          <&sgmiisys CLK_SGMII_RX250M_EN>,
 929                          <&sgmiisys CLK_SGMII_CDR_REF>,
 930                          <&sgmiisys CLK_SGMII_CDR_FB>,
 931                          <&topckgen CLK_TOP_SGMIIPLL>,
 932                          <&apmixedsys CLK_APMIXED_ETH2PLL>;
 933                 clock-names = "ethif", "esw", "gp0", "gp1", "gp2",
 934                               "sgmii_tx250m", "sgmii_rx250m",
 935                               "sgmii_cdr_ref", "sgmii_cdr_fb", "sgmii_ck",
 936                               "eth2pll";
 937                 power-domains = <&scpsys MT7622_POWER_DOMAIN_ETHSYS>;
 938                 mediatek,ethsys = <&ethsys>;
 939                 mediatek,sgmiisys = <&sgmiisys>;
 940                 #address-cells = <1>;
 941                 #size-cells = <0>;
 942                 status = "disabled";
 943         };
 944
 945         sgmiisys: sgmiisys@1b128000 {
 946                 compatible = "mediatek,mt7622-sgmiisys",
 947                              "syscon";
 948                 reg = <0 0x1b128000 0 0x3000>;
 949                 #clock-cells = <1>;
 950         };
 951 };