arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts

   1 /*
   2  * Copyright (c) 2017 MediaTek Inc.
   3  * Author: Ming Huang <ming.huang@mediatek.com>
   4  *         Sean Wang <sean.wang@mediatek.com>
   5  *
   6  * SPDX-License-Identifier: (GPL-2.0 OR MIT)
   7  */
   8
   9 /dts-v1/;
  10 #include <dt-bindings/input/input.h>
  11 #include <dt-bindings/gpio/gpio.h>
  12
  13 #include "mt7622.dtsi"
  14 #include "mt6380.dtsi"
  15
  16 / {
  17         model = "MediaTek MT7622 RFB1 board";
  18         compatible = "mediatek,mt7622-rfb1", "mediatek,mt7622";
  19
  20         aliases {
  21                 serial0 = &uart0;
  22         };
  23
  24         chosen {
  25                 stdout-path = "serial0:115200n8";
  26                 bootargs = "earlycon=uart8250,mmio32,0x11002000 swiotlb=512";
  27         };
  28
  29         cpus {
  30                 cpu@0 {
  31                         proc-supply = <&mt6380_vcpu_reg>;
  32                         sram-supply = <&mt6380_vm_reg>;
  33                 };
  34
  35                 cpu@1 {
  36                         proc-supply = <&mt6380_vcpu_reg>;
  37                         sram-supply = <&mt6380_vm_reg>;
  38                 };
  39         };
  40
  41         gpio-keys {
  42                 compatible = "gpio-keys";
  43                 poll-interval = <100>;
  44
  45                 factory {
  46                         label = "factory";
  47                         linux,code = <BTN_0>;
  48                         gpios = <&pio 0 0>;
  49                 };
  50
  51                 wps {
  52                         label = "wps";
  53                         linux,code = <KEY_WPS_BUTTON>;
  54                         gpios = <&pio 102 0>;
  55                 };
  56         };
  57
  58         memory {
  59                 reg = <0 0x40000000 0 0x20000000>;
  60         };
  61
  62         reg_1p8v: regulator-1p8v {
  63                 compatible = "regulator-fixed";
  64                 regulator-name = "fixed-1.8V";
  65                 regulator-min-microvolt = <1800000>;
  66                 regulator-max-microvolt = <1800000>;
  67                 regulator-always-on;
  68         };
  69
  70         reg_3p3v: regulator-3p3v {
  71                 compatible = "regulator-fixed";
  72                 regulator-name = "fixed-3.3V";
  73                 regulator-min-microvolt = <3300000>;
  74                 regulator-max-microvolt = <3300000>;
  75                 regulator-boot-on;
  76                 regulator-always-on;
  77         };
  78
  79         reg_5v: regulator-5v {
  80                 compatible = "regulator-fixed";
  81                 regulator-name = "fixed-5V";
  82                 regulator-min-microvolt = <5000000>;
  83                 regulator-max-microvolt = <5000000>;
  84                 regulator-boot-on;
  85                 regulator-always-on;
  86         };
  87 };
  88
  89 &bch {
  90         status = "disabled";
  91 };
  92
  93 &btif {
  94         status = "okay";
  95 };
  96
  97 &cir {
  98         pinctrl-names = "default";
  99         pinctrl-0 = <&irrx_pins>;
 100         status = "okay";
 101 };
 102
 103 &eth {
 104         pinctrl-names = "default";
 105         pinctrl-0 = <&eth_pins>;
 106         status = "okay";
 107
 108         gmac0: mac@0 {
 109                 compatible = "mediatek,eth-mac";
 110                 reg = <0>;
 111                 phy-mode = "2500base-x";
 112
 113                 fixed-link {
 114                         speed = <2500>;
 115                         full-duplex;
 116                         pause;
 117                 };
 118         };
 119
 120         mdio-bus {
 121                 #address-cells = <1>;
 122                 #size-cells = <0>;
 123
 124                 switch@0 {
 125                         compatible = "mediatek,mt7531";
 126                         reg = <0>;
 127                         reset-gpios = <&pio 54 0>;
 128
 129                         ports {
 130                                 #address-cells = <1>;
 131                                 #size-cells = <0>;
 132
 133                                 port@0 {
 134                                         reg = <0>;
 135                                         label = "lan0";
 136                                 };
 137
 138                                 port@1 {
 139                                         reg = <1>;
 140                                         label = "lan1";
 141                                 };
 142
 143                                 port@2 {
 144                                         reg = <2>;
 145                                         label = "lan2";
 146                                 };
 147
 148                                 port@3 {
 149                                         reg = <3>;
 150                                         label = "lan3";
 151                                 };
 152
 153                                 port@4 {
 154                                         reg = <4>;
 155                                         label = "wan";
 156                                 };
 157
 158                                 port@6 {
 159                                         reg = <6>;
 160                                         label = "cpu";
 161                                         ethernet = <&gmac0>;
 162                                         phy-mode = "2500base-x";
 163
 164                                         fixed-link {
 165                                                 speed = <2500>;
 166                                                 full-duplex;
 167                                                 pause;
 168                                         };
 169                                 };
 170                         };
 171                 };
 172
 173         };
 174 };
 175
 176 &i2c1 {
 177         pinctrl-names = "default";
 178         pinctrl-0 = <&i2c1_pins>;
 179         status = "okay";
 180 };
 181
 182 &i2c2 {
 183         pinctrl-names = "default";
 184         pinctrl-0 = <&i2c2_pins>;
 185         status = "okay";
 186 };
 187
 188 &mmc0 {
 189         pinctrl-names = "default", "state_uhs";
 190         pinctrl-0 = <&emmc_pins_default>;
 191         pinctrl-1 = <&emmc_pins_uhs>;
 192         status = "okay";
 193         bus-width = <8>;
 194         max-frequency = <50000000>;
 195         cap-mmc-highspeed;
 196         mmc-hs200-1_8v;
 197         vmmc-supply = <&reg_3p3v>;
 198         vqmmc-supply = <&reg_1p8v>;
 199         assigned-clocks = <&topckgen CLK_TOP_MSDC30_0_SEL>;
 200         assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
 201         non-removable;
 202 };
 203
 204 &mmc1 {
 205         pinctrl-names = "default", "state_uhs";
 206         pinctrl-0 = <&sd0_pins_default>;
 207         pinctrl-1 = <&sd0_pins_uhs>;
 208         status = "okay";
 209         bus-width = <4>;
 210         max-frequency = <50000000>;
 211         cap-sd-highspeed;
 212         r_smpl = <1>;
 213         cd-gpios = <&pio 81 GPIO_ACTIVE_LOW>;
 214         vmmc-supply = <&reg_3p3v>;
 215         vqmmc-supply = <&reg_3p3v>;
 216         assigned-clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>;
 217         assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
 218 };
 219
 220 &nandc {
 221         pinctrl-names = "default";
 222         pinctrl-0 = <&parallel_nand_pins>;
 223         status = "disabled";
 224 };
 225
 226 &nor_flash {
 227         pinctrl-names = "default";
 228         pinctrl-0 = <&spi_nor_pins>;
 229         status = "disabled";
 230
 231         flash@0 {
 232                 compatible = "jedec,spi-nor";
 233                 reg = <0>;
 234         };
 235 };
 236
 237 &pcie {
 238         pinctrl-names = "default";
 239         pinctrl-0 = <&pcie0_pins>;
 240         status = "okay";
 241
 242         pcie@0,0 {
 243                 status = "okay";
 244         };
 245 };
 246
 247 &pio {
 248         /* eMMC is shared pin with parallel NAND */
 249         emmc_pins_default: emmc-pins-default {
 250                 mux {
 251                         function = "emmc", "emmc_rst";
 252                         groups = "emmc";
 253                 };
 254
 255                 /* "NDL0","NDL1","NDL2","NDL3","NDL4","NDL5","NDL6","NDL7",
 256                  * "NRB","NCLE" pins are used as DAT0,DAT1,DAT2,DAT3,DAT4,
 257                  * DAT5,DAT6,DAT7,CMD,CLK for eMMC respectively
 258                  */
 259                 conf-cmd-dat {
 260                         pins = "NDL0", "NDL1", "NDL2",
 261                                "NDL3", "NDL4", "NDL5",
 262                                "NDL6", "NDL7", "NRB";
 263                         input-enable;
 264                         bias-pull-up;
 265                 };
 266
 267                 conf-clk {
 268                         pins = "NCLE";
 269                         bias-pull-down;
 270                 };
 271         };
 272
 273         emmc_pins_uhs: emmc-pins-uhs {
 274                 mux {
 275                         function = "emmc";
 276                         groups = "emmc";
 277                 };
 278
 279                 conf-cmd-dat {
 280                         pins = "NDL0", "NDL1", "NDL2",
 281                                "NDL3", "NDL4", "NDL5",
 282                                "NDL6", "NDL7", "NRB";
 283                         input-enable;
 284                         drive-strength = <4>;
 285                         bias-pull-up;
 286                 };
 287
 288                 conf-clk {
 289                         pins = "NCLE";
 290                         drive-strength = <4>;
 291                         bias-pull-down;
 292                 };
 293         };
 294
 295         eth_pins: eth-pins {
 296                 mux {
 297                         function = "eth";
 298                         groups = "mdc_mdio", "rgmii_via_gmac2";
 299                 };
 300         };
 301
 302         i2c1_pins: i2c1-pins {
 303                 mux {
 304                         function = "i2c";
 305                         groups =  "i2c1_0";
 306                 };
 307         };
 308
 309         i2c2_pins: i2c2-pins {
 310                 mux {
 311                         function = "i2c";
 312                         groups =  "i2c2_0";
 313                 };
 314         };
 315
 316         i2s1_pins: i2s1-pins {
 317                 mux {
 318                         function = "i2s";
 319                         groups =  "i2s_out_mclk_bclk_ws",
 320                                   "i2s1_in_data",
 321                                   "i2s1_out_data";
 322                 };
 323
 324                 conf {
 325                         pins = "I2S1_IN", "I2S1_OUT", "I2S_BCLK",
 326                                "I2S_WS", "I2S_MCLK";
 327                         drive-strength = <12>;
 328                         bias-pull-down;
 329                 };
 330         };
 331
 332         irrx_pins: irrx-pins {
 333                 mux {
 334                         function = "ir";
 335                         groups =  "ir_1_rx";
 336                 };
 337         };
 338
 339         irtx_pins: irtx-pins {
 340                 mux {
 341                         function = "ir";
 342                         groups =  "ir_1_tx";
 343                 };
 344         };
 345
 346         /* Parallel nand is shared pin with eMMC */
 347         parallel_nand_pins: parallel-nand-pins {
 348                 mux {
 349                         function = "flash";
 350                         groups = "par_nand";
 351                 };
 352         };
 353
 354         pcie0_pins: pcie0-pins {
 355                 mux {
 356                         function = "pcie";
 357                         groups = "pcie0_pad_perst",
 358                                  "pcie0_1_waken",
 359                                  "pcie0_1_clkreq";
 360                 };
 361         };
 362
 363         pcie1_pins: pcie1-pins {
 364                 mux {
 365                         function = "pcie";
 366                         groups = "pcie1_pad_perst",
 367                                  "pcie1_0_waken",
 368                                  "pcie1_0_clkreq";
 369                 };
 370         };
 371
 372         pmic_bus_pins: pmic-bus-pins {
 373                 mux {
 374                         function = "pmic";
 375                         groups = "pmic_bus";
 376                 };
 377         };
 378
 379         pwm7_pins: pwm1-2-pins {
 380                 mux {
 381                         function = "pwm";
 382                         groups = "pwm_ch7_2";
 383                 };
 384         };
 385
 386         wled_pins: wled-pins {
 387                 mux {
 388                         function = "led";
 389                         groups = "wled";
 390                 };
 391         };
 392
 393         sd0_pins_default: sd0-pins-default {
 394                 mux {
 395                         function = "sd";
 396                         groups = "sd_0";
 397                 };
 398
 399                 /* "I2S2_OUT, "I2S4_IN"", "I2S3_IN", "I2S2_IN",
 400                  *  "I2S4_OUT", "I2S3_OUT" are used as DAT0, DAT1,
 401                  *  DAT2, DAT3, CMD, CLK for SD respectively.
 402                  */
 403                 conf-cmd-data {
 404                         pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN",
 405                                "I2S2_IN","I2S4_OUT";
 406                         input-enable;
 407                         drive-strength = <8>;
 408                         bias-pull-up;
 409                 };
 410                 conf-clk {
 411                         pins = "I2S3_OUT";
 412                         drive-strength = <12>;
 413                         bias-pull-down;
 414                 };
 415                 conf-cd {
 416                         pins = "TXD3";
 417                         bias-pull-up;
 418                 };
 419         };
 420
 421         sd0_pins_uhs: sd0-pins-uhs {
 422                 mux {
 423                         function = "sd";
 424                         groups = "sd_0";
 425                 };
 426
 427                 conf-cmd-data {
 428                         pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN",
 429                                "I2S2_IN","I2S4_OUT";
 430                         input-enable;
 431                         bias-pull-up;
 432                 };
 433
 434                 conf-clk {
 435                         pins = "I2S3_OUT";
 436                         bias-pull-down;
 437                 };
 438         };
 439
 440         /* Serial NAND is shared pin with SPI-NOR */
 441         serial_nand_pins: serial-nand-pins {
 442                 mux {
 443                         function = "flash";
 444                         groups = "snfi";
 445                 };
 446         };
 447
 448         spic0_pins: spic0-pins {
 449                 mux {
 450                         function = "spi";
 451                         groups = "spic0_0";
 452                 };
 453         };
 454
 455         spic1_pins: spic1-pins {
 456                 mux {
 457                         function = "spi";
 458                         groups = "spic1_0";
 459                 };
 460         };
 461
 462         /* SPI-NOR is shared pin with serial NAND */
 463         spi_nor_pins: spi-nor-pins {
 464                 mux {
 465                         function = "flash";
 466                         groups = "spi_nor";
 467                 };
 468         };
 469
 470         /* serial NAND is shared pin with SPI-NOR */
 471         serial_nand_pins: serial-nand-pins {
 472                 mux {
 473                         function = "flash";
 474                         groups = "snfi";
 475                 };
 476         };
 477
 478         uart0_pins: uart0-pins {
 479                 mux {
 480                         function = "uart";
 481                         groups = "uart0_0_tx_rx" ;
 482                 };
 483         };
 484
 485         uart2_pins: uart2-pins {
 486                 mux {
 487                         function = "uart";
 488                         groups = "uart2_1_tx_rx" ;
 489                 };
 490         };
 491
 492         watchdog_pins: watchdog-pins {
 493                 mux {
 494                         function = "watchdog";
 495                         groups = "watchdog";
 496                 };
 497         };
 498
 499         wmac_pins: wmac-pins {
 500                 mux {
 501                         function = "antsel";
 502                         groups = "antsel0", "antsel1", "antsel2", "antsel3",
 503                                  "antsel4", "antsel5", "antsel6", "antsel7",
 504                                  "antsel8", "antsel9", "antsel12", "antsel13",
 505                                  "antsel14", "antsel15", "antsel16", "antsel17";
 506                 };
 507         };
 508 };
 509
 510 &pwm {
 511         pinctrl-names = "default";
 512         pinctrl-0 = <&pwm7_pins>;
 513         status = "okay";
 514 };
 515
 516 &pwrap {
 517         pinctrl-names = "default";
 518         pinctrl-0 = <&pmic_bus_pins>;
 519
 520         status = "okay";
 521 };
 522
 523 &sata {
 524         status = "okay";
 525 };
 526
 527 &sata_phy {
 528         status = "okay";
 529 };
 530
 531 &spi0 {
 532         pinctrl-names = "default";
 533         pinctrl-0 = <&spic0_pins>;
 534         status = "okay";
 535 };
 536
 537 &spi1 {
 538         pinctrl-names = "default";
 539         pinctrl-0 = <&spic1_pins>;
 540         status = "okay";
 541 };
 542
 543 &ssusb {
 544         vusb33-supply = <&reg_3p3v>;
 545         vbus-supply = <&reg_5v>;
 546         status = "okay";
 547 };
 548
 549 &u3phy {
 550         status = "okay";
 551 };
 552
 553 &uart0 {
 554         pinctrl-names = "default";
 555         pinctrl-0 = <&uart0_pins>;
 556         status = "okay";
 557 };
 558
 559 &uart2 {
 560         pinctrl-names = "default";
 561         pinctrl-0 = <&uart2_pins>;
 562         status = "okay";
 563 };
 564
 565 &watchdog {
 566         pinctrl-names = "default";
 567         pinctrl-0 = <&watchdog_pins>;
 568         status = "okay";
 569 };
 570
 571 &wmac {
 572         pinctrl-names = "default";
 573         pinctrl-0 = <&wmac_pins>;
 574         status = "okay";
 575 };