arch/arm64/boot/dts/marvell/cn9132-db.dts

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Copyright (C) 2019 Marvell International Ltd.
   4  *
   5  * Device tree for the CN9132-DB board.
   6  */
   7
   8 #include "cn9131-db.dts"
   9
  10 / {
  11         model = "Marvell Armada CN9132-DB";
  12         compatible = "marvell,cn9132", "marvell,cn9131", "marvell,cn9130",
  13                      "marvell,armada-ap807-quad", "marvell,armada-ap807";
  14
  15         aliases {
  16                 gpio5 = &cp2_gpio1;
  17                 gpio6 = &cp2_gpio2;
  18                 ethernet5 = &cp2_eth0;
  19         };
  20
  21         cp2_reg_usb3_vbus0: cp2_usb3_vbus@0 {
  22                 compatible = "regulator-fixed";
  23                 regulator-name = "cp2-xhci0-vbus";
  24                 regulator-min-microvolt = <5000000>;
  25                 regulator-max-microvolt = <5000000>;
  26                 enable-active-high;
  27                 gpio = <&cp2_gpio1 2 GPIO_ACTIVE_HIGH>;
  28         };
  29
  30         cp2_usb3_0_phy0: cp2_usb3_phy0 {
  31                 compatible = "usb-nop-xceiv";
  32                 vcc-supply = <&cp2_reg_usb3_vbus0>;
  33         };
  34
  35         cp2_reg_usb3_vbus1: cp2_usb3_vbus@1 {
  36                 compatible = "regulator-fixed";
  37                 regulator-name = "cp2-xhci1-vbus";
  38                 regulator-min-microvolt = <5000000>;
  39                 regulator-max-microvolt = <5000000>;
  40                 enable-active-high;
  41                 gpio = <&cp2_gpio1 3 GPIO_ACTIVE_HIGH>;
  42         };
  43
  44         cp2_usb3_0_phy1: cp2_usb3_phy1 {
  45                 compatible = "usb-nop-xceiv";
  46                 vcc-supply = <&cp2_reg_usb3_vbus1>;
  47         };
  48
  49         cp2_reg_sd_vccq: cp2_sd_vccq@0 {
  50                 compatible = "regulator-gpio";
  51                 regulator-name = "cp2_sd_vcc";
  52                 regulator-min-microvolt = <1800000>;
  53                 regulator-max-microvolt = <3300000>;
  54                 gpios = <&cp2_gpio2 17 GPIO_ACTIVE_HIGH>;
  55                 states = <1800000 0x1 3300000 0x0>;
  56         };
  57
  58         cp2_sfp_eth0: sfp-eth0 {
  59                 compatible = "sff,sfp";
  60                 i2c-bus = <&cp2_sfpp0_i2c>;
  61                 los-gpio = <&cp2_module_expander1 11 GPIO_ACTIVE_HIGH>;
  62                 mod-def0-gpio = <&cp2_module_expander1 10 GPIO_ACTIVE_LOW>;
  63                 tx-disable-gpio = <&cp2_module_expander1 9 GPIO_ACTIVE_HIGH>;
  64                 tx-fault-gpio = <&cp2_module_expander1 8 GPIO_ACTIVE_HIGH>;
  65                 /*
  66                  * SFP cages are unconnected on early PCBs because of an the I2C
  67                  * lanes not being connected. Prevent the port for being
  68                  * unusable by disabling the SFP node.
  69                  */
  70                 status = "disabled";
  71         };
  72 };
  73
  74 /*
  75  * Instantiate the second slave CP115
  76  */
  77
  78 #define CP11X_NAME              cp2
  79 #define CP11X_BASE              f6000000
  80 #define CP11X_PCIEx_MEM_BASE(iface) (0xe5000000 + (iface * 0x1000000))
  81 #define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000
  82 #define CP11X_PCIE0_BASE        f6600000
  83 #define CP11X_PCIE1_BASE        f6620000
  84 #define CP11X_PCIE2_BASE        f6640000
  85
  86 #include "armada-cp115.dtsi"
  87
  88 #undef CP11X_NAME
  89 #undef CP11X_BASE
  90 #undef CP11X_PCIEx_MEM_BASE
  91 #undef CP11X_PCIEx_MEM_SIZE
  92 #undef CP11X_PCIE0_BASE
  93 #undef CP11X_PCIE1_BASE
  94 #undef CP11X_PCIE2_BASE
  95
  96 &cp2_crypto {
  97         status = "disabled";
  98 };
  99
 100 &cp2_ethernet {
 101         status = "okay";
 102 };
 103
 104 /* SLM-1521-V2, CON9 */
 105 &cp2_eth0 {
 106         status = "disabled";
 107         phy-mode = "10gbase-kr";
 108         /* Generic PHY, providing serdes lanes */
 109         phys = <&cp2_comphy4 0>;
 110         managed = "in-band-status";
 111         sfp = <&cp2_sfp_eth0>;
 112 };
 113
 114 &cp2_gpio1 {
 115         status = "okay";
 116 };
 117
 118 &cp2_gpio2 {
 119         status = "okay";
 120 };
 121
 122 &cp2_i2c0 {
 123         clock-frequency = <100000>;
 124
 125         /* SLM-1521-V2 - U3 */
 126         i2c-mux@72 {
 127                 compatible = "nxp,pca9544";
 128                 #address-cells = <1>;
 129                 #size-cells = <0>;
 130                 reg = <0x72>;
 131                 cp2_sfpp0_i2c: i2c@0 {
 132                         #address-cells = <1>;
 133                         #size-cells = <0>;
 134                         reg = <0>;
 135                 };
 136
 137                 i2c@1 {
 138                         #address-cells = <1>;
 139                         #size-cells = <0>;
 140                         reg = <1>;
 141                         /* U12 */
 142                         cp2_module_expander1: pca9555@21 {
 143                                 compatible = "nxp,pca9555";
 144                                 pinctrl-names = "default";
 145                                 gpio-controller;
 146                                 #gpio-cells = <2>;
 147                                 reg = <0x21>;
 148                         };
 149                 };
 150         };
 151 };
 152
 153 /* SLM-1521-V2, CON6 */
 154 &cp2_pcie0 {
 155         status = "okay";
 156         num-lanes = <2>;
 157         num-viewport = <8>;
 158         /* Generic PHY, providing serdes lanes */
 159         phys = <&cp2_comphy0 0
 160                 &cp2_comphy1 0>;
 161 };
 162
 163 /* SLM-1521-V2, CON8 */
 164 &cp2_pcie2 {
 165         status = "okay";
 166         num-lanes = <1>;
 167         num-viewport = <8>;
 168         /* Generic PHY, providing serdes lanes */
 169         phys = <&cp2_comphy5 2>;
 170 };
 171
 172 &cp2_sata0 {
 173         status = "okay";
 174
 175         /* SLM-1521-V2, CON4 */
 176         sata-port@0 {
 177                 /* Generic PHY, providing serdes lanes */
 178                 phys = <&cp2_comphy2 0>;
 179         };
 180 };
 181
 182 /* CON 2 on SLM-1683 - microSD */
 183 &cp2_sdhci0 {
 184         status = "okay";
 185         pinctrl-names = "default";
 186         pinctrl-0 = <&cp2_sdhci_pins>;
 187         bus-width = <4>;
 188         cd-gpios = <&cp2_gpio2 23 GPIO_ACTIVE_LOW>;
 189         vqmmc-supply = <&cp2_reg_sd_vccq>;
 190 };
 191
 192 &cp2_syscon0 {
 193         cp2_pinctrl: pinctrl {
 194                 compatible = "marvell,cp115-standalone-pinctrl";
 195
 196                 cp2_i2c0_pins: cp2-i2c-pins-0 {
 197                         marvell,pins = "mpp37", "mpp38";
 198                         marvell,function = "i2c0";
 199                 };
 200                 cp2_sdhci_pins: cp2-sdhi-pins-0 {
 201                         marvell,pins = "mpp56", "mpp57", "mpp58",
 202                                        "mpp59", "mpp60", "mpp61";
 203                         marvell,function = "sdio";
 204                 };
 205         };
 206 };
 207
 208 &cp2_utmi {
 209         status = "okay";
 210 };
 211
 212 &cp2_usb3_0 {
 213         status = "okay";
 214         usb-phy = <&cp2_usb3_0_phy0>;
 215         phys = <&cp2_utmi0>;
 216         phy-names = "usb";
 217         dr_mode = "host";
 218 };
 219
 220 /* SLM-1521-V2, CON11 */
 221 &cp2_usb3_1 {
 222         status = "okay";
 223         usb-phy = <&cp2_usb3_0_phy1>;
 224         /* Generic PHY, providing serdes lanes */
 225         phys = <&cp2_comphy3 1>, <&cp2_utmi1>;
 226         phy-names = "usb", "utmi";
 227         dr_mode = "host";
 228 };