arch/arm64/boot/dts/marvell/cn9130-crb.dtsi

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2020 Marvell International Ltd.
   4  */
   5
   6 #include "cn9130.dtsi" /* include SoC device tree */
   7
   8 #include <dt-bindings/gpio/gpio.h>
   9
  10 / {
  11         chosen {
  12                 stdout-path = "serial0:115200n8";
  13         };
  14
  15         aliases {
  16                 i2c0 = &cp0_i2c0;
  17                 ethernet0 = &cp0_eth0;
  18                 ethernet1 = &cp0_eth1;
  19                 ethernet2 = &cp0_eth2;
  20                 gpio1 = &cp0_gpio1;
  21                 gpio2 = &cp0_gpio2;
  22         };
  23
  24         memory@0 {
  25                 device_type = "memory";
  26                 reg = <0x0 0x0 0x0 0x80000000>;
  27         };
  28
  29         ap0_reg_mmc_vccq: ap0_mmc_vccq@0 {
  30                 compatible = "regulator-gpio";
  31                 regulator-name = "ap0_mmc_vccq";
  32                 regulator-min-microvolt = <1800000>;
  33                 regulator-max-microvolt = <3300000>;
  34                 gpios = <&expander0 5 GPIO_ACTIVE_HIGH>;
  35                 states = <1800000 0x1
  36                           3300000 0x0>;
  37         };
  38
  39         cp0_reg_usb3_vbus1: cp0_usb3_vbus@1 {
  40                 compatible = "regulator-fixed";
  41                 regulator-name = "cp0-xhci1-vbus";
  42                 regulator-min-microvolt = <5000000>;
  43                 regulator-max-microvolt = <5000000>;
  44                 enable-active-high;
  45                 gpio = <&expander0 8 GPIO_ACTIVE_HIGH>;
  46         };
  47
  48         cp0_usb3_0_phy0: cp0_usb3_phy0 {
  49                 compatible = "usb-nop-xceiv";
  50         };
  51
  52         cp0_usb3_0_phy1: cp0_usb3_phy1 {
  53                 compatible = "usb-nop-xceiv";
  54                 vcc-supply = <&cp0_reg_usb3_vbus1>;
  55         };
  56
  57         cp0_reg_sd_vccq: cp0_sd_vccq@0 {
  58                 compatible = "regulator-gpio";
  59                 regulator-name = "cp0_sd_vccq";
  60                 regulator-min-microvolt = <1800000>;
  61                 regulator-max-microvolt = <3300000>;
  62                 gpios = <&cp0_gpio2 18 GPIO_ACTIVE_HIGH>;
  63                 states = <1800000 0x1
  64                           3300000 0x0>;
  65         };
  66
  67         cp0_reg_sd_vcc: cp0_sd_vcc@0 {
  68                 compatible = "regulator-fixed";
  69                 regulator-name = "cp0_sd_vcc";
  70                 regulator-min-microvolt = <3300000>;
  71                 regulator-max-microvolt = <3300000>;
  72                 gpio = <&cp0_gpio2 19 GPIO_ACTIVE_HIGH>;
  73                 enable-active-high;
  74                 regulator-always-on;
  75         };
  76
  77         sfp: sfp {
  78                 compatible = "sff,sfp";
  79                 i2c-bus = <&cp0_i2c1>;
  80                 mod-def0-gpios = <&expander0 3 GPIO_ACTIVE_LOW>;
  81                 los-gpios = <&expander0 15 GPIO_ACTIVE_HIGH>;
  82                 tx-disable-gpios = <&expander0 2 GPIO_ACTIVE_HIGH>;
  83                 tx-fault-gpios = <&cp0_gpio1 24 GPIO_ACTIVE_HIGH>;
  84                 maximum-power-milliwatt = <3000>;
  85                 status = "okay";
  86         };
  87 };
  88
  89 &uart0 {
  90         status = "okay";
  91 };
  92
  93 /* on-board eMMC U6 */
  94 &ap_sdhci0 {
  95         pinctrl-names = "default";
  96         bus-width = <8>;
  97         status = "okay";
  98         mmc-ddr-1_8v;
  99         vqmmc-supply = <&ap0_reg_mmc_vccq>;
 100 };
 101
 102 &cp0_syscon0 {
 103         cp0_pinctrl: pinctrl {
 104                 compatible = "marvell,cp115-standalone-pinctrl";
 105
 106                 cp0_i2c0_pins: cp0-i2c-pins-0 {
 107                         marvell,pins = "mpp37", "mpp38";
 108                         marvell,function = "i2c0";
 109                 };
 110                 cp0_i2c1_pins: cp0-i2c-pins-1 {
 111                         marvell,pins = "mpp35", "mpp36";
 112                         marvell,function = "i2c1";
 113                 };
 114                 cp0_sdhci_cd_pins_crb: cp0-sdhci-cd-pins-crb {
 115                         marvell,pins = "mpp55";
 116                         marvell,function = "gpio";
 117                 };
 118                 cp0_sdhci_pins: cp0-sdhi-pins-0 {
 119                         marvell,pins = "mpp56", "mpp57", "mpp58",
 120                                        "mpp59", "mpp60", "mpp61";
 121                         marvell,function = "sdio";
 122                 };
 123                 cp0_spi1_pins: cp0-spi-pins-1 {
 124                         marvell,pins = "mpp13", "mpp14", "mpp15", "mpp16";
 125                         marvell,function = "spi1";
 126                 };
 127         };
 128 };
 129
 130 &cp0_gpio1 {
 131         status = "okay";
 132 };
 133
 134 &cp0_gpio2 {
 135         status = "okay";
 136 };
 137
 138 &cp0_i2c0 {
 139         pinctrl-names = "default";
 140         pinctrl-0 = <&cp0_i2c0_pins>;
 141         status = "okay";
 142         clock-frequency = <100000>;
 143         expander0: mcp23x17@20 {
 144                 compatible = "microchip,mcp23017";
 145                 gpio-controller;
 146                 #gpio-cells = <2>;
 147                 reg = <0x20>;
 148                 status = "okay";
 149         };
 150 };
 151
 152 &cp0_i2c1 {
 153         pinctrl-names = "default";
 154         pinctrl-0 = <&cp0_i2c1_pins>;
 155         clock-frequency = <100000>;
 156         status = "okay";
 157 };
 158
 159
 160 &cp0_sdhci0 {
 161         pinctrl-names = "default";
 162         pinctrl-0 = <&cp0_sdhci_pins
 163                      &cp0_sdhci_cd_pins_crb>;
 164         bus-width = <4>;
 165         cd-gpios = <&cp0_gpio2 23 GPIO_ACTIVE_HIGH>;
 166         vqmmc-supply = <&cp0_reg_sd_vccq>;
 167         vmmc-supply = <&cp0_reg_sd_vcc>;
 168         status = "okay";
 169 };
 170
 171 &cp0_spi1 {
 172         pinctrl-names = "default";
 173         pinctrl-0 = <&cp0_spi1_pins>;
 174         reg = <0x700680 0x50>,          /* control */
 175               <0x2000000 0x1000000>;    /* CS0 */
 176         status = "okay";
 177
 178         flash@0 {
 179                 #address-cells = <0x1>;
 180                 #size-cells = <0x1>;
 181                 compatible = "jedec,spi-nor";
 182                 reg = <0x0>;
 183                 /* On-board MUX does not allow higher frequencies */
 184                 spi-max-frequency = <40000000>;
 185
 186                 partitions {
 187                         compatible = "fixed-partitions";
 188                         #address-cells = <1>;
 189                         #size-cells = <1>;
 190
 191                         partition@0 {
 192                                 label = "U-Boot";
 193                                 reg = <0x0 0x200000>;
 194                         };
 195
 196                         partition@400000 {
 197                                 label = "Filesystem";
 198                                 reg = <0x200000 0xe00000>;
 199                         };
 200                 };
 201         };
 202 };
 203
 204 &cp0_mdio {
 205         status = "okay";
 206         phy0: ethernet-phy@0 {
 207                 reg = <0>;
 208         };
 209
 210         switch6: ethernet-switch@6 {
 211                 /* Actual device is MV88E6393X */
 212                 compatible = "marvell,mv88e6190";
 213                 reg = <6>;
 214                 interrupt-parent = <&cp0_gpio1>;
 215                 interrupts = <28 IRQ_TYPE_LEVEL_LOW>;
 216                 interrupt-controller;
 217                 #interrupt-cells = <2>;
 218
 219                 dsa,member = <0 0>;
 220
 221                 ethernet-ports {
 222                         #address-cells = <1>;
 223                         #size-cells = <0>;
 224
 225                         ethernet-port@1 {
 226                                 reg = <1>;
 227                                 label = "p1";
 228                                 phy-handle = <&switch0phy1>;
 229                         };
 230
 231                         ethernet-port@2 {
 232                                 reg = <2>;
 233                                 label = "p2";
 234                                 phy-handle = <&switch0phy2>;
 235                         };
 236
 237                         ethernet-port@3 {
 238                                 reg = <3>;
 239                                 label = "p3";
 240                                 phy-handle = <&switch0phy3>;
 241                         };
 242
 243                         ethernet-port@4 {
 244                                 reg = <4>;
 245                                 label = "p4";
 246                                 phy-handle = <&switch0phy4>;
 247                         };
 248
 249                         ethernet-port@5 {
 250                                 reg = <5>;
 251                                 label = "p5";
 252                                 phy-handle = <&switch0phy5>;
 253                         };
 254
 255                         ethernet-port@6 {
 256                                 reg = <6>;
 257                                 label = "p6";
 258                                 phy-handle = <&switch0phy6>;
 259                         };
 260
 261                         ethernet-port@7 {
 262                                 reg = <7>;
 263                                 label = "p7";
 264                                 phy-handle = <&switch0phy7>;
 265                         };
 266
 267                         ethernet-port@8 {
 268                                 reg = <8>;
 269                                 label = "p8";
 270                                 phy-handle = <&switch0phy8>;
 271                         };
 272
 273                         ethernet-port@9 {
 274                                 reg = <9>;
 275                                 label = "p9";
 276                                 phy-mode = "10gbase-r";
 277                                 sfp = <&sfp>;
 278                                 managed = "in-band-status";
 279                         };
 280
 281                         ethernet-port@a {
 282                                 reg = <10>;
 283                                 ethernet = <&cp0_eth0>;
 284                                 phy-mode = "10gbase-r";
 285                                 managed = "in-band-status";
 286                         };
 287
 288                 };
 289
 290                 mdio {
 291                         #address-cells = <1>;
 292                         #size-cells = <0>;
 293
 294                         switch0phy1: ethernet-phy@1 {
 295                                 reg = <0x1>;
 296                         };
 297
 298                         switch0phy2: ethernet-phy@2 {
 299                                 reg = <0x2>;
 300                         };
 301
 302                         switch0phy3: ethernet-phy@3 {
 303                                 reg = <0x3>;
 304                         };
 305
 306                         switch0phy4: ethernet-phy@4 {
 307                                 reg = <0x4>;
 308                         };
 309
 310                         switch0phy5: ethernet-phy@5 {
 311                                 reg = <0x5>;
 312                         };
 313
 314                         switch0phy6: ethernet-phy@6 {
 315                                 reg = <0x6>;
 316                         };
 317
 318                         switch0phy7: ethernet-phy@7 {
 319                                 reg = <0x7>;
 320                         };
 321
 322                         switch0phy8: ethernet-phy@8 {
 323                                 reg = <0x8>;
 324                         };
 325                 };
 326         };
 327 };
 328
 329 &cp0_xmdio {
 330         status = "okay";
 331         nbaset_phy0: ethernet-phy@0 {
 332                 compatible = "ethernet-phy-ieee802.3-c45";
 333                 reg = <0>;
 334         };
 335 };
 336
 337 &cp0_ethernet {
 338         status = "okay";
 339 };
 340
 341 &cp0_eth0 {
 342         /* This port is connected to 88E6393X switch */
 343         status = "okay";
 344         phy-mode = "10gbase-r";
 345         managed = "in-band-status";
 346         phys = <&cp0_comphy4 0>;
 347 };
 348
 349 &cp0_eth1 {
 350         status = "okay";
 351         phy = <&phy0>;
 352         phy-mode = "rgmii-id";
 353 };
 354
 355 &cp0_eth2 {
 356         /* This port uses "2500base-t" phy-mode */
 357         status = "disabled";
 358         phy = <&nbaset_phy0>;
 359         phys = <&cp0_comphy5 2>;
 360 };
 361