arch/arm64/boot/dts/hisilicon/hi3670.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * dts file for Hisilicon Hi3670 SoC
   4  *
   5  * Copyright (C) 2016, Hisilicon Ltd.
   6  * Copyright (C) 2018, Linaro Ltd.
   7  */
   8
   9 #include <dt-bindings/interrupt-controller/arm-gic.h>
  10 #include <dt-bindings/clock/hi3670-clock.h>
  11
  12 / {
  13         compatible = "hisilicon,hi3670";
  14         interrupt-parent = <&gic>;
  15         #address-cells = <2>;
  16         #size-cells = <2>;
  17
  18         psci {
  19                 compatible = "arm,psci-0.2";
  20                 method = "smc";
  21         };
  22
  23         cpus {
  24                 #address-cells = <2>;
  25                 #size-cells = <0>;
  26
  27                 cpu-map {
  28                         cluster0 {
  29                                 core0 {
  30                                         cpu = <&cpu0>;
  31                                 };
  32                                 core1 {
  33                                         cpu = <&cpu1>;
  34                                 };
  35                                 core2 {
  36                                         cpu = <&cpu2>;
  37                                 };
  38                                 core3 {
  39                                         cpu = <&cpu3>;
  40                                 };
  41                         };
  42                         cluster1 {
  43                                 core0 {
  44                                         cpu = <&cpu4>;
  45                                 };
  46                                 core1 {
  47                                         cpu = <&cpu5>;
  48                                 };
  49                                 core2 {
  50                                         cpu = <&cpu6>;
  51                                 };
  52                                 core3 {
  53                                         cpu = <&cpu7>;
  54                                 };
  55                         };
  56                 };
  57
  58                 cpu0: cpu@0 {
  59                         compatible = "arm,cortex-a53";
  60                         device_type = "cpu";
  61                         reg = <0x0 0x0>;
  62                         enable-method = "psci";
  63                 };
  64
  65                 cpu1: cpu@1 {
  66                         compatible = "arm,cortex-a53";
  67                         device_type = "cpu";
  68                         reg = <0x0 0x1>;
  69                         enable-method = "psci";
  70                 };
  71
  72                 cpu2: cpu@2 {
  73                         compatible = "arm,cortex-a53";
  74                         device_type = "cpu";
  75                         reg = <0x0 0x2>;
  76                         enable-method = "psci";
  77                 };
  78
  79                 cpu3: cpu@3 {
  80                         compatible = "arm,cortex-a53";
  81                         device_type = "cpu";
  82                         reg = <0x0 0x3>;
  83                         enable-method = "psci";
  84                 };
  85
  86                 cpu4: cpu@100 {
  87                         compatible = "arm,cortex-a73";
  88                         device_type = "cpu";
  89                         reg = <0x0 0x100>;
  90                         enable-method = "psci";
  91                 };
  92
  93                 cpu5: cpu@101 {
  94                         compatible = "arm,cortex-a73";
  95                         device_type = "cpu";
  96                         reg = <0x0 0x101>;
  97                         enable-method = "psci";
  98                 };
  99
 100                 cpu6: cpu@102 {
 101                         compatible = "arm,cortex-a73";
 102                         device_type = "cpu";
 103                         reg = <0x0 0x102>;
 104                         enable-method = "psci";
 105                 };
 106
 107                 cpu7: cpu@103 {
 108                         compatible = "arm,cortex-a73";
 109                         device_type = "cpu";
 110                         reg = <0x0 0x103>;
 111                         enable-method = "psci";
 112                 };
 113         };
 114
 115         gic: interrupt-controller@e82b0000 {
 116                 compatible = "arm,gic-400";
 117                 reg = <0x0 0xe82b1000 0 0x1000>, /* GICD */
 118                       <0x0 0xe82b2000 0 0x2000>, /* GICC */
 119                       <0x0 0xe82b4000 0 0x2000>, /* GICH */
 120                       <0x0 0xe82b6000 0 0x2000>; /* GICV */
 121                 #interrupt-cells = <3>;
 122                 #address-cells = <0>;
 123                 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) |
 124                                          IRQ_TYPE_LEVEL_HIGH)>;
 125                 interrupt-controller;
 126         };
 127
 128         timer {
 129                 compatible = "arm,armv8-timer";
 130                 interrupt-parent = <&gic>;
 131                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) |
 132                                           IRQ_TYPE_LEVEL_LOW)>,
 133                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) |
 134                                           IRQ_TYPE_LEVEL_LOW)>,
 135                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) |
 136                                           IRQ_TYPE_LEVEL_LOW)>,
 137                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) |
 138                                           IRQ_TYPE_LEVEL_LOW)>;
 139                 clock-frequency = <1920000>;
 140         };
 141
 142         soc {
 143                 compatible = "simple-bus";
 144                 #address-cells = <2>;
 145                 #size-cells = <2>;
 146                 ranges;
 147
 148                 crg_ctrl: crg_ctrl@fff35000 {
 149                         compatible = "hisilicon,hi3670-crgctrl", "syscon";
 150                         reg = <0x0 0xfff35000 0x0 0x1000>;
 151                         #clock-cells = <1>;
 152                 };
 153
 154                 crg_rst: crg_rst_controller {
 155                         compatible = "hisilicon,hi3670-reset",
 156                                      "hisilicon,hi3660-reset";
 157                         #reset-cells = <2>;
 158                         hisi,rst-syscon = <&crg_ctrl>;
 159                 };
 160
 161                 pctrl: pctrl@e8a09000 {
 162                         compatible = "hisilicon,hi3670-pctrl", "syscon";
 163                         reg = <0x0 0xe8a09000 0x0 0x1000>;
 164                         #clock-cells = <1>;
 165                 };
 166
 167                 pmuctrl: crg_ctrl@fff34000 {
 168                         compatible = "hisilicon,hi3670-pmuctrl", "syscon";
 169                         reg = <0x0 0xfff34000 0x0 0x1000>;
 170                         #clock-cells = <1>;
 171                 };
 172
 173                 sctrl: sctrl@fff0a000 {
 174                         compatible = "hisilicon,hi3670-sctrl", "syscon";
 175                         reg = <0x0 0xfff0a000 0x0 0x1000>;
 176                         #clock-cells = <1>;
 177                 };
 178
 179                 iomcu: iomcu@ffd7e000 {
 180                         compatible = "hisilicon,hi3670-iomcu", "syscon";
 181                         reg = <0x0 0xffd7e000 0x0 0x1000>;
 182                         #clock-cells = <1>;
 183                 };
 184
 185                 media1_crg: media1_crgctrl@e87ff000 {
 186                         compatible = "hisilicon,hi3670-media1-crg", "syscon";
 187                         reg = <0x0 0xe87ff000 0x0 0x1000>;
 188                         #clock-cells = <1>;
 189                 };
 190
 191                 media2_crg: media2_crgctrl@e8900000 {
 192                         compatible = "hisilicon,hi3670-media2-crg","syscon";
 193                         reg = <0x0 0xe8900000 0x0 0x1000>;
 194                         #clock-cells = <1>;
 195                 };
 196
 197                 uart0: serial@fdf02000 {
 198                         compatible = "arm,pl011", "arm,primecell";
 199                         reg = <0x0 0xfdf02000 0x0 0x1000>;
 200                         interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 201                         clocks = <&crg_ctrl HI3670_CLK_GATE_UART0>,
 202                                  <&crg_ctrl HI3670_PCLK>;
 203                         clock-names = "uartclk", "apb_pclk";
 204                         pinctrl-names = "default";
 205                         pinctrl-0 = <&uart0_pmx_func &uart0_cfg_func>;
 206                         status = "disabled";
 207                 };
 208
 209                 uart1: serial@fdf00000 {
 210                         compatible = "arm,pl011", "arm,primecell";
 211                         reg = <0x0 0xfdf00000 0x0 0x1000>;
 212                         interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 213                         clocks = <&crg_ctrl HI3670_CLK_GATE_UART1>,
 214                                  <&crg_ctrl HI3670_PCLK>;
 215                         clock-names = "uartclk", "apb_pclk";
 216                         status = "disabled";
 217                 };
 218
 219                 uart2: serial@fdf03000 {
 220                         compatible = "arm,pl011", "arm,primecell";
 221                         reg = <0x0 0xfdf03000 0x0 0x1000>;
 222                         interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
 223                         clocks = <&crg_ctrl HI3670_CLK_GATE_UART2>,
 224                                  <&crg_ctrl HI3670_PCLK>;
 225                         clock-names = "uartclk", "apb_pclk";
 226                         pinctrl-names = "default";
 227                         pinctrl-0 = <&uart2_pmx_func &uart2_cfg_func>;
 228                         status = "disabled";
 229                 };
 230
 231                 uart3: serial@ffd74000 {
 232                         compatible = "arm,pl011", "arm,primecell";
 233                         reg = <0x0 0xffd74000 0x0 0x1000>;
 234                         interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
 235                         clocks = <&crg_ctrl HI3670_CLK_GATE_UART3>,
 236                                  <&crg_ctrl HI3670_PCLK>;
 237                         clock-names = "uartclk", "apb_pclk";
 238                         pinctrl-names = "default";
 239                         pinctrl-0 = <&uart3_pmx_func &uart3_cfg_func>;
 240                         status = "disabled";
 241                 };
 242
 243                 uart4: serial@fdf01000 {
 244                         compatible = "arm,pl011", "arm,primecell";
 245                         reg = <0x0 0xfdf01000 0x0 0x1000>;
 246                         interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
 247                         clocks = <&crg_ctrl HI3670_CLK_GATE_UART4>,
 248                                  <&crg_ctrl HI3670_PCLK>;
 249                         clock-names = "uartclk", "apb_pclk";
 250                         pinctrl-names = "default";
 251                         pinctrl-0 = <&uart4_pmx_func &uart4_cfg_func>;
 252                         status = "disabled";
 253                 };
 254
 255                 uart5: serial@fdf05000 {
 256                         compatible = "arm,pl011", "arm,primecell";
 257                         reg = <0x0 0xfdf05000 0x0 0x1000>;
 258                         interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
 259                         clocks = <&crg_ctrl HI3670_CLK_GATE_UART5>,
 260                                  <&crg_ctrl HI3670_PCLK>;
 261                         clock-names = "uartclk", "apb_pclk";
 262                         status = "disabled";
 263                 };
 264
 265                 uart6: serial@fff32000 {
 266                         compatible = "arm,pl011", "arm,primecell";
 267                         reg = <0x0 0xfff32000 0x0 0x1000>;
 268                         interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 269                         clocks = <&crg_ctrl HI3670_CLK_UART6>,
 270                                  <&crg_ctrl HI3670_PCLK>;
 271                         clock-names = "uartclk", "apb_pclk";
 272                         pinctrl-names = "default";
 273                         pinctrl-0 = <&uart6_pmx_func &uart6_cfg_func>;
 274                         status = "disabled";
 275                 };
 276
 277                 gpio0: gpio@e8a0b000 {
 278                         compatible = "arm,pl061", "arm,primecell";
 279                         reg = <0x0 0xe8a0b000 0x0 0x1000>;
 280                         interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 281                         gpio-controller;
 282                         #gpio-cells = <2>;
 283                         gpio-ranges = <&pmx0 1 0 1 &pmx0 3 1 5>;
 284                         interrupt-controller;
 285                         #interrupt-cells = <2>;
 286                         clocks = <&crg_ctrl HI3670_PCLK_GPIO0>;
 287                         clock-names = "apb_pclk";
 288                 };
 289
 290                 gpio1: gpio@e8a0c000 {
 291                         compatible = "arm,pl061", "arm,primecell";
 292                         reg = <0x0 0xe8a0c000 0x0 0x1000>;
 293                         interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 294                         gpio-controller;
 295                         #gpio-cells = <2>;
 296                         interrupt-controller;
 297                         #interrupt-cells = <2>;
 298                         clocks = <&crg_ctrl HI3670_PCLK_GPIO1>;
 299                         clock-names = "apb_pclk";
 300                 };
 301
 302                 gpio2: gpio@e8a0d000 {
 303                         compatible = "arm,pl061", "arm,primecell";
 304                         reg = <0x0 0xe8a0d000 0x0 0x1000>;
 305                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 306                         gpio-controller;
 307                         #gpio-cells = <2>;
 308                         gpio-ranges = <&pmx0 1 6 7>;
 309                         interrupt-controller;
 310                         #interrupt-cells = <2>;
 311                         clocks = <&crg_ctrl HI3670_PCLK_GPIO2>;
 312                         clock-names = "apb_pclk";
 313                 };
 314
 315                 gpio3: gpio@e8a0e000 {
 316                         compatible = "arm,pl061", "arm,primecell";
 317                         reg = <0x0 0xe8a0e000 0x0 0x1000>;
 318                         interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
 319                         gpio-controller;
 320                         #gpio-cells = <2>;
 321                         gpio-ranges =  <&pmx0 0 13 4 &pmx0 7 17 1>;
 322                         interrupt-controller;
 323                         #interrupt-cells = <2>;
 324                         clocks = <&crg_ctrl HI3670_PCLK_GPIO3>;
 325                         clock-names = "apb_pclk";
 326                 };
 327
 328                 gpio4: gpio@e8a0f000 {
 329                         compatible = "arm,pl061", "arm,primecell";
 330                         reg = <0x0 0xe8a0f000 0x0 0x1000>;
 331                         interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
 332                         gpio-controller;
 333                         #gpio-cells = <2>;
 334                         gpio-ranges = <&pmx0 0 18 8>;
 335                         interrupt-controller;
 336                         #interrupt-cells = <2>;
 337                         clocks = <&crg_ctrl HI3670_PCLK_GPIO4>;
 338                         clock-names = "apb_pclk";
 339                 };
 340
 341                 gpio5: gpio@e8a10000 {
 342                         compatible = "arm,pl061", "arm,primecell";
 343                         reg = <0x0 0xe8a10000 0x0 0x1000>;
 344                         interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
 345                         gpio-controller;
 346                         #gpio-cells = <2>;
 347                         gpio-ranges = <&pmx0 0 26 8>;
 348                         interrupt-controller;
 349                         #interrupt-cells = <2>;
 350                         clocks = <&crg_ctrl HI3670_PCLK_GPIO5>;
 351                         clock-names = "apb_pclk";
 352                 };
 353
 354                 gpio6: gpio@e8a11000 {
 355                         compatible = "arm,pl061", "arm,primecell";
 356                         reg = <0x0 0xe8a11000 0x0 0x1000>;
 357                         interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
 358                         gpio-controller;
 359                         #gpio-cells = <2>;
 360                         gpio-ranges = <&pmx0 1 34 7>;
 361                         interrupt-controller;
 362                         #interrupt-cells = <2>;
 363                         clocks = <&crg_ctrl HI3670_PCLK_GPIO6>;
 364                         clock-names = "apb_pclk";
 365                 };
 366
 367                 gpio7: gpio@e8a12000 {
 368                         compatible = "arm,pl061", "arm,primecell";
 369                         reg = <0x0 0xe8a12000 0x0 0x1000>;
 370                         interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
 371                         gpio-controller;
 372                         #gpio-cells = <2>;
 373                         gpio-ranges = <&pmx0 0 41 8>;
 374                         interrupt-controller;
 375                         #interrupt-cells = <2>;
 376                         clocks = <&crg_ctrl HI3670_PCLK_GPIO7>;
 377                         clock-names = "apb_pclk";
 378                 };
 379
 380                 gpio8: gpio@e8a13000 {
 381                         compatible = "arm,pl061", "arm,primecell";
 382                         reg = <0x0 0xe8a13000 0x0 0x1000>;
 383                         interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
 384                         gpio-controller;
 385                         #gpio-cells = <2>;
 386                         gpio-ranges = <&pmx0 0 49 8>;
 387                         interrupt-controller;
 388                         #interrupt-cells = <2>;
 389                         clocks = <&crg_ctrl HI3670_PCLK_GPIO8>;
 390                         clock-names = "apb_pclk";
 391                 };
 392
 393                 gpio9: gpio@e8a14000 {
 394                         compatible = "arm,pl061", "arm,primecell";
 395                         reg = <0x0 0xe8a14000 0x0 0x1000>;
 396                         interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
 397                         gpio-controller;
 398                         #gpio-cells = <2>;
 399                         gpio-ranges = <&pmx0 0 57 8>;
 400                         interrupt-controller;
 401                         #interrupt-cells = <2>;
 402                         clocks = <&crg_ctrl HI3670_PCLK_GPIO9>;
 403                         clock-names = "apb_pclk";
 404                 };
 405
 406                 gpio10: gpio@e8a15000 {
 407                         compatible = "arm,pl061", "arm,primecell";
 408                         reg = <0x0 0xe8a15000 0x0 0x1000>;
 409                         interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
 410                         gpio-controller;
 411                         #gpio-cells = <2>;
 412                         gpio-ranges = <&pmx0 0 65 8>;
 413                         interrupt-controller;
 414                         #interrupt-cells = <2>;
 415                         clocks = <&crg_ctrl HI3670_PCLK_GPIO10>;
 416                         clock-names = "apb_pclk";
 417                 };
 418
 419                 gpio11: gpio@e8a16000 {
 420                         compatible = "arm,pl061", "arm,primecell";
 421                         reg = <0x0 0xe8a16000 0x0 0x1000>;
 422                         interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
 423                         gpio-controller;
 424                         #gpio-cells = <2>;
 425                         gpio-ranges = <&pmx0 0 73 8>;
 426                         interrupt-controller;
 427                         #interrupt-cells = <2>;
 428                         clocks = <&crg_ctrl HI3670_PCLK_GPIO11>;
 429                         clock-names = "apb_pclk";
 430                 };
 431
 432                 gpio12: gpio@e8a17000 {
 433                         compatible = "arm,pl061", "arm,primecell";
 434                         reg = <0x0 0xe8a17000 0x0 0x1000>;
 435                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 436                         gpio-controller;
 437                         #gpio-cells = <2>;
 438                         gpio-ranges = <&pmx0 0 81 1>;
 439                         interrupt-controller;
 440                         #interrupt-cells = <2>;
 441                         clocks = <&crg_ctrl HI3670_PCLK_GPIO12>;
 442                         clock-names = "apb_pclk";
 443                 };
 444
 445                 gpio13: gpio@e8a18000 {
 446                         compatible = "arm,pl061", "arm,primecell";
 447                         reg = <0x0 0xe8a18000 0x0 0x1000>;
 448                         interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 449                         gpio-controller;
 450                         #gpio-cells = <2>;
 451                         interrupt-controller;
 452                         #interrupt-cells = <2>;
 453                         clocks = <&crg_ctrl HI3670_PCLK_GPIO13>;
 454                         clock-names = "apb_pclk";
 455                 };
 456
 457                 gpio14: gpio@e8a19000 {
 458                         compatible = "arm,pl061", "arm,primecell";
 459                         reg = <0x0 0xe8a19000 0x0 0x1000>;
 460                         interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
 461                         gpio-controller;
 462                         #gpio-cells = <2>;
 463                         interrupt-controller;
 464                         #interrupt-cells = <2>;
 465                         clocks = <&crg_ctrl HI3670_PCLK_GPIO14>;
 466                         clock-names = "apb_pclk";
 467                 };
 468
 469                 gpio15: gpio@e8a1a000 {
 470                         compatible = "arm,pl061", "arm,primecell";
 471                         reg = <0x0 0xe8a1a000 0x0 0x1000>;
 472                         interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
 473                         gpio-controller;
 474                         #gpio-cells = <2>;
 475                         interrupt-controller;
 476                         #interrupt-cells = <2>;
 477                         clocks = <&crg_ctrl HI3670_PCLK_GPIO15>;
 478                         clock-names = "apb_pclk";
 479                 };
 480
 481                 gpio16: gpio@e8a1b000 {
 482                         compatible = "arm,pl061", "arm,primecell";
 483                         reg = <0x0 0xe8a1b000 0x0 0x1000>;
 484                         interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
 485                         gpio-controller;
 486                         #gpio-cells = <2>;
 487                         gpio-ranges = <&pmx5 0 0 8>;
 488                         interrupt-controller;
 489                         #interrupt-cells = <2>;
 490                         clocks = <&crg_ctrl HI3670_PCLK_GPIO16>;
 491                         clock-names = "apb_pclk";
 492                 };
 493
 494                 gpio17: gpio@e8a1c000 {
 495                         compatible = "arm,pl061", "arm,primecell";
 496                         reg = <0x0 0xe8a1c000 0x0 0x1000>;
 497                         interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
 498                         gpio-controller;
 499                         #gpio-cells = <2>;
 500                         gpio-ranges = <&pmx5 0 8 2>;
 501                         interrupt-controller;
 502                         #interrupt-cells = <2>;
 503                         clocks = <&crg_ctrl HI3670_PCLK_GPIO17>;
 504                         clock-names = "apb_pclk";
 505                 };
 506
 507                 gpio18: gpio@fff28000 {
 508                         compatible = "arm,pl061", "arm,primecell";
 509                         reg = <0x0 0xfff28000 0x0 0x1000>;
 510                         interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
 511                         gpio-controller;
 512                         #gpio-cells = <2>;
 513                         gpio-ranges = <&pmx1 4 42 4>;
 514                         interrupt-controller;
 515                         #interrupt-cells = <2>;
 516                         clocks = <&sctrl HI3670_PCLK_GPIO18>;
 517                         clock-names = "apb_pclk";
 518                 };
 519
 520                 gpio19: gpio@fff29000 {
 521                         compatible = "arm,pl061", "arm,primecell";
 522                         reg = <0x0 0xfff29000 0x0 0x1000>;
 523                         interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 524                         gpio-controller;
 525                         #gpio-cells = <2>;
 526                         gpio-ranges = <&pmx1 0 61 2>;
 527                         interrupt-controller;
 528                         #interrupt-cells = <2>;
 529                         clocks = <&sctrl HI3670_PCLK_GPIO19>;
 530                         clock-names = "apb_pclk";
 531                 };
 532
 533                 gpio20: gpio@e8a1f000 {
 534                         compatible = "arm,pl061", "arm,primecell";
 535                         reg = <0x0 0xe8a1f000 0x0 0x1000>;
 536                         interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
 537                         gpio-controller;
 538                         #gpio-cells = <2>;
 539                         gpio-ranges = <&pmx7 0 0 8>;
 540                         interrupt-controller;
 541                         #interrupt-cells = <2>;
 542                         clocks = <&crg_ctrl HI3670_PCLK_GPIO20>;
 543                         clock-names = "apb_pclk";
 544                 };
 545
 546                 gpio21: gpio@e8a20000 {
 547                         compatible = "arm,pl061", "arm,primecell";
 548                         reg = <0x0 0xe8a20000 0x0 0x1000>;
 549                         interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
 550                         gpio-controller;
 551                         #gpio-cells = <2>;
 552                         gpio-ranges = <&pmx7 0 8 4>;
 553                         interrupt-controller;
 554                         #interrupt-cells = <2>;
 555                         clocks = <&crg_ctrl HI3670_PCLK_GPIO21>;
 556                         clock-names = "apb_pclk";
 557                 };
 558
 559                 gpio22: gpio@fff0b000 {
 560                         compatible = "arm,pl061", "arm,primecell";
 561                         reg = <0x0 0xfff0b000 0x0 0x1000>;
 562                         interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
 563                         gpio-controller;
 564                         #gpio-cells = <2>;
 565                         /* GPIO176 */
 566                         gpio-ranges = <&pmx1 2 0 6>;
 567                         interrupt-controller;
 568                         #interrupt-cells = <2>;
 569                         clocks = <&sctrl HI3670_PCLK_AO_GPIO0>;
 570                         clock-names = "apb_pclk";
 571                 };
 572
 573                 gpio23: gpio@fff0c000 {
 574                         compatible = "arm,pl061", "arm,primecell";
 575                         reg = <0x0 0xfff0c000 0x0 0x1000>;
 576                         interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
 577                         gpio-controller;
 578                         #gpio-cells = <2>;
 579                         /* GPIO184 */
 580                         gpio-ranges = <&pmx1 0 6 8>;
 581                         interrupt-controller;
 582                         #interrupt-cells = <2>;
 583                         clocks = <&sctrl HI3670_PCLK_AO_GPIO1>;
 584                         clock-names = "apb_pclk";
 585                 };
 586
 587                 gpio24: gpio@fff0d000 {
 588                         compatible = "arm,pl061", "arm,primecell";
 589                         reg = <0x0 0xfff0d000 0x0 0x1000>;
 590                         interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
 591                         gpio-controller;
 592                         #gpio-cells = <2>;
 593                         /* GPIO192 */
 594                         gpio-ranges = <&pmx1 0 14 8>;
 595                         interrupt-controller;
 596                         #interrupt-cells = <2>;
 597                         clocks = <&sctrl HI3670_PCLK_AO_GPIO2>;
 598                         clock-names = "apb_pclk";
 599                 };
 600
 601                 gpio25: gpio@fff0e000 {
 602                         compatible = "arm,pl061", "arm,primecell";
 603                         reg = <0x0 0xfff0e000 0x0 0x1000>;
 604                         interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
 605                         gpio-controller;
 606                         #gpio-cells = <2>;
 607                         /* GPIO200 */
 608                         gpio-ranges = <&pmx1 0 22 8>;
 609                         interrupt-controller;
 610                         #interrupt-cells = <2>;
 611                         clocks = <&sctrl HI3670_PCLK_AO_GPIO3>;
 612                         clock-names = "apb_pclk";
 613                 };
 614
 615                 gpio26: gpio@fff0f000 {
 616                         compatible = "arm,pl061", "arm,primecell";
 617                         reg = <0x0 0xfff0f000 0x0 0x1000>;
 618                         interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
 619                         gpio-controller;
 620                         #gpio-cells = <2>;
 621                         /* GPIO208 */
 622                         gpio-ranges = <&pmx1 0 30 1>;
 623                         interrupt-controller;
 624                         #interrupt-cells = <2>;
 625                         clocks = <&sctrl HI3670_PCLK_AO_GPIO4>;
 626                         clock-names = "apb_pclk";
 627                 };
 628
 629                 gpio27: gpio@fff10000 {
 630                         compatible = "arm,pl061", "arm,primecell";
 631                         reg = <0x0 0xfff10000 0x0 0x1000>;
 632                         interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
 633                         gpio-controller;
 634                         #gpio-cells = <2>;
 635                         /* GPIO216 */
 636                         gpio-ranges = <&pmx1 4 31 4>;
 637                         interrupt-controller;
 638                         #interrupt-cells = <2>;
 639                         clocks = <&sctrl HI3670_PCLK_AO_GPIO5>;
 640                         clock-names = "apb_pclk";
 641                 };
 642
 643                 gpio28: gpio@fff1d000 {
 644                         compatible = "arm,pl061", "arm,primecell";
 645                         reg = <0x0 0xfff1d000 0x0 0x1000>;
 646                         interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
 647                         gpio-controller;
 648                         #gpio-cells = <2>;
 649                         gpio-ranges = <&pmx1 1 35 7>;
 650                         interrupt-controller;
 651                         #interrupt-cells = <2>;
 652                         clocks = <&sctrl HI3670_PCLK_AO_GPIO6>;
 653                         clock-names = "apb_pclk";
 654                 };
 655
 656                 /* UFS */
 657                 ufs: ufs@ff3c0000 {
 658                         compatible = "hisilicon,hi3670-ufs", "jedec,ufs-2.1";
 659                         /* 0: HCI standard */
 660                         /* 1: UFS SYS CTRL */
 661                         reg = <0x0 0xff3c0000 0x0 0x1000>,
 662                                 <0x0 0xff3e0000 0x0 0x1000>;
 663                         interrupt-parent = <&gic>;
 664                         interrupts = <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>;
 665                         clocks = <&crg_ctrl HI3670_CLK_GATE_UFSIO_REF>,
 666                                 <&crg_ctrl HI3670_CLK_GATE_UFS_SUBSYS>;
 667                         clock-names = "ref_clk", "phy_clk";
 668                         freq-table-hz = <0 0
 669                                          0 0>;
 670                         /* offset: 0x84; bit: 12 */
 671                         resets = <&crg_rst 0x84 12>;
 672                         reset-names = "rst";
 673                 };
 674
 675                 /* SD */
 676                 dwmmc1: dwmmc1@ff37f000 {
 677                         compatible = "hisilicon,hi3670-dw-mshc",
 678                                      "hisilicon,hi3660-dw-mshc";
 679                         reg = <0x0 0xff37f000 0x0 0x1000>;
 680                         #address-cells = <1>;
 681                         #size-cells = <0>;
 682                         interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
 683                         clocks = <&crg_ctrl HI3670_CLK_GATE_SD>,
 684                                 <&crg_ctrl HI3670_HCLK_GATE_SD>;
 685                         clock-names = "ciu", "biu";
 686                         clock-frequency = <3200000>;
 687                         resets = <&crg_rst 0x94 18>;
 688                         reset-names = "reset";
 689                         hisilicon,peripheral-syscon = <&sctrl>;
 690                         card-detect-delay = <200>;
 691                         status = "disabled";
 692                 };
 693
 694                 /* SDIO */
 695                 dwmmc2: dwmmc2@fc183000 {
 696                         compatible = "hisilicon,hi3670-dw-mshc",
 697                                      "hisilicon,hi3660-dw-mshc";
 698                         reg = <0x0 0xfc183000 0x0 0x1000>;
 699                         #address-cells = <1>;
 700                         #size-cells = <0>;
 701                         interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
 702                         clocks = <&crg_ctrl HI3670_CLK_GATE_SDIO>,
 703                                 <&crg_ctrl HI3670_HCLK_GATE_SDIO>;
 704                         clock-names = "ciu", "biu";
 705                         clock-frequency = <3200000>;
 706                         resets = <&crg_rst 0x94 20>;
 707                         reset-names = "reset";
 708                         card-detect-delay = <200>;
 709                         status = "disabled";
 710                 };
 711         };
 712 };