arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi

   1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
   2 /*
   3  * Copyright 2019 Toradex
   4  */
   5
   6 / {
   7         chosen {
   8                 stdout-path = &lpuart3;
   9         };
  10
  11         colibri_gpio_keys: gpio-keys {
  12                 compatible = "gpio-keys";
  13                 pinctrl-names = "default";
  14                 pinctrl-0 = <&pinctrl_gpiokeys>;
  15                 status = "disabled";
  16
  17                 key-wakeup {
  18                         debounce-interval = <10>;
  19                         gpios = <&lsio_gpio3 10 GPIO_ACTIVE_HIGH>;
  20                         label = "Wake-Up";
  21                         linux,code = <KEY_WAKEUP>;
  22                         wakeup-source;
  23                 };
  24         };
  25
  26         reg_module_3v3: regulator-module-3v3 {
  27                 compatible = "regulator-fixed";
  28                 regulator-name = "+V3.3";
  29                 regulator-min-microvolt = <3300000>;
  30                 regulator-max-microvolt = <3300000>;
  31         };
  32 };
  33
  34 /* TODO Analogue Inputs */
  35
  36 /* TODO Cooling maps for DX */
  37
  38 &cpu_alert0 {
  39         hysteresis = <2000>;
  40         temperature = <90000>;
  41         type = "passive";
  42 };
  43
  44 &cpu_crit0 {
  45         hysteresis = <2000>;
  46         temperature = <105000>;
  47         type = "critical";
  48 };
  49
  50 /* TODO flexcan1 - 3 */
  51
  52 /* TODO GPU */
  53
  54 /* On-module I2C */
  55 &i2c0 {
  56         #address-cells = <1>;
  57         #size-cells = <0>;
  58         clock-frequency = <100000>;
  59         pinctrl-names = "default";
  60         pinctrl-0 = <&pinctrl_i2c0>, <&pinctrl_sgtl5000_usb_clk>;
  61         status = "okay";
  62
  63         /* Touch controller */
  64         touchscreen@2c {
  65                 compatible = "adi,ad7879-1";
  66                 pinctrl-names = "default";
  67                 pinctrl-0 = <&pinctrl_ad7879_int>;
  68                 reg = <0x2c>;
  69                 interrupt-parent = <&lsio_gpio3>;
  70                 interrupts = <5 IRQ_TYPE_EDGE_FALLING>;
  71                 touchscreen-max-pressure = <4096>;
  72                 adi,resistance-plate-x = <120>;
  73                 adi,first-conversion-delay = /bits/ 8 <3>;
  74                 adi,acquisition-time = /bits/ 8 <1>;
  75                 adi,median-filter-size = /bits/ 8 <2>;
  76                 adi,averaging = /bits/ 8 <1>;
  77                 adi,conversion-interval = /bits/ 8 <255>;
  78                 status = "disabled";
  79         };
  80 };
  81
  82 /* TODO i2c lvds0 accessible on FFC (X2) */
  83
  84 /* TODO i2c lvds1 accessible on FFC (X3) */
  85
  86 /* Colibri I2C */
  87 &i2c1 {
  88         #address-cells = <1>;
  89         #size-cells = <0>;
  90         clock-frequency = <100000>;
  91         pinctrl-names = "default";
  92         pinctrl-0 = <&pinctrl_i2c1>;
  93 };
  94
  95 &jpegdec {
  96         status = "okay";
  97 };
  98
  99 &jpegenc {
 100         status = "okay";
 101 };
 102
 103 /* TODO Parallel RRB */
 104
 105 /* Colibri UART_B */
 106 &lpuart0 {
 107         pinctrl-names = "default";
 108         pinctrl-0 = <&pinctrl_lpuart0>;
 109 };
 110
 111 /* Colibri UART_C */
 112 &lpuart2 {
 113         pinctrl-names = "default";
 114         pinctrl-0 = <&pinctrl_lpuart2>;
 115 };
 116
 117 /* Colibri UART_A */
 118 &lpuart3 {
 119         pinctrl-names = "default";
 120         pinctrl-0 = <&pinctrl_lpuart3>, <&pinctrl_lpuart3_ctrl>;
 121 };
 122
 123 /* Colibri FastEthernet */
 124 &fec1 {
 125         pinctrl-names = "default", "sleep";
 126         pinctrl-0 = <&pinctrl_fec1>;
 127         pinctrl-1 = <&pinctrl_fec1_sleep>;
 128         phy-mode = "rmii";
 129         phy-handle = <&ethphy0>;
 130         fsl,magic-packet;
 131
 132         mdio {
 133                 #address-cells = <1>;
 134                 #size-cells = <0>;
 135
 136                 ethphy0: ethernet-phy@2 {
 137                         compatible = "ethernet-phy-ieee802.3-c22";
 138                         max-speed = <100>;
 139                         reg = <2>;
 140                 };
 141         };
 142 };
 143
 144 /* Colibri SPI */
 145 &lpspi2 {
 146         pinctrl-names = "default";
 147         pinctrl-0 = <&pinctrl_lpspi2>;
 148         cs-gpios = <&lsio_gpio1 0 GPIO_ACTIVE_LOW>;
 149 };
 150
 151 &lsio_gpio0 {
 152         gpio-line-names = "",
 153                           "SODIMM_70",
 154                           "SODIMM_60",
 155                           "SODIMM_58",
 156                           "SODIMM_78",
 157                           "SODIMM_72",
 158                           "SODIMM_80",
 159                           "SODIMM_46",
 160                           "SODIMM_62",
 161                           "SODIMM_48",
 162                           "SODIMM_74",
 163                           "SODIMM_50",
 164                           "SODIMM_52",
 165                           "SODIMM_54",
 166                           "SODIMM_66",
 167                           "SODIMM_64",
 168                           "SODIMM_68",
 169                           "",
 170                           "",
 171                           "SODIMM_82",
 172                           "SODIMM_56",
 173                           "SODIMM_28",
 174                           "SODIMM_30",
 175                           "",
 176                           "SODIMM_61",
 177                           "SODIMM_103",
 178                           "",
 179                           "",
 180                           "",
 181                           "SODIMM_25",
 182                           "SODIMM_27",
 183                           "SODIMM_100";
 184 };
 185
 186 &lsio_gpio1 {
 187         gpio-line-names = "SODIMM_86",
 188                           "SODIMM_92",
 189                           "SODIMM_90",
 190                           "SODIMM_88",
 191                           "",
 192                           "",
 193                           "",
 194                           "SODIMM_59",
 195                           "",
 196                           "SODIMM_6",
 197                           "SODIMM_8",
 198                           "",
 199                           "",
 200                           "SODIMM_2",
 201                           "SODIMM_4",
 202                           "SODIMM_34",
 203                           "SODIMM_32",
 204                           "SODIMM_63",
 205                           "SODIMM_55",
 206                           "SODIMM_33",
 207                           "SODIMM_35",
 208                           "SODIMM_36",
 209                           "SODIMM_38",
 210                           "SODIMM_21",
 211                           "SODIMM_19",
 212                           "SODIMM_140",
 213                           "SODIMM_142",
 214                           "SODIMM_196",
 215                           "SODIMM_194",
 216                           "SODIMM_186",
 217                           "SODIMM_188",
 218                           "SODIMM_138";
 219 };
 220
 221 &lsio_gpio2 {
 222         gpio-line-names = "SODIMM_23",
 223                           "",
 224                           "",
 225                           "SODIMM_144";
 226 };
 227
 228 &lsio_gpio3 {
 229         gpio-line-names = "SODIMM_96",
 230                           "SODIMM_75",
 231                           "SODIMM_37",
 232                           "SODIMM_29",
 233                           "",
 234                           "",
 235                           "",
 236                           "",
 237                           "",
 238                           "SODIMM_43",
 239                           "SODIMM_45",
 240                           "SODIMM_69",
 241                           "SODIMM_71",
 242                           "SODIMM_73",
 243                           "SODIMM_77",
 244                           "SODIMM_89",
 245                           "SODIMM_93",
 246                           "SODIMM_95",
 247                           "SODIMM_99",
 248                           "SODIMM_105",
 249                           "SODIMM_107",
 250                           "SODIMM_98",
 251                           "SODIMM_102",
 252                           "SODIMM_104",
 253                           "SODIMM_106";
 254 };
 255
 256 &lsio_gpio4 {
 257         gpio-line-names = "",
 258                           "",
 259                           "",
 260                           "SODIMM_129",
 261                           "SODIMM_133",
 262                           "SODIMM_127",
 263                           "SODIMM_131",
 264                           "",
 265                           "",
 266                           "",
 267                           "",
 268                           "",
 269                           "",
 270                           "",
 271                           "",
 272                           "",
 273                           "",
 274                           "",
 275                           "",
 276                           "SODIMM_44",
 277                           "",
 278                           "SODIMM_76",
 279                           "SODIMM_31",
 280                           "SODIMM_47",
 281                           "SODIMM_190",
 282                           "SODIMM_192",
 283                           "SODIMM_49",
 284                           "SODIMM_51",
 285                           "SODIMM_53";
 286 };
 287
 288 &lsio_gpio5 {
 289         gpio-line-names = "",
 290                           "SODIMM_57",
 291                           "SODIMM_65",
 292                           "SODIMM_85",
 293                           "",
 294                           "",
 295                           "",
 296                           "",
 297                           "SODIMM_135",
 298                           "SODIMM_137",
 299                           "UNUSABLE_SODIMM_180",
 300                           "UNUSABLE_SODIMM_184";
 301 };
 302
 303 /* Colibri PWM_B */
 304 &lsio_pwm0 {
 305         #pwm-cells = <3>;
 306         pinctrl-0 = <&pinctrl_pwm_b>;
 307         pinctrl-names = "default";
 308 };
 309
 310 /* Colibri PWM_C */
 311 &lsio_pwm1 {
 312         #pwm-cells = <3>;
 313         pinctrl-0 = <&pinctrl_pwm_c>;
 314         pinctrl-names = "default";
 315 };
 316
 317 /* Colibri PWM_D */
 318 &lsio_pwm2 {
 319         #pwm-cells = <3>;
 320         pinctrl-0 = <&pinctrl_pwm_d>;
 321         pinctrl-names = "default";
 322 };
 323
 324 /* TODO MIPI CSI */
 325
 326 /* TODO MIPI DSI with DSI-to-HDMI bridge lt8912 */
 327
 328 /* TODO on-module PCIe for Wi-Fi */
 329
 330 /* TODO On-module i2s / Audio */
 331
 332 /* On-module eMMC */
 333 &usdhc1 {
 334         bus-width = <8>;
 335         non-removable;
 336         no-sd;
 337         no-sdio;
 338         pinctrl-names = "default", "state_100mhz", "state_200mhz";
 339         pinctrl-0 = <&pinctrl_usdhc1>;
 340         pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
 341         pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
 342         status = "okay";
 343 };
 344
 345 /* Colibri SD/MMC Card */
 346 &usdhc2 {
 347         bus-width = <4>;
 348         cd-gpios = <&lsio_gpio3 9 GPIO_ACTIVE_LOW>;
 349         vmmc-supply = <&reg_module_3v3>;
 350         pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
 351         pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
 352         pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
 353         pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
 354         pinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_usdhc2_gpio_sleep>;
 355         disable-wp;
 356         no-1-8-v;
 357 };
 358
 359 /* TODO USB Client/Host */
 360
 361 /* TODO USB Host */
 362
 363 /* TODO VPU Encoder/Decoder */
 364
 365 &iomuxc {
 366         /* On-module touch pen-down interrupt */
 367         pinctrl_ad7879_int: ad7879intgrp {
 368                 fsl,pins = <IMX8QXP_MIPI_CSI0_I2C0_SCL_LSIO_GPIO3_IO05  0x21>;
 369         };
 370
 371         /* Colibri Analogue Inputs */
 372         pinctrl_adc0: adc0grp {
 373                 fsl,pins = <IMX8QXP_ADC_IN0_ADMA_ADC_IN0                        0x60>,          /* SODIMM   8 */
 374                            <IMX8QXP_ADC_IN1_ADMA_ADC_IN1                        0x60>,          /* SODIMM   6 */
 375                            <IMX8QXP_ADC_IN4_ADMA_ADC_IN4                        0x60>,          /* SODIMM   4 */
 376                            <IMX8QXP_ADC_IN5_ADMA_ADC_IN5                        0x60>;          /* SODIMM   2 */
 377         };
 378
 379         /* Atmel MXT touchsceen + Capacitive Touch Adapter */
 380         /* NOTE: This pingroup conflicts with pingroups
 381          * pinctrl_pwm_b/pinctrl_pwm_c. Don't enable them
 382          * simultaneously.
 383          */
 384         pinctrl_atmel_adap: atmeladaptergrp {
 385                 fsl,pins = <IMX8QXP_UART1_RX_LSIO_GPIO0_IO22                    0x21>,          /* SODIMM  30 */
 386                            <IMX8QXP_UART1_TX_LSIO_GPIO0_IO21                    0x4000021>;     /* SODIMM  28 */
 387         };
 388
 389         /* Atmel MXT touchsceen + boards with built-in Capacitive Touch Connector */
 390         pinctrl_atmel_conn: atmelconnectorgrp {
 391                 fsl,pins = <IMX8QXP_QSPI0B_DATA2_LSIO_GPIO3_IO20                0x4000021>,     /* SODIMM 107 */
 392                            <IMX8QXP_QSPI0B_SS1_B_LSIO_GPIO3_IO24                0x21>;          /* SODIMM 106 */
 393         };
 394
 395         pinctrl_can_int: canintgrp {
 396                 fsl,pins = <IMX8QXP_QSPI0A_DQS_LSIO_GPIO3_IO13                  0x40>;          /* SODIMM  73 */
 397         };
 398
 399         pinctrl_csi_ctl: csictlgrp {
 400                 fsl,pins = <IMX8QXP_QSPI0A_SS0_B_LSIO_GPIO3_IO14                0x20>,          /* SODIMM  77 */
 401                            <IMX8QXP_QSPI0A_SS1_B_LSIO_GPIO3_IO15                0x20>;          /* SODIMM  89 */
 402         };
 403
 404         pinctrl_csi_mclk: csimclkgrp {
 405                 fsl,pins = <IMX8QXP_CSI_MCLK_CI_PI_MCLK                         0xC0000041>;    /* SODIMM  75 / X3-12 */
 406         };
 407
 408         pinctrl_ext_io0: extio0grp {
 409                 fsl,pins = <IMX8QXP_ENET0_RGMII_RXD3_LSIO_GPIO5_IO08            0x06000040>;    /* SODIMM 135 */
 410         };
 411
 412         /* Colibri Ethernet: On-module 100Mbps PHY Micrel KSZ8041 */
 413         pinctrl_fec1: fec1grp {
 414                 fsl,pins = <IMX8QXP_ENET0_MDC_CONN_ENET0_MDC                    0x06000020>,
 415                            <IMX8QXP_ENET0_MDIO_CONN_ENET0_MDIO                  0x06000020>,
 416                            <IMX8QXP_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL  0x61>,
 417                            <IMX8QXP_ENET0_RGMII_TXC_CONN_ENET0_RCLK50M_OUT      0x06000061>,
 418                            <IMX8QXP_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0      0x61>,
 419                            <IMX8QXP_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1      0x61>,
 420                            <IMX8QXP_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL  0x61>,
 421                            <IMX8QXP_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0      0x61>,
 422                            <IMX8QXP_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1      0x61>,
 423                            <IMX8QXP_ENET0_RGMII_RXD2_CONN_ENET0_RMII_RX_ER      0x61>;
 424         };
 425
 426         pinctrl_fec1_sleep: fec1slpgrp {
 427                 fsl,pins = <IMX8QXP_ENET0_MDC_LSIO_GPIO5_IO11                   0x06000041>,
 428                            <IMX8QXP_ENET0_MDIO_LSIO_GPIO5_IO10                  0x06000041>,
 429                            <IMX8QXP_ENET0_RGMII_TX_CTL_LSIO_GPIO4_IO30          0x41>,
 430                            <IMX8QXP_ENET0_RGMII_TXC_LSIO_GPIO4_IO29             0x41>,
 431                            <IMX8QXP_ENET0_RGMII_TXD0_LSIO_GPIO4_IO31            0x41>,
 432                            <IMX8QXP_ENET0_RGMII_TXD1_LSIO_GPIO5_IO00            0x41>,
 433                            <IMX8QXP_ENET0_RGMII_RX_CTL_LSIO_GPIO5_IO04          0x41>,
 434                            <IMX8QXP_ENET0_RGMII_RXD0_LSIO_GPIO5_IO05            0x41>,
 435                            <IMX8QXP_ENET0_RGMII_RXD1_LSIO_GPIO5_IO06            0x41>,
 436                            <IMX8QXP_ENET0_RGMII_RXD2_LSIO_GPIO5_IO07            0x41>;
 437         };
 438
 439         /* Colibri optional CAN on UART_B RTS/CTS */
 440         pinctrl_flexcan1: flexcan0grp {
 441                 fsl,pins = <IMX8QXP_FLEXCAN0_TX_ADMA_FLEXCAN0_TX                0x21>,          /* SODIMM  32 */
 442                            <IMX8QXP_FLEXCAN0_RX_ADMA_FLEXCAN0_RX                0x21>;          /* SODIMM  34 */
 443         };
 444
 445         /* Colibri optional CAN on PS2 */
 446         pinctrl_flexcan2: flexcan1grp {
 447                 fsl,pins = <IMX8QXP_FLEXCAN1_TX_ADMA_FLEXCAN1_TX                0x21>,          /* SODIMM  55 */
 448                            <IMX8QXP_FLEXCAN1_RX_ADMA_FLEXCAN1_RX                0x21>;          /* SODIMM  63 */
 449         };
 450
 451         /* Colibri optional CAN on UART_A TXD/RXD */
 452         pinctrl_flexcan3: flexcan2grp {
 453                 fsl,pins = <IMX8QXP_FLEXCAN2_TX_ADMA_FLEXCAN2_TX                0x21>,          /* SODIMM  35 */
 454                            <IMX8QXP_FLEXCAN2_RX_ADMA_FLEXCAN2_RX                0x21>;          /* SODIMM  33 */
 455         };
 456
 457         /* Colibri LCD Back-Light GPIO */
 458         pinctrl_gpio_bl_on: gpioblongrp {
 459                 fsl,pins = <IMX8QXP_QSPI0A_DATA3_LSIO_GPIO3_IO12                0x60>;          /* SODIMM  71 */
 460         };
 461
 462         /* HDMI Hot Plug Detect on FFC (X2) */
 463         pinctrl_gpio_hpd: gpiohpdgrp {
 464                 fsl,pins = <IMX8QXP_MIPI_DSI1_GPIO0_00_LSIO_GPIO1_IO31          0x20>;          /* SODIMM 138 */
 465         };
 466
 467         pinctrl_gpiokeys: gpiokeysgrp {
 468                 fsl,pins = <IMX8QXP_QSPI0A_DATA1_LSIO_GPIO3_IO10                0x06700041>;    /* SODIMM  45 */
 469         };
 470
 471         pinctrl_hog0: hog0grp {
 472                 fsl,pins = <IMX8QXP_CSI_D07_CI_PI_D09                           0x61>,          /* SODIMM  65 */
 473                            <IMX8QXP_QSPI0A_DATA2_LSIO_GPIO3_IO11                0x20>,          /* SODIMM  69 */
 474                            <IMX8QXP_SAI0_TXC_LSIO_GPIO0_IO26                    0x20>,          /* SODIMM  79 */
 475                            <IMX8QXP_CSI_D02_CI_PI_D04                           0x61>,          /* SODIMM  79 */
 476                            <IMX8QXP_ENET0_RGMII_RXC_LSIO_GPIO5_IO03             0x06000020>,    /* SODIMM  85 */
 477                            <IMX8QXP_CSI_D06_CI_PI_D08                           0x61>,          /* SODIMM  85 */
 478                            <IMX8QXP_QSPI0B_SCLK_LSIO_GPIO3_IO17                 0x20>,          /* SODIMM  95 */
 479                            <IMX8QXP_SAI0_RXD_LSIO_GPIO0_IO27                    0x20>,          /* SODIMM  97 */
 480                            <IMX8QXP_CSI_D03_CI_PI_D05                           0x61>,          /* SODIMM  97 */
 481                            <IMX8QXP_QSPI0B_DATA0_LSIO_GPIO3_IO18                0x20>,          /* SODIMM  99 */
 482                            <IMX8QXP_SAI0_TXFS_LSIO_GPIO0_IO28                   0x20>,          /* SODIMM 101 */
 483                            <IMX8QXP_CSI_D00_CI_PI_D02                           0x61>,          /* SODIMM 101 */
 484                            <IMX8QXP_SAI0_TXD_LSIO_GPIO0_IO25                    0x20>,          /* SODIMM 103 */
 485                            <IMX8QXP_CSI_D01_CI_PI_D03                           0x61>,          /* SODIMM 103 */
 486                            <IMX8QXP_QSPI0B_DATA1_LSIO_GPIO3_IO19                0x20>,          /* SODIMM 105 */
 487                            <IMX8QXP_USB_SS3_TC2_LSIO_GPIO4_IO05                 0x20>,          /* SODIMM 127 */
 488                            <IMX8QXP_USB_SS3_TC3_LSIO_GPIO4_IO06                 0x20>,          /* SODIMM 131 */
 489                            <IMX8QXP_USB_SS3_TC1_LSIO_GPIO4_IO04                 0x20>,          /* SODIMM 133 */
 490                            <IMX8QXP_CSI_PCLK_LSIO_GPIO3_IO00                    0x20>,          /* SODIMM  96 */
 491                            <IMX8QXP_QSPI0B_DATA3_LSIO_GPIO3_IO21                0x20>,          /* SODIMM  98 */
 492                            <IMX8QXP_SAI1_RXFS_LSIO_GPIO0_IO31                   0x20>,          /* SODIMM 100 */
 493                            <IMX8QXP_QSPI0B_DQS_LSIO_GPIO3_IO22                  0x20>,          /* SODIMM 102 */
 494                            <IMX8QXP_QSPI0B_SS0_B_LSIO_GPIO3_IO23                0x20>;          /* SODIMM 104 */
 495         };
 496
 497         pinctrl_hog1: hog1grp {
 498                 fsl,pins = <IMX8QXP_QSPI0A_SCLK_LSIO_GPIO3_IO16                 0x20>;          /* SODIMM  93 */
 499         };
 500
 501         pinctrl_hog2: hog2grp {
 502                 fsl,pins = <IMX8QXP_CSI_MCLK_LSIO_GPIO3_IO01                    0x20>;          /* SODIMM  75 */
 503         };
 504
 505         /*
 506          * This pin is used in the SCFW as a UART. Using it from
 507          * Linux would require rewritting the SCFW board file.
 508          */
 509         pinctrl_hog_scfw: hogscfwgrp {
 510                 fsl,pins = <IMX8QXP_SCU_GPIO0_00_LSIO_GPIO2_IO03                0x20>;          /* SODIMM 144 */
 511         };
 512
 513         /* On Module I2C */
 514         pinctrl_i2c0: i2c0grp {
 515                 fsl,pins = <IMX8QXP_MIPI_CSI0_GPIO0_00_ADMA_I2C0_SCL            0x06000021>,
 516                            <IMX8QXP_MIPI_CSI0_GPIO0_01_ADMA_I2C0_SDA            0x06000021>;
 517         };
 518
 519         /* MIPI DSI I2C accessible on SODIMM (X1) and FFC (X2) */
 520         pinctrl_i2c0_mipi_lvds0: i2c0mipilvds0grp {
 521                 fsl,pins = <IMX8QXP_MIPI_DSI0_I2C0_SCL_MIPI_DSI0_I2C0_SCL       0xc6000020>,    /* SODIMM 140 */
 522                            <IMX8QXP_MIPI_DSI0_I2C0_SDA_MIPI_DSI0_I2C0_SDA       0xc6000020>;    /* SODIMM 142 */
 523         };
 524
 525         /* MIPI CSI I2C accessible on SODIMM (X1) and FFC (X3) */
 526         pinctrl_i2c0_mipi_lvds1: i2c0mipilvds1grp {
 527                 fsl,pins = <IMX8QXP_MIPI_DSI1_I2C0_SCL_MIPI_DSI1_I2C0_SCL       0xc6000020>,    /* SODIMM 186 */
 528                            <IMX8QXP_MIPI_DSI1_I2C0_SDA_MIPI_DSI1_I2C0_SDA       0xc6000020>;    /* SODIMM 188 */
 529         };
 530
 531         /* Colibri I2C */
 532         pinctrl_i2c1: i2c1grp {
 533                 fsl,pins = <IMX8QXP_MIPI_DSI0_GPIO0_00_ADMA_I2C1_SCL            0x06000021>,    /* SODIMM 196 */
 534                            <IMX8QXP_MIPI_DSI0_GPIO0_01_ADMA_I2C1_SDA            0x06000021>;    /* SODIMM 194 */
 535         };
 536
 537         /* Colibri Parallel RGB LCD Interface */
 538         pinctrl_lcdif: lcdifgrp {
 539                 fsl,pins = <IMX8QXP_MCLK_OUT0_ADMA_LCDIF_CLK                    0x60>,          /* SODIMM  56 */
 540                            <IMX8QXP_SPI3_CS0_ADMA_LCDIF_HSYNC                   0x60>,          /* SODIMM  68 */
 541                            <IMX8QXP_MCLK_IN0_ADMA_LCDIF_VSYNC                   0x60>,          /* SODIMM  82 */
 542                            <IMX8QXP_MCLK_IN1_ADMA_LCDIF_EN                      0x40>,          /* SODIMM  44 */
 543                            <IMX8QXP_USDHC1_RESET_B_LSIO_GPIO4_IO19              0x40>,          /* SODIMM  44 */
 544                            <IMX8QXP_ESAI0_FSR_ADMA_LCDIF_D00                    0x60>,          /* SODIMM  76 */
 545                            <IMX8QXP_USDHC1_WP_LSIO_GPIO4_IO21                   0x60>,          /* SODIMM  76 */
 546                            <IMX8QXP_ESAI0_FST_ADMA_LCDIF_D01                    0x60>,          /* SODIMM  70 */
 547                            <IMX8QXP_ESAI0_SCKR_ADMA_LCDIF_D02                   0x60>,          /* SODIMM  60 */
 548                            <IMX8QXP_ESAI0_SCKT_ADMA_LCDIF_D03                   0x60>,          /* SODIMM  58 */
 549                            <IMX8QXP_ESAI0_TX0_ADMA_LCDIF_D04                    0x60>,          /* SODIMM  78 */
 550                            <IMX8QXP_ESAI0_TX1_ADMA_LCDIF_D05                    0x60>,          /* SODIMM  72 */
 551                            <IMX8QXP_ESAI0_TX2_RX3_ADMA_LCDIF_D06                0x60>,          /* SODIMM  80 */
 552                            <IMX8QXP_ESAI0_TX3_RX2_ADMA_LCDIF_D07                0x60>,          /* SODIMM  46 */
 553                            <IMX8QXP_ESAI0_TX4_RX1_ADMA_LCDIF_D08                0x60>,          /* SODIMM  62 */
 554                            <IMX8QXP_ESAI0_TX5_RX0_ADMA_LCDIF_D09                0x60>,          /* SODIMM  48 */
 555                            <IMX8QXP_SPDIF0_RX_ADMA_LCDIF_D10                    0x60>,          /* SODIMM  74 */
 556                            <IMX8QXP_SPDIF0_TX_ADMA_LCDIF_D11                    0x60>,          /* SODIMM  50 */
 557                            <IMX8QXP_SPDIF0_EXT_CLK_ADMA_LCDIF_D12               0x60>,          /* SODIMM  52 */
 558                            <IMX8QXP_SPI3_SCK_ADMA_LCDIF_D13                     0x60>,          /* SODIMM  54 */
 559                            <IMX8QXP_SPI3_SDO_ADMA_LCDIF_D14                     0x60>,          /* SODIMM  66 */
 560                            <IMX8QXP_SPI3_SDI_ADMA_LCDIF_D15                     0x60>,          /* SODIMM  64 */
 561                            <IMX8QXP_SPI3_CS1_ADMA_LCDIF_D16                     0x60>,          /* SODIMM  57 */
 562                            <IMX8QXP_ENET0_RGMII_TXD2_LSIO_GPIO5_IO01            0x60>,          /* SODIMM  57 */
 563                            <IMX8QXP_UART1_CTS_B_ADMA_LCDIF_D17                  0x60>;          /* SODIMM  61 */
 564         };
 565
 566         /* Colibri SPI */
 567         pinctrl_lpspi2: lpspi2grp {
 568                 fsl,pins = <IMX8QXP_SPI2_CS0_LSIO_GPIO1_IO00                    0x21>,          /* SODIMM  86 */
 569                            <IMX8QXP_SPI2_SDO_ADMA_SPI2_SDO                      0x06000040>,    /* SODIMM  92 */
 570                            <IMX8QXP_SPI2_SDI_ADMA_SPI2_SDI                      0x06000040>,    /* SODIMM  90 */
 571                            <IMX8QXP_SPI2_SCK_ADMA_SPI2_SCK                      0x06000040>;    /* SODIMM  88 */
 572         };
 573
 574         pinctrl_lpspi2_cs2: lpspi2cs2grp {
 575                 fsl,pins = <IMX8QXP_ENET0_RGMII_TXD3_LSIO_GPIO5_IO02            0x21>;          /* SODIMM  65 */
 576         };
 577
 578         /* Colibri UART_B */
 579         pinctrl_lpuart0: lpuart0grp {
 580                 fsl,pins = <IMX8QXP_UART0_RX_ADMA_UART0_RX                      0x06000020>,    /* SODIMM  36 */
 581                            <IMX8QXP_UART0_TX_ADMA_UART0_TX                      0x06000020>,    /* SODIMM  38 */
 582                            <IMX8QXP_FLEXCAN0_RX_ADMA_UART0_RTS_B                0x06000020>,    /* SODIMM  34 */
 583                            <IMX8QXP_FLEXCAN0_TX_ADMA_UART0_CTS_B                0x06000020>;    /* SODIMM  32 */
 584         };
 585
 586         /* Colibri UART_C */
 587         pinctrl_lpuart2: lpuart2grp {
 588                 fsl,pins = <IMX8QXP_UART2_RX_ADMA_UART2_RX                      0x06000020>,    /* SODIMM  19 */
 589                            <IMX8QXP_UART2_TX_ADMA_UART2_TX                      0x06000020>;    /* SODIMM  21 */
 590         };
 591
 592         /* Colibri UART_A */
 593         pinctrl_lpuart3: lpuart3grp {
 594                 fsl,pins = <IMX8QXP_FLEXCAN2_RX_ADMA_UART3_RX                   0x06000020>,    /* SODIMM  33 */
 595                            <IMX8QXP_FLEXCAN2_TX_ADMA_UART3_TX                   0x06000020>;    /* SODIMM  35 */
 596         };
 597
 598         /* Colibri UART_A Control */
 599         pinctrl_lpuart3_ctrl: lpuart3ctrlgrp {
 600                 fsl,pins = <IMX8QXP_MIPI_DSI1_GPIO0_01_LSIO_GPIO2_IO00          0x20>,          /* SODIMM  23 */
 601                            <IMX8QXP_SAI1_RXD_LSIO_GPIO0_IO29                    0x20>,          /* SODIMM  25 */
 602                            <IMX8QXP_SAI1_RXC_LSIO_GPIO0_IO30                    0x20>,          /* SODIMM  27 */
 603                            <IMX8QXP_CSI_RESET_LSIO_GPIO3_IO03                   0x20>,          /* SODIMM  29 */
 604                            <IMX8QXP_USDHC1_CD_B_LSIO_GPIO4_IO22                 0x20>,          /* SODIMM  31 */
 605                            <IMX8QXP_CSI_EN_LSIO_GPIO3_IO02                      0x20>;          /* SODIMM  37 */
 606         };
 607
 608         /* On module wifi module */
 609         pinctrl_pcieb: pciebgrp {
 610                 fsl,pins = <IMX8QXP_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO01         0x04000061>,    /* SODIMM 178 */
 611                            <IMX8QXP_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO02           0x04000061>,    /* SODIMM  94 */
 612                            <IMX8QXP_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO00          0x60>;          /* SODIMM  81 */
 613         };
 614
 615         /* Colibri PWM_A */
 616         pinctrl_pwm_a: pwmagrp {
 617         /* both pins are connected together, reserve the unused CSI_D05 */
 618                 fsl,pins = <IMX8QXP_CSI_D05_CI_PI_D07                           0x61>,          /* SODIMM  59 */
 619                            <IMX8QXP_SPI0_CS1_ADMA_LCD_PWM0_OUT                  0x60>;          /* SODIMM  59 */
 620         };
 621
 622         /* Colibri PWM_B */
 623         pinctrl_pwm_b: pwmbgrp {
 624                 fsl,pins = <IMX8QXP_UART1_TX_LSIO_PWM0_OUT                      0x60>;          /* SODIMM  28 */
 625         };
 626
 627         /* Colibri PWM_C */
 628         pinctrl_pwm_c: pwmcgrp {
 629                 fsl,pins = <IMX8QXP_UART1_RX_LSIO_PWM1_OUT                      0x60>;          /* SODIMM  30 */
 630         };
 631
 632         /* Colibri PWM_D */
 633         pinctrl_pwm_d: pwmdgrp {
 634         /* both pins are connected together, reserve the unused CSI_D04 */
 635                 fsl,pins = <IMX8QXP_CSI_D04_CI_PI_D06                           0x61>,          /* SODIMM  67 */
 636                            <IMX8QXP_UART1_RTS_B_LSIO_PWM2_OUT                   0x60>;          /* SODIMM  67 */
 637         };
 638
 639         /* On-module I2S */
 640         pinctrl_sai0: sai0grp {
 641                 fsl,pins = <IMX8QXP_SPI0_SDI_ADMA_SAI0_TXD                      0x06000040>,
 642                            <IMX8QXP_SPI0_CS0_ADMA_SAI0_RXD                      0x06000040>,
 643                            <IMX8QXP_SPI0_SCK_ADMA_SAI0_TXC                      0x06000040>,
 644                            <IMX8QXP_SPI0_SDO_ADMA_SAI0_TXFS                     0x06000040>;
 645         };
 646
 647         /* Colibri Audio Analogue Microphone GND */
 648         pinctrl_sgtl5000: sgtl5000grp {
 649                 fsl,pins = <IMX8QXP_MIPI_CSI0_I2C0_SDA_LSIO_GPIO3_IO06          0x41>;
 650         };
 651
 652         /* On-module SGTL5000 clock */
 653         pinctrl_sgtl5000_usb_clk: sgtl5000usbclkgrp {
 654                 fsl,pins = <IMX8QXP_ADC_IN3_ADMA_ACM_MCLK_OUT0                  0x21>;
 655         };
 656
 657         /* On-module USB interrupt */
 658         pinctrl_usb3503a: usb3503agrp {
 659                 fsl,pins = <IMX8QXP_MIPI_CSI0_MCLK_OUT_LSIO_GPIO3_IO04          0x61>;
 660         };
 661
 662         /* Colibri USB Client Cable Detect */
 663         pinctrl_usbc_det: usbcdetgrp {
 664                 fsl,pins = <IMX8QXP_ENET0_REFCLK_125M_25M_LSIO_GPIO5_IO09       0x06000040>;    /* SODIMM 137 */
 665         };
 666
 667         /* USB Host Power Enable */
 668         pinctrl_usbh1_reg: usbh1reggrp {
 669                 fsl,pins = <IMX8QXP_USB_SS3_TC0_LSIO_GPIO4_IO03                 0x06000040>;    /* SODIMM 129 */
 670         };
 671
 672         /* On-module eMMC */
 673         pinctrl_usdhc1: usdhc1grp {
 674                 fsl,pins = <IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK                    0x06000041>,
 675                            <IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD                    0x21>,
 676                            <IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0                0x21>,
 677                            <IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1                0x21>,
 678                            <IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2                0x21>,
 679                            <IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3                0x21>,
 680                            <IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4                0x21>,
 681                            <IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5                0x21>,
 682                            <IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6                0x21>,
 683                            <IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7                0x21>,
 684                            <IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE              0x41>,
 685                            <IMX8QXP_EMMC0_RESET_B_CONN_EMMC0_RESET_B            0x21>;
 686         };
 687
 688         pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
 689                 fsl,pins = <IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK                    0x06000041>,
 690                            <IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD                    0x21>,
 691                            <IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0                0x21>,
 692                            <IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1                0x21>,
 693                            <IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2                0x21>,
 694                            <IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3                0x21>,
 695                            <IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4                0x21>,
 696                            <IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5                0x21>,
 697                            <IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6                0x21>,
 698                            <IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7                0x21>,
 699                            <IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE              0x41>,
 700                            <IMX8QXP_EMMC0_RESET_B_CONN_EMMC0_RESET_B            0x21>;
 701         };
 702
 703         pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
 704                 fsl,pins = <IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK                    0x06000041>,
 705                            <IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD                    0x21>,
 706                            <IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0                0x21>,
 707                            <IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1                0x21>,
 708                            <IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2                0x21>,
 709                            <IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3                0x21>,
 710                            <IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4                0x21>,
 711                            <IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5                0x21>,
 712                            <IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6                0x21>,
 713                            <IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7                0x21>,
 714                            <IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE              0x41>,
 715                            <IMX8QXP_EMMC0_RESET_B_CONN_EMMC0_RESET_B            0x21>;
 716         };
 717
 718         /* Colibri SD/MMC Card Detect */
 719         pinctrl_usdhc2_gpio: usdhc2gpiogrp {
 720                 fsl,pins = <IMX8QXP_QSPI0A_DATA0_LSIO_GPIO3_IO09                0x06000021>;    /* SODIMM  43 */
 721         };
 722
 723         pinctrl_usdhc2_gpio_sleep: usdhc2gpioslpgrp {
 724                 fsl,pins = <IMX8QXP_QSPI0A_DATA0_LSIO_GPIO3_IO09                0x60>;          /* SODIMM  43 */
 725         };
 726
 727         /* Colibri SD/MMC Card */
 728         pinctrl_usdhc2: usdhc2grp {
 729                 fsl,pins = <IMX8QXP_USDHC1_CLK_CONN_USDHC1_CLK                  0x06000041>,    /* SODIMM  47 */
 730                            <IMX8QXP_USDHC1_CMD_CONN_USDHC1_CMD                  0x21>,          /* SODIMM 190 */
 731                            <IMX8QXP_USDHC1_DATA0_CONN_USDHC1_DATA0              0x21>,          /* SODIMM 192 */
 732                            <IMX8QXP_USDHC1_DATA1_CONN_USDHC1_DATA1              0x21>,          /* SODIMM  49 */
 733                            <IMX8QXP_USDHC1_DATA2_CONN_USDHC1_DATA2              0x21>,          /* SODIMM  51 */
 734                            <IMX8QXP_USDHC1_DATA3_CONN_USDHC1_DATA3              0x21>,          /* SODIMM  53 */
 735                            <IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT          0x21>;
 736         };
 737
 738         pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
 739                 fsl,pins = <IMX8QXP_USDHC1_CLK_CONN_USDHC1_CLK                  0x06000041>,    /* SODIMM  47 */
 740                            <IMX8QXP_USDHC1_CMD_CONN_USDHC1_CMD                  0x21>,          /* SODIMM 190 */
 741                            <IMX8QXP_USDHC1_DATA0_CONN_USDHC1_DATA0              0x21>,          /* SODIMM 192 */
 742                            <IMX8QXP_USDHC1_DATA1_CONN_USDHC1_DATA1              0x21>,          /* SODIMM  49 */
 743                            <IMX8QXP_USDHC1_DATA2_CONN_USDHC1_DATA2              0x21>,          /* SODIMM  51 */
 744                            <IMX8QXP_USDHC1_DATA3_CONN_USDHC1_DATA3              0x21>,          /* SODIMM  53 */
 745                            <IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT          0x21>;
 746         };
 747
 748         pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
 749                 fsl,pins = <IMX8QXP_USDHC1_CLK_CONN_USDHC1_CLK                  0x06000041>,    /* SODIMM  47 */
 750                            <IMX8QXP_USDHC1_CMD_CONN_USDHC1_CMD                  0x21>,          /* SODIMM 190 */
 751                            <IMX8QXP_USDHC1_DATA0_CONN_USDHC1_DATA0              0x21>,          /* SODIMM 192 */
 752                            <IMX8QXP_USDHC1_DATA1_CONN_USDHC1_DATA1              0x21>,          /* SODIMM  49 */
 753                            <IMX8QXP_USDHC1_DATA2_CONN_USDHC1_DATA2              0x21>,          /* SODIMM  51 */
 754                            <IMX8QXP_USDHC1_DATA3_CONN_USDHC1_DATA3              0x21>,          /* SODIMM  53 */
 755                            <IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT          0x21>;
 756         };
 757
 758         pinctrl_usdhc2_sleep: usdhc2slpgrp {
 759                 fsl,pins = <IMX8QXP_USDHC1_CLK_LSIO_GPIO4_IO23                  0x60>,          /* SODIMM  47 */
 760                            <IMX8QXP_USDHC1_CMD_LSIO_GPIO4_IO24                  0x60>,          /* SODIMM 190 */
 761                            <IMX8QXP_USDHC1_DATA0_LSIO_GPIO4_IO25                0x60>,          /* SODIMM 192 */
 762                            <IMX8QXP_USDHC1_DATA1_LSIO_GPIO4_IO26                0x60>,          /* SODIMM  49 */
 763                            <IMX8QXP_USDHC1_DATA2_LSIO_GPIO4_IO27                0x60>,          /* SODIMM  51 */
 764                            <IMX8QXP_USDHC1_DATA3_LSIO_GPIO4_IO28                0x60>,          /* SODIMM  53 */
 765                            <IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT          0x21>;
 766         };
 767
 768         pinctrl_wifi: wifigrp {
 769                 fsl,pins = <IMX8QXP_SCU_BOOT_MODE3_SCU_DSC_RTC_CLOCK_OUTPUT_32K 0x20>;
 770         };
 771 };
 772
 773 /* Delete peripherals which are not present on SOC, but are defined in imx8-ss-*.dtsi */
 774
 775 /delete-node/ &adc1;
 776 /delete-node/ &adc1_lpcg;
 777 /delete-node/ &dsp;
 778 /delete-node/ &dsp_lpcg;