1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2018-2019 NXP
4 * Dong Aisheng <aisheng.dong@nxp.com>
12 model = "Freescale i.MX8QM MEK";
13 compatible = "fsl,imx8qm-mek", "fsl,imx8qm";
16 stdout-path = &lpuart0;
20 /delete-node/ cpu-map;
21 /delete-node/ cpu@100;
22 /delete-node/ cpu@101;
26 /delete-node/ cpu1-thermal;
30 device_type = "memory";
31 reg = <0x00000000 0x80000000 0 0x40000000>;
34 reg_usdhc2_vmmc: usdhc2-vmmc {
35 compatible = "regulator-fixed";
36 regulator-name = "SD1_SPWR";
37 regulator-min-microvolt = <3000000>;
38 regulator-max-microvolt = <3000000>;
39 gpio = <&lsio_gpio4 19 GPIO_ACTIVE_HIGH>;
47 clock-frequency = <100000>;
48 pinctrl-names = "default", "gpio";
49 pinctrl-0 = <&pinctrl_i2c1>;
50 pinctrl-1 = <&pinctrl_i2c1_gpio>;
51 scl-gpios = <&lsio_gpio0 14 GPIO_ACTIVE_HIGH>;
52 sda-gpios = <&lsio_gpio0 15 GPIO_ACTIVE_HIGH>;
57 pinctrl-names = "default";
58 pinctrl-0 = <&pinctrl_lpuart0>;
63 pinctrl-names = "default";
64 pinctrl-0 = <&pinctrl_lpuart2>;
69 pinctrl-names = "default";
70 pinctrl-0 = <&pinctrl_lpuart3>;
75 pinctrl-names = "default";
76 pinctrl-0 = <&pinctrl_fec1>;
77 phy-mode = "rgmii-id";
78 phy-handle = <ðphy0>;
86 ethphy0: ethernet-phy@0 {
87 compatible = "ethernet-phy-ieee802.3-c22";
91 ethphy1: ethernet-phy@1 {
92 compatible = "ethernet-phy-ieee802.3-c22";
99 pinctrl-names = "default";
100 pinctrl-0 = <&pinctrl_usdhc1>;
109 pinctrl-names = "default";
110 pinctrl-0 = <&pinctrl_usdhc2>;
112 vmmc-supply = <®_usdhc2_vmmc>;
113 cd-gpios = <&lsio_gpio5 22 GPIO_ACTIVE_LOW>;
114 wp-gpios = <&lsio_gpio5 21 GPIO_ACTIVE_HIGH>;
119 pinctrl_i2c1: i2c1grp {
121 IMX8QM_GPT0_CLK_DMA_I2C1_SCL 0x0600004c
122 IMX8QM_GPT0_CAPTURE_DMA_I2C1_SDA 0x0600004c
126 pinctrl_i2c1_gpio: i2c1gpio-grp {
128 IMX8QM_GPT0_CLK_LSIO_GPIO0_IO14 0xc600004c
129 IMX8QM_GPT0_CAPTURE_LSIO_GPIO0_IO15 0xc600004c
133 pinctrl_fec1: fec1grp {
135 IMX8QM_ENET0_MDC_CONN_ENET0_MDC 0x06000020
136 IMX8QM_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020
137 IMX8QM_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x06000020
138 IMX8QM_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x06000020
139 IMX8QM_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x06000020
140 IMX8QM_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x06000020
141 IMX8QM_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x06000020
142 IMX8QM_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x06000020
143 IMX8QM_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x06000020
144 IMX8QM_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x06000020
145 IMX8QM_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x06000020
146 IMX8QM_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x06000020
147 IMX8QM_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x06000020
148 IMX8QM_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x06000020
152 pinctrl_lpuart0: lpuart0grp {
154 IMX8QM_UART0_RX_DMA_UART0_RX 0x06000020
155 IMX8QM_UART0_TX_DMA_UART0_TX 0x06000020
159 pinctrl_lpuart2: lpuart2grp {
161 IMX8QM_UART0_RTS_B_DMA_UART2_RX 0x06000020
162 IMX8QM_UART0_CTS_B_DMA_UART2_TX 0x06000020
166 pinctrl_lpuart3: lpuart3grp {
168 IMX8QM_M41_GPIO0_00_DMA_UART3_RX 0x06000020
169 IMX8QM_M41_GPIO0_01_DMA_UART3_TX 0x06000020
173 pinctrl_usdhc1: usdhc1grp {
175 IMX8QM_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041
176 IMX8QM_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021
177 IMX8QM_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021
178 IMX8QM_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021
179 IMX8QM_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021
180 IMX8QM_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021
181 IMX8QM_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021
182 IMX8QM_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021
183 IMX8QM_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021
184 IMX8QM_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021
185 IMX8QM_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041
189 pinctrl_usdhc2: usdhc2grp {
191 IMX8QM_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041
192 IMX8QM_USDHC1_CMD_CONN_USDHC1_CMD 0x00000021
193 IMX8QM_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000021
194 IMX8QM_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000021
195 IMX8QM_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000021
196 IMX8QM_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000021
197 IMX8QM_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021