arch/arm64/boot/dts/freescale/imx8mq.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Copyright 2017 NXP
   4  * Copyright (C) 2017-2018 Pengutronix, Lucas Stach <kernel@pengutronix.de>
   5  */
   6
   7 #include <dt-bindings/clock/imx8mq-clock.h>
   8 #include <dt-bindings/power/imx8mq-power.h>
   9 #include <dt-bindings/reset/imx8mq-reset.h>
  10 #include <dt-bindings/gpio/gpio.h>
  11 #include "dt-bindings/input/input.h"
  12 #include <dt-bindings/interrupt-controller/arm-gic.h>
  13 #include <dt-bindings/thermal/thermal.h>
  14 #include <dt-bindings/interconnect/imx8mq.h>
  15 #include "imx8mq-pinfunc.h"
  16
  17 / {
  18         interrupt-parent = <&gpc>;
  19
  20         #address-cells = <2>;
  21         #size-cells = <2>;
  22
  23         aliases {
  24                 ethernet0 = &fec1;
  25                 gpio0 = &gpio1;
  26                 gpio1 = &gpio2;
  27                 gpio2 = &gpio3;
  28                 gpio3 = &gpio4;
  29                 gpio4 = &gpio5;
  30                 i2c0 = &i2c1;
  31                 i2c1 = &i2c2;
  32                 i2c2 = &i2c3;
  33                 i2c3 = &i2c4;
  34                 mmc0 = &usdhc1;
  35                 mmc1 = &usdhc2;
  36                 serial0 = &uart1;
  37                 serial1 = &uart2;
  38                 serial2 = &uart3;
  39                 serial3 = &uart4;
  40                 spi0 = &ecspi1;
  41                 spi1 = &ecspi2;
  42                 spi2 = &ecspi3;
  43         };
  44
  45         ckil: clock-ckil {
  46                 compatible = "fixed-clock";
  47                 #clock-cells = <0>;
  48                 clock-frequency = <32768>;
  49                 clock-output-names = "ckil";
  50         };
  51
  52         osc_25m: clock-osc-25m {
  53                 compatible = "fixed-clock";
  54                 #clock-cells = <0>;
  55                 clock-frequency = <25000000>;
  56                 clock-output-names = "osc_25m";
  57         };
  58
  59         osc_27m: clock-osc-27m {
  60                 compatible = "fixed-clock";
  61                 #clock-cells = <0>;
  62                 clock-frequency = <27000000>;
  63                 clock-output-names = "osc_27m";
  64         };
  65
  66         clk_ext1: clock-ext1 {
  67                 compatible = "fixed-clock";
  68                 #clock-cells = <0>;
  69                 clock-frequency = <133000000>;
  70                 clock-output-names = "clk_ext1";
  71         };
  72
  73         clk_ext2: clock-ext2 {
  74                 compatible = "fixed-clock";
  75                 #clock-cells = <0>;
  76                 clock-frequency = <133000000>;
  77                 clock-output-names = "clk_ext2";
  78         };
  79
  80         clk_ext3: clock-ext3 {
  81                 compatible = "fixed-clock";
  82                 #clock-cells = <0>;
  83                 clock-frequency = <133000000>;
  84                 clock-output-names = "clk_ext3";
  85         };
  86
  87         clk_ext4: clock-ext4 {
  88                 compatible = "fixed-clock";
  89                 #clock-cells = <0>;
  90                 clock-frequency= <133000000>;
  91                 clock-output-names = "clk_ext4";
  92         };
  93
  94         cpus {
  95                 #address-cells = <1>;
  96                 #size-cells = <0>;
  97
  98                 A53_0: cpu@0 {
  99                         device_type = "cpu";
 100                         compatible = "arm,cortex-a53";
 101                         reg = <0x0>;
 102                         clock-latency = <61036>; /* two CLK32 periods */
 103                         clocks = <&clk IMX8MQ_CLK_ARM>;
 104                         enable-method = "psci";
 105                         next-level-cache = <&A53_L2>;
 106                         operating-points-v2 = <&a53_opp_table>;
 107                         #cooling-cells = <2>;
 108                         nvmem-cells = <&cpu_speed_grade>;
 109                         nvmem-cell-names = "speed_grade";
 110                 };
 111
 112                 A53_1: cpu@1 {
 113                         device_type = "cpu";
 114                         compatible = "arm,cortex-a53";
 115                         reg = <0x1>;
 116                         clock-latency = <61036>; /* two CLK32 periods */
 117                         clocks = <&clk IMX8MQ_CLK_ARM>;
 118                         enable-method = "psci";
 119                         next-level-cache = <&A53_L2>;
 120                         operating-points-v2 = <&a53_opp_table>;
 121                         #cooling-cells = <2>;
 122                 };
 123
 124                 A53_2: cpu@2 {
 125                         device_type = "cpu";
 126                         compatible = "arm,cortex-a53";
 127                         reg = <0x2>;
 128                         clock-latency = <61036>; /* two CLK32 periods */
 129                         clocks = <&clk IMX8MQ_CLK_ARM>;
 130                         enable-method = "psci";
 131                         next-level-cache = <&A53_L2>;
 132                         operating-points-v2 = <&a53_opp_table>;
 133                         #cooling-cells = <2>;
 134                 };
 135
 136                 A53_3: cpu@3 {
 137                         device_type = "cpu";
 138                         compatible = "arm,cortex-a53";
 139                         reg = <0x3>;
 140                         clock-latency = <61036>; /* two CLK32 periods */
 141                         clocks = <&clk IMX8MQ_CLK_ARM>;
 142                         enable-method = "psci";
 143                         next-level-cache = <&A53_L2>;
 144                         operating-points-v2 = <&a53_opp_table>;
 145                         #cooling-cells = <2>;
 146                 };
 147
 148                 A53_L2: l2-cache0 {
 149                         compatible = "cache";
 150                 };
 151         };
 152
 153         a53_opp_table: opp-table {
 154                 compatible = "operating-points-v2";
 155                 opp-shared;
 156
 157                 opp-800000000 {
 158                         opp-hz = /bits/ 64 <800000000>;
 159                         opp-microvolt = <900000>;
 160                         /* Industrial only */
 161                         opp-supported-hw = <0xf>, <0x4>;
 162                         clock-latency-ns = <150000>;
 163                         opp-suspend;
 164                 };
 165
 166                 opp-1000000000 {
 167                         opp-hz = /bits/ 64 <1000000000>;
 168                         opp-microvolt = <900000>;
 169                         /* Consumer only */
 170                         opp-supported-hw = <0xe>, <0x3>;
 171                         clock-latency-ns = <150000>;
 172                         opp-suspend;
 173                 };
 174
 175                 opp-1300000000 {
 176                         opp-hz = /bits/ 64 <1300000000>;
 177                         opp-microvolt = <1000000>;
 178                         opp-supported-hw = <0xc>, <0x4>;
 179                         clock-latency-ns = <150000>;
 180                         opp-suspend;
 181                 };
 182
 183                 opp-1500000000 {
 184                         opp-hz = /bits/ 64 <1500000000>;
 185                         opp-microvolt = <1000000>;
 186                         opp-supported-hw = <0x8>, <0x3>;
 187                         clock-latency-ns = <150000>;
 188                         opp-suspend;
 189                 };
 190         };
 191
 192         pmu {
 193                 compatible = "arm,cortex-a53-pmu";
 194                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
 195                 interrupt-parent = <&gic>;
 196                 interrupt-affinity = <&A53_0>, <&A53_1>, <&A53_2>, <&A53_3>;
 197         };
 198
 199         psci {
 200                 compatible = "arm,psci-1.0";
 201                 method = "smc";
 202         };
 203
 204         thermal-zones {
 205                 cpu_thermal: cpu-thermal {
 206                         polling-delay-passive = <250>;
 207                         polling-delay = <2000>;
 208                         thermal-sensors = <&tmu 0>;
 209
 210                         trips {
 211                                 cpu_alert: cpu-alert {
 212                                         temperature = <80000>;
 213                                         hysteresis = <2000>;
 214                                         type = "passive";
 215                                 };
 216
 217                                 cpu-crit {
 218                                         temperature = <90000>;
 219                                         hysteresis = <2000>;
 220                                         type = "critical";
 221                                 };
 222                         };
 223
 224                         cooling-maps {
 225                                 map0 {
 226                                         trip = <&cpu_alert>;
 227                                         cooling-device =
 228                                                 <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 229                                                 <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 230                                                 <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 231                                                 <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 232                                 };
 233                         };
 234                 };
 235
 236                 gpu-thermal {
 237                         polling-delay-passive = <250>;
 238                         polling-delay = <2000>;
 239                         thermal-sensors = <&tmu 1>;
 240
 241                         trips {
 242                                 gpu_alert: gpu-alert {
 243                                         temperature = <80000>;
 244                                         hysteresis = <2000>;
 245                                         type = "passive";
 246                                 };
 247
 248                                 gpu-crit {
 249                                         temperature = <90000>;
 250                                         hysteresis = <2000>;
 251                                         type = "critical";
 252                                 };
 253                         };
 254
 255                         cooling-maps {
 256                                 map0 {
 257                                         trip = <&gpu_alert>;
 258                                         cooling-device =
 259                                                 <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 260                                 };
 261                         };
 262                 };
 263
 264                 vpu-thermal {
 265                         polling-delay-passive = <250>;
 266                         polling-delay = <2000>;
 267                         thermal-sensors = <&tmu 2>;
 268
 269                         trips {
 270                                 vpu-crit {
 271                                         temperature = <90000>;
 272                                         hysteresis = <2000>;
 273                                         type = "critical";
 274                                 };
 275                         };
 276                 };
 277         };
 278
 279         timer {
 280                 compatible = "arm,armv8-timer";
 281                 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* Physical Secure */
 282                              <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* Physical Non-Secure */
 283                              <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* Virtual */
 284                              <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* Hypervisor */
 285                 interrupt-parent = <&gic>;
 286                 arm,no-tick-in-suspend;
 287         };
 288
 289         soc@0 {
 290                 compatible = "fsl,imx8mq-soc", "simple-bus";
 291                 #address-cells = <1>;
 292                 #size-cells = <1>;
 293                 ranges = <0x0 0x0 0x0 0x3e000000>;
 294                 dma-ranges = <0x40000000 0x0 0x40000000 0xc0000000>;
 295                 nvmem-cells = <&imx8mq_uid>;
 296                 nvmem-cell-names = "soc_unique_id";
 297
 298                 bus@30000000 { /* AIPS1 */
 299                         compatible = "fsl,aips-bus", "simple-bus";
 300                         reg = <0x30000000 0x400000>;
 301                         #address-cells = <1>;
 302                         #size-cells = <1>;
 303                         ranges = <0x30000000 0x30000000 0x400000>;
 304
 305                         sai1: sai@30010000 {
 306                                 #sound-dai-cells = <0>;
 307                                 compatible = "fsl,imx8mq-sai";
 308                                 reg = <0x30010000 0x10000>;
 309                                 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
 310                                 clocks = <&clk IMX8MQ_CLK_SAI1_IPG>,
 311                                          <&clk IMX8MQ_CLK_SAI1_ROOT>,
 312                                          <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>;
 313                                 clock-names = "bus", "mclk1", "mclk2", "mclk3";
 314                                 dmas = <&sdma2 8 24 0>, <&sdma1 9 24 0>;
 315                                 dma-names = "rx", "tx";
 316                                 status = "disabled";
 317                         };
 318
 319                         sai6: sai@30030000 {
 320                                 #sound-dai-cells = <0>;
 321                                 compatible = "fsl,imx8mq-sai";
 322                                 reg = <0x30030000 0x10000>;
 323                                 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
 324                                 clocks = <&clk IMX8MQ_CLK_SAI6_IPG>,
 325                                          <&clk IMX8MQ_CLK_SAI6_ROOT>,
 326                                          <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>;
 327                                 clock-names = "bus", "mclk1", "mclk2", "mclk3";
 328                                 dmas = <&sdma2 4 24 0>, <&sdma2 5 24 0>;
 329                                 dma-names = "rx", "tx";
 330                                 status = "disabled";
 331                         };
 332
 333                         sai5: sai@30040000 {
 334                                 #sound-dai-cells = <0>;
 335                                 compatible = "fsl,imx8mq-sai";
 336                                 reg = <0x30040000 0x10000>;
 337                                 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
 338                                 clocks = <&clk IMX8MQ_CLK_SAI5_IPG>,
 339                                          <&clk IMX8MQ_CLK_SAI5_ROOT>,
 340                                          <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>;
 341                                 clock-names = "bus", "mclk1", "mclk2", "mclk3";
 342                                 dmas = <&sdma2 2 24 0>, <&sdma2 3 24 0>;
 343                                 dma-names = "rx", "tx";
 344                                 status = "disabled";
 345                         };
 346
 347                         sai4: sai@30050000 {
 348                                 #sound-dai-cells = <0>;
 349                                 compatible = "fsl,imx8mq-sai";
 350                                 reg = <0x30050000 0x10000>;
 351                                 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
 352                                 clocks = <&clk IMX8MQ_CLK_SAI4_IPG>,
 353                                          <&clk IMX8MQ_CLK_SAI4_ROOT>,
 354                                          <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>;
 355                                 clock-names = "bus", "mclk1", "mclk2", "mclk3";
 356                                 dmas = <&sdma2 0 24 0>, <&sdma2 1 24 0>;
 357                                 dma-names = "rx", "tx";
 358                                 status = "disabled";
 359                         };
 360
 361                         gpio1: gpio@30200000 {
 362                                 compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
 363                                 reg = <0x30200000 0x10000>;
 364                                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
 365                                              <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 366                                 clocks = <&clk IMX8MQ_CLK_GPIO1_ROOT>;
 367                                 gpio-controller;
 368                                 #gpio-cells = <2>;
 369                                 interrupt-controller;
 370                                 #interrupt-cells = <2>;
 371                                 gpio-ranges = <&iomuxc 0 10 30>;
 372                         };
 373
 374                         gpio2: gpio@30210000 {
 375                                 compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
 376                                 reg = <0x30210000 0x10000>;
 377                                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
 378                                              <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
 379                                 clocks = <&clk IMX8MQ_CLK_GPIO2_ROOT>;
 380                                 gpio-controller;
 381                                 #gpio-cells = <2>;
 382                                 interrupt-controller;
 383                                 #interrupt-cells = <2>;
 384                                 gpio-ranges = <&iomuxc 0 40 21>;
 385                         };
 386
 387                         gpio3: gpio@30220000 {
 388                                 compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
 389                                 reg = <0x30220000 0x10000>;
 390                                 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
 391                                              <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
 392                                 clocks = <&clk IMX8MQ_CLK_GPIO3_ROOT>;
 393                                 gpio-controller;
 394                                 #gpio-cells = <2>;
 395                                 interrupt-controller;
 396                                 #interrupt-cells = <2>;
 397                                 gpio-ranges = <&iomuxc 0 61 26>;
 398                         };
 399
 400                         gpio4: gpio@30230000 {
 401                                 compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
 402                                 reg = <0x30230000 0x10000>;
 403                                 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
 404                                              <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 405                                 clocks = <&clk IMX8MQ_CLK_GPIO4_ROOT>;
 406                                 gpio-controller;
 407                                 #gpio-cells = <2>;
 408                                 interrupt-controller;
 409                                 #interrupt-cells = <2>;
 410                                 gpio-ranges = <&iomuxc 0 87 32>;
 411                         };
 412
 413                         gpio5: gpio@30240000 {
 414                                 compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
 415                                 reg = <0x30240000 0x10000>;
 416                                 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
 417                                              <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 418                                 clocks = <&clk IMX8MQ_CLK_GPIO5_ROOT>;
 419                                 gpio-controller;
 420                                 #gpio-cells = <2>;
 421                                 interrupt-controller;
 422                                 #interrupt-cells = <2>;
 423                                 gpio-ranges = <&iomuxc 0 119 30>;
 424                         };
 425
 426                         tmu: tmu@30260000 {
 427                                 compatible = "fsl,imx8mq-tmu";
 428                                 reg = <0x30260000 0x10000>;
 429                                 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
 430                                 clocks = <&clk IMX8MQ_CLK_TMU_ROOT>;
 431                                 little-endian;
 432                                 fsl,tmu-range = <0xb0000 0xa0026 0x80048 0x70061>;
 433                                 fsl,tmu-calibration = <0x00000000 0x00000023
 434                                                        0x00000001 0x00000029
 435                                                        0x00000002 0x0000002f
 436                                                        0x00000003 0x00000035
 437                                                        0x00000004 0x0000003d
 438                                                        0x00000005 0x00000043
 439                                                        0x00000006 0x0000004b
 440                                                        0x00000007 0x00000051
 441                                                        0x00000008 0x00000057
 442                                                        0x00000009 0x0000005f
 443                                                        0x0000000a 0x00000067
 444                                                        0x0000000b 0x0000006f
 445
 446                                                        0x00010000 0x0000001b
 447                                                        0x00010001 0x00000023
 448                                                        0x00010002 0x0000002b
 449                                                        0x00010003 0x00000033
 450                                                        0x00010004 0x0000003b
 451                                                        0x00010005 0x00000043
 452                                                        0x00010006 0x0000004b
 453                                                        0x00010007 0x00000055
 454                                                        0x00010008 0x0000005d
 455                                                        0x00010009 0x00000067
 456                                                        0x0001000a 0x00000070
 457
 458                                                        0x00020000 0x00000017
 459                                                        0x00020001 0x00000023
 460                                                        0x00020002 0x0000002d
 461                                                        0x00020003 0x00000037
 462                                                        0x00020004 0x00000041
 463                                                        0x00020005 0x0000004b
 464                                                        0x00020006 0x00000057
 465                                                        0x00020007 0x00000063
 466                                                        0x00020008 0x0000006f
 467
 468                                                        0x00030000 0x00000015
 469                                                        0x00030001 0x00000021
 470                                                        0x00030002 0x0000002d
 471                                                        0x00030003 0x00000039
 472                                                        0x00030004 0x00000045
 473                                                        0x00030005 0x00000053
 474                                                        0x00030006 0x0000005f
 475                                                        0x00030007 0x00000071>;
 476                                 #thermal-sensor-cells =  <1>;
 477                         };
 478
 479                         wdog1: watchdog@30280000 {
 480                                 compatible = "fsl,imx8mq-wdt", "fsl,imx21-wdt";
 481                                 reg = <0x30280000 0x10000>;
 482                                 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
 483                                 clocks = <&clk IMX8MQ_CLK_WDOG1_ROOT>;
 484                                 status = "disabled";
 485                         };
 486
 487                         wdog2: watchdog@30290000 {
 488                                 compatible = "fsl,imx8mq-wdt", "fsl,imx21-wdt";
 489                                 reg = <0x30290000 0x10000>;
 490                                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 491                                 clocks = <&clk IMX8MQ_CLK_WDOG2_ROOT>;
 492                                 status = "disabled";
 493                         };
 494
 495                         wdog3: watchdog@302a0000 {
 496                                 compatible = "fsl,imx8mq-wdt", "fsl,imx21-wdt";
 497                                 reg = <0x302a0000 0x10000>;
 498                                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 499                                 clocks = <&clk IMX8MQ_CLK_WDOG3_ROOT>;
 500                                 status = "disabled";
 501                         };
 502
 503                         sdma2: sdma@302c0000 {
 504                                 compatible = "fsl,imx8mq-sdma","fsl,imx7d-sdma";
 505                                 reg = <0x302c0000 0x10000>;
 506                                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 507                                 clocks = <&clk IMX8MQ_CLK_SDMA2_ROOT>,
 508                                          <&clk IMX8MQ_CLK_SDMA2_ROOT>;
 509                                 clock-names = "ipg", "ahb";
 510                                 #dma-cells = <3>;
 511                                 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
 512                         };
 513
 514                         lcdif: lcd-controller@30320000 {
 515                                 compatible = "fsl,imx8mq-lcdif", "fsl,imx28-lcdif";
 516                                 reg = <0x30320000 0x10000>;
 517                                 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
 518                                 clocks = <&clk IMX8MQ_CLK_LCDIF_PIXEL>;
 519                                 clock-names = "pix";
 520                                 assigned-clocks = <&clk IMX8MQ_VIDEO_PLL1_REF_SEL>,
 521                                                   <&clk IMX8MQ_VIDEO_PLL1_BYPASS>,
 522                                                   <&clk IMX8MQ_CLK_LCDIF_PIXEL>,
 523                                                   <&clk IMX8MQ_VIDEO_PLL1>;
 524                                 assigned-clock-parents = <&clk IMX8MQ_CLK_25M>,
 525                                                   <&clk IMX8MQ_VIDEO_PLL1>,
 526                                                   <&clk IMX8MQ_VIDEO_PLL1_OUT>;
 527                                 assigned-clock-rates = <0>, <0>, <0>, <594000000>;
 528                                 interconnects = <&noc IMX8MQ_ICM_LCDIF &noc IMX8MQ_ICS_DRAM>;
 529                                 interconnect-names = "dram";
 530                                 status = "disabled";
 531
 532                                 port@0 {
 533                                         lcdif_mipi_dsi: endpoint {
 534                                                 remote-endpoint = <&mipi_dsi_lcdif_in>;
 535                                         };
 536                                 };
 537                         };
 538
 539                         iomuxc: pinctrl@30330000 {
 540                                 compatible = "fsl,imx8mq-iomuxc";
 541                                 reg = <0x30330000 0x10000>;
 542                         };
 543
 544                         iomuxc_gpr: syscon@30340000 {
 545                                 compatible = "fsl,imx8mq-iomuxc-gpr", "fsl,imx6q-iomuxc-gpr",
 546                                              "syscon", "simple-mfd";
 547                                 reg = <0x30340000 0x10000>;
 548
 549                                 mux: mux-controller {
 550                                         compatible = "mmio-mux";
 551                                         #mux-control-cells = <1>;
 552                                         mux-reg-masks = <0x34 0x00000004>; /* MIPI_MUX_SEL */
 553                                 };
 554                         };
 555
 556                         ocotp: efuse@30350000 {
 557                                 compatible = "fsl,imx8mq-ocotp", "syscon";
 558                                 reg = <0x30350000 0x10000>;
 559                                 clocks = <&clk IMX8MQ_CLK_OCOTP_ROOT>;
 560                                 #address-cells = <1>;
 561                                 #size-cells = <1>;
 562
 563                                 imx8mq_uid: soc-uid@410 {
 564                                         reg = <0x4 0x8>;
 565                                 };
 566
 567                                 cpu_speed_grade: speed-grade@10 {
 568                                         reg = <0x10 4>;
 569                                 };
 570
 571                                 fec_mac_address: mac-address@90 {
 572                                         reg = <0x90 6>;
 573                                 };
 574                         };
 575
 576                         anatop: syscon@30360000 {
 577                                 compatible = "fsl,imx8mq-anatop", "syscon";
 578                                 reg = <0x30360000 0x10000>;
 579                                 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
 580                         };
 581
 582                         snvs: snvs@30370000 {
 583                                 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
 584                                 reg = <0x30370000 0x10000>;
 585
 586                                 snvs_rtc: snvs-rtc-lp{
 587                                         compatible = "fsl,sec-v4.0-mon-rtc-lp";
 588                                         regmap =<&snvs>;
 589                                         offset = <0x34>;
 590                                         interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
 591                                                 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 592                                         clocks = <&clk IMX8MQ_CLK_SNVS_ROOT>;
 593                                         clock-names = "snvs-rtc";
 594                                 };
 595
 596                                 snvs_pwrkey: snvs-powerkey {
 597                                         compatible = "fsl,sec-v4.0-pwrkey";
 598                                         regmap = <&snvs>;
 599                                         interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 600                                         clocks = <&clk IMX8MQ_CLK_SNVS_ROOT>;
 601                                         clock-names = "snvs-pwrkey";
 602                                         linux,keycode = <KEY_POWER>;
 603                                         wakeup-source;
 604                                         status = "disabled";
 605                                 };
 606                         };
 607
 608                         clk: clock-controller@30380000 {
 609                                 compatible = "fsl,imx8mq-ccm";
 610                                 reg = <0x30380000 0x10000>;
 611                                 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
 612                                              <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 613                                 #clock-cells = <1>;
 614                                 clocks = <&ckil>, <&osc_25m>, <&osc_27m>,
 615                                          <&clk_ext1>, <&clk_ext2>,
 616                                          <&clk_ext3>, <&clk_ext4>;
 617                                 clock-names = "ckil", "osc_25m", "osc_27m",
 618                                               "clk_ext1", "clk_ext2",
 619                                               "clk_ext3", "clk_ext4";
 620                                 assigned-clocks = <&clk IMX8MQ_CLK_A53_SRC>,
 621                                                   <&clk IMX8MQ_CLK_A53_CORE>,
 622                                                   <&clk IMX8MQ_CLK_NOC>,
 623                                                   <&clk IMX8MQ_CLK_AUDIO_AHB>,
 624                                                   <&clk IMX8MQ_AUDIO_PLL1_BYPASS>,
 625                                                   <&clk IMX8MQ_AUDIO_PLL2_BYPASS>,
 626                                                   <&clk IMX8MQ_AUDIO_PLL1>,
 627                                                   <&clk IMX8MQ_AUDIO_PLL2>;
 628                                 assigned-clock-rates = <0>, <0>,
 629                                                        <800000000>,
 630                                                        <0>,
 631                                                        <0>,
 632                                                        <0>,
 633                                                        <786432000>,
 634                                                        <722534400>;
 635                                 assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_800M>,
 636                                                          <&clk IMX8MQ_ARM_PLL_OUT>,
 637                                                          <0>,
 638                                                          <&clk IMX8MQ_SYS2_PLL_500M>,
 639                                                          <&clk IMX8MQ_AUDIO_PLL1>,
 640                                                          <&clk IMX8MQ_AUDIO_PLL2>;
 641                         };
 642
 643                         src: reset-controller@30390000 {
 644                                 compatible = "fsl,imx8mq-src", "syscon";
 645                                 reg = <0x30390000 0x10000>;
 646                                 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
 647                                 #reset-cells = <1>;
 648                         };
 649
 650                         gpc: gpc@303a0000 {
 651                                 compatible = "fsl,imx8mq-gpc";
 652                                 reg = <0x303a0000 0x10000>;
 653                                 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
 654                                 interrupt-parent = <&gic>;
 655                                 interrupt-controller;
 656                                 #interrupt-cells = <3>;
 657
 658                                 pgc {
 659                                         #address-cells = <1>;
 660                                         #size-cells = <0>;
 661
 662                                         pgc_mipi: power-domain@0 {
 663                                                 #power-domain-cells = <0>;
 664                                                 reg = <IMX8M_POWER_DOMAIN_MIPI>;
 665                                         };
 666
 667                                         /*
 668                                          * As per comment in ATF source code:
 669                                          *
 670                                          * PCIE1 and PCIE2 share the
 671                                          * same reset signal, if we
 672                                          * power down PCIE2, PCIE1
 673                                          * will be held in reset too.
 674                                          *
 675                                          * So instead of creating two
 676                                          * separate power domains for
 677                                          * PCIE1 and PCIE2 we create a
 678                                          * link between both and use
 679                                          * it as a shared PCIE power
 680                                          * domain.
 681                                          */
 682                                         pgc_pcie: power-domain@1 {
 683                                                 #power-domain-cells = <0>;
 684                                                 reg = <IMX8M_POWER_DOMAIN_PCIE1>;
 685                                                 power-domains = <&pgc_pcie2>;
 686                                         };
 687
 688                                         pgc_otg1: power-domain@2 {
 689                                                 #power-domain-cells = <0>;
 690                                                 reg = <IMX8M_POWER_DOMAIN_USB_OTG1>;
 691                                         };
 692
 693                                         pgc_otg2: power-domain@3 {
 694                                                 #power-domain-cells = <0>;
 695                                                 reg = <IMX8M_POWER_DOMAIN_USB_OTG2>;
 696                                         };
 697
 698                                         pgc_ddr1: power-domain@4 {
 699                                                 #power-domain-cells = <0>;
 700                                                 reg = <IMX8M_POWER_DOMAIN_DDR1>;
 701                                         };
 702
 703                                         pgc_gpu: power-domain@5 {
 704                                                 #power-domain-cells = <0>;
 705                                                 reg = <IMX8M_POWER_DOMAIN_GPU>;
 706                                                 clocks = <&clk IMX8MQ_CLK_GPU_ROOT>,
 707                                                          <&clk IMX8MQ_CLK_GPU_SHADER_DIV>,
 708                                                          <&clk IMX8MQ_CLK_GPU_AXI>,
 709                                                          <&clk IMX8MQ_CLK_GPU_AHB>;
 710                                         };
 711
 712                                         pgc_vpu: power-domain@6 {
 713                                                 #power-domain-cells = <0>;
 714                                                 reg = <IMX8M_POWER_DOMAIN_VPU>;
 715                                                 clocks = <&clk IMX8MQ_CLK_VPU_DEC_ROOT>;
 716                                         };
 717
 718                                         pgc_disp: power-domain@7 {
 719                                                 #power-domain-cells = <0>;
 720                                                 reg = <IMX8M_POWER_DOMAIN_DISP>;
 721                                         };
 722
 723                                         pgc_mipi_csi1: power-domain@8 {
 724                                                 #power-domain-cells = <0>;
 725                                                 reg = <IMX8M_POWER_DOMAIN_MIPI_CSI1>;
 726                                         };
 727
 728                                         pgc_mipi_csi2: power-domain@9 {
 729                                                 #power-domain-cells = <0>;
 730                                                 reg = <IMX8M_POWER_DOMAIN_MIPI_CSI2>;
 731                                         };
 732
 733                                         pgc_pcie2: power-domain@a {
 734                                                 #power-domain-cells = <0>;
 735                                                 reg = <IMX8M_POWER_DOMAIN_PCIE2>;
 736                                         };
 737                                 };
 738                         };
 739                 };
 740
 741                 bus@30400000 { /* AIPS2 */
 742                         compatible = "fsl,aips-bus", "simple-bus";
 743                         reg = <0x30400000 0x400000>;
 744                         #address-cells = <1>;
 745                         #size-cells = <1>;
 746                         ranges = <0x30400000 0x30400000 0x400000>;
 747
 748                         pwm1: pwm@30660000 {
 749                                 compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm";
 750                                 reg = <0x30660000 0x10000>;
 751                                 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
 752                                 clocks = <&clk IMX8MQ_CLK_PWM1_ROOT>,
 753                                          <&clk IMX8MQ_CLK_PWM1_ROOT>;
 754                                 clock-names = "ipg", "per";
 755                                 #pwm-cells = <2>;
 756                                 status = "disabled";
 757                         };
 758
 759                         pwm2: pwm@30670000 {
 760                                 compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm";
 761                                 reg = <0x30670000 0x10000>;
 762                                 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 763                                 clocks = <&clk IMX8MQ_CLK_PWM2_ROOT>,
 764                                          <&clk IMX8MQ_CLK_PWM2_ROOT>;
 765                                 clock-names = "ipg", "per";
 766                                 #pwm-cells = <2>;
 767                                 status = "disabled";
 768                         };
 769
 770                         pwm3: pwm@30680000 {
 771                                 compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm";
 772                                 reg = <0x30680000 0x10000>;
 773                                 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 774                                 clocks = <&clk IMX8MQ_CLK_PWM3_ROOT>,
 775                                          <&clk IMX8MQ_CLK_PWM3_ROOT>;
 776                                 clock-names = "ipg", "per";
 777                                 #pwm-cells = <2>;
 778                                 status = "disabled";
 779                         };
 780
 781                         pwm4: pwm@30690000 {
 782                                 compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm";
 783                                 reg = <0x30690000 0x10000>;
 784                                 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 785                                 clocks = <&clk IMX8MQ_CLK_PWM4_ROOT>,
 786                                          <&clk IMX8MQ_CLK_PWM4_ROOT>;
 787                                 clock-names = "ipg", "per";
 788                                 #pwm-cells = <2>;
 789                                 status = "disabled";
 790                         };
 791
 792                         system_counter: timer@306a0000 {
 793                                 compatible = "nxp,sysctr-timer";
 794                                 reg = <0x306a0000 0x20000>;
 795                                 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
 796                                 clocks = <&osc_25m>;
 797                                 clock-names = "per";
 798                         };
 799                 };
 800
 801                 bus@30800000 { /* AIPS3 */
 802                         compatible = "fsl,aips-bus", "simple-bus";
 803                         reg = <0x30800000 0x400000>;
 804                         #address-cells = <1>;
 805                         #size-cells = <1>;
 806                         ranges = <0x30800000 0x30800000 0x400000>,
 807                                  <0x08000000 0x08000000 0x10000000>;
 808
 809                         spdif1: spdif@30810000 {
 810                                 compatible = "fsl,imx35-spdif";
 811                                 reg = <0x30810000 0x10000>;
 812                                 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
 813                                 clocks = <&clk IMX8MQ_CLK_IPG_ROOT>, /* core */
 814                                         <&clk IMX8MQ_CLK_25M>, /* rxtx0 */
 815                                         <&clk IMX8MQ_CLK_SPDIF1>, /* rxtx1 */
 816                                         <&clk IMX8MQ_CLK_DUMMY>, /* rxtx2 */
 817                                         <&clk IMX8MQ_CLK_DUMMY>, /* rxtx3 */
 818                                         <&clk IMX8MQ_CLK_DUMMY>, /* rxtx4 */
 819                                         <&clk IMX8MQ_CLK_IPG_ROOT>, /* rxtx5 */
 820                                         <&clk IMX8MQ_CLK_DUMMY>, /* rxtx6 */
 821                                         <&clk IMX8MQ_CLK_DUMMY>, /* rxtx7 */
 822                                         <&clk IMX8MQ_CLK_DUMMY>; /* spba */
 823                                 clock-names = "core", "rxtx0",
 824                                               "rxtx1", "rxtx2",
 825                                               "rxtx3", "rxtx4",
 826                                               "rxtx5", "rxtx6",
 827                                               "rxtx7", "spba";
 828                                 dmas = <&sdma1 8 18 0>, <&sdma1 9 18 0>;
 829                                 dma-names = "rx", "tx";
 830                                 status = "disabled";
 831                         };
 832
 833                         ecspi1: spi@30820000 {
 834                                 #address-cells = <1>;
 835                                 #size-cells = <0>;
 836                                 compatible = "fsl,imx8mq-ecspi", "fsl,imx51-ecspi";
 837                                 reg = <0x30820000 0x10000>;
 838                                 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 839                                 clocks = <&clk IMX8MQ_CLK_ECSPI1_ROOT>,
 840                                          <&clk IMX8MQ_CLK_ECSPI1_ROOT>;
 841                                 clock-names = "ipg", "per";
 842                                 dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>;
 843                                 dma-names = "rx", "tx";
 844                                 status = "disabled";
 845                         };
 846
 847                         ecspi2: spi@30830000 {
 848                                 #address-cells = <1>;
 849                                 #size-cells = <0>;
 850                                 compatible = "fsl,imx8mq-ecspi", "fsl,imx51-ecspi";
 851                                 reg = <0x30830000 0x10000>;
 852                                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 853                                 clocks = <&clk IMX8MQ_CLK_ECSPI2_ROOT>,
 854                                          <&clk IMX8MQ_CLK_ECSPI2_ROOT>;
 855                                 clock-names = "ipg", "per";
 856                                 dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>;
 857                                 dma-names = "rx", "tx";
 858                                 status = "disabled";
 859                         };
 860
 861                         ecspi3: spi@30840000 {
 862                                 #address-cells = <1>;
 863                                 #size-cells = <0>;
 864                                 compatible = "fsl,imx8mq-ecspi", "fsl,imx51-ecspi";
 865                                 reg = <0x30840000 0x10000>;
 866                                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 867                                 clocks = <&clk IMX8MQ_CLK_ECSPI3_ROOT>,
 868                                          <&clk IMX8MQ_CLK_ECSPI3_ROOT>;
 869                                 clock-names = "ipg", "per";
 870                                 dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>;
 871                                 dma-names = "rx", "tx";
 872                                 status = "disabled";
 873                         };
 874
 875                         uart1: serial@30860000 {
 876                                 compatible = "fsl,imx8mq-uart",
 877                                              "fsl,imx6q-uart";
 878                                 reg = <0x30860000 0x10000>;
 879                                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 880                                 clocks = <&clk IMX8MQ_CLK_UART1_ROOT>,
 881                                          <&clk IMX8MQ_CLK_UART1_ROOT>;
 882                                 clock-names = "ipg", "per";
 883                                 status = "disabled";
 884                         };
 885
 886                         uart3: serial@30880000 {
 887                                 compatible = "fsl,imx8mq-uart",
 888                                              "fsl,imx6q-uart";
 889                                 reg = <0x30880000 0x10000>;
 890                                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 891                                 clocks = <&clk IMX8MQ_CLK_UART3_ROOT>,
 892                                          <&clk IMX8MQ_CLK_UART3_ROOT>;
 893                                 clock-names = "ipg", "per";
 894                                 status = "disabled";
 895                         };
 896
 897                         uart2: serial@30890000 {
 898                                 compatible = "fsl,imx8mq-uart",
 899                                              "fsl,imx6q-uart";
 900                                 reg = <0x30890000 0x10000>;
 901                                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 902                                 clocks = <&clk IMX8MQ_CLK_UART2_ROOT>,
 903                                          <&clk IMX8MQ_CLK_UART2_ROOT>;
 904                                 clock-names = "ipg", "per";
 905                                 status = "disabled";
 906                         };
 907
 908                         spdif2: spdif@308a0000 {
 909                                 compatible = "fsl,imx35-spdif";
 910                                 reg = <0x308a0000 0x10000>;
 911                                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 912                                 clocks = <&clk IMX8MQ_CLK_IPG_ROOT>, /* core */
 913                                         <&clk IMX8MQ_CLK_25M>, /* rxtx0 */
 914                                         <&clk IMX8MQ_CLK_SPDIF2>, /* rxtx1 */
 915                                         <&clk IMX8MQ_CLK_DUMMY>, /* rxtx2 */
 916                                         <&clk IMX8MQ_CLK_DUMMY>, /* rxtx3 */
 917                                         <&clk IMX8MQ_CLK_DUMMY>, /* rxtx4 */
 918                                         <&clk IMX8MQ_CLK_IPG_ROOT>, /* rxtx5 */
 919                                         <&clk IMX8MQ_CLK_DUMMY>, /* rxtx6 */
 920                                         <&clk IMX8MQ_CLK_DUMMY>, /* rxtx7 */
 921                                         <&clk IMX8MQ_CLK_DUMMY>; /* spba */
 922                                 clock-names = "core", "rxtx0",
 923                                               "rxtx1", "rxtx2",
 924                                               "rxtx3", "rxtx4",
 925                                               "rxtx5", "rxtx6",
 926                                               "rxtx7", "spba";
 927                                 dmas = <&sdma1 16 18 0>, <&sdma1 17 18 0>;
 928                                 dma-names = "rx", "tx";
 929                                 status = "disabled";
 930                         };
 931
 932                         sai2: sai@308b0000 {
 933                                 #sound-dai-cells = <0>;
 934                                 compatible = "fsl,imx8mq-sai";
 935                                 reg = <0x308b0000 0x10000>;
 936                                 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 937                                 clocks = <&clk IMX8MQ_CLK_SAI2_IPG>,
 938                                          <&clk IMX8MQ_CLK_SAI2_ROOT>,
 939                                          <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>;
 940                                 clock-names = "bus", "mclk1", "mclk2", "mclk3";
 941                                 dmas = <&sdma1 10 24 0>, <&sdma1 11 24 0>;
 942                                 dma-names = "rx", "tx";
 943                                 status = "disabled";
 944                         };
 945
 946                         sai3: sai@308c0000 {
 947                                 #sound-dai-cells = <0>;
 948                                 compatible = "fsl,imx8mq-sai";
 949                                 reg = <0x308c0000 0x10000>;
 950                                 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
 951                                 clocks = <&clk IMX8MQ_CLK_SAI3_IPG>,
 952                                          <&clk IMX8MQ_CLK_SAI3_ROOT>,
 953                                          <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>;
 954                                 clock-names = "bus", "mclk1", "mclk2", "mclk3";
 955                                 dmas = <&sdma1 12 24 0>, <&sdma1 13 24 0>;
 956                                 dma-names = "rx", "tx";
 957                                 status = "disabled";
 958                         };
 959
 960                         crypto: crypto@30900000 {
 961                                 compatible = "fsl,sec-v4.0";
 962                                 #address-cells = <1>;
 963                                 #size-cells = <1>;
 964                                 reg = <0x30900000 0x40000>;
 965                                 ranges = <0 0x30900000 0x40000>;
 966                                 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
 967                                 clocks = <&clk IMX8MQ_CLK_AHB>,
 968                                          <&clk IMX8MQ_CLK_IPG_ROOT>;
 969                                 clock-names = "aclk", "ipg";
 970
 971                                 sec_jr0: jr@1000 {
 972                                         compatible = "fsl,sec-v4.0-job-ring";
 973                                         reg = <0x1000 0x1000>;
 974                                         interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
 975                                 };
 976
 977                                 sec_jr1: jr@2000 {
 978                                         compatible = "fsl,sec-v4.0-job-ring";
 979                                         reg = <0x2000 0x1000>;
 980                                         interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
 981                                 };
 982
 983                                 sec_jr2: jr@3000 {
 984                                         compatible = "fsl,sec-v4.0-job-ring";
 985                                         reg = <0x3000 0x1000>;
 986                                         interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
 987                                 };
 988                         };
 989
 990                         mipi_dsi: mipi-dsi@30a00000 {
 991                                 compatible = "fsl,imx8mq-nwl-dsi";
 992                                 reg = <0x30a00000 0x300>;
 993                                 clocks = <&clk IMX8MQ_CLK_DSI_CORE>,
 994                                          <&clk IMX8MQ_CLK_DSI_AHB>,
 995                                          <&clk IMX8MQ_CLK_DSI_IPG_DIV>,
 996                                          <&clk IMX8MQ_CLK_DSI_PHY_REF>,
 997                                          <&clk IMX8MQ_CLK_LCDIF_PIXEL>;
 998                                 clock-names = "core", "rx_esc", "tx_esc", "phy_ref", "lcdif";
 999                                 assigned-clocks = <&clk IMX8MQ_CLK_DSI_AHB>,
1000                                                   <&clk IMX8MQ_CLK_DSI_CORE>,
1001                                                   <&clk IMX8MQ_CLK_DSI_IPG_DIV>;
1002                                 assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>,
1003                                                          <&clk IMX8MQ_SYS1_PLL_266M>;
1004                                 assigned-clock-rates = <80000000>, <266000000>, <20000000>;
1005                                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
1006                                 mux-controls = <&mux 0>;
1007                                 power-domains = <&pgc_mipi>;
1008                                 phys = <&dphy>;
1009                                 phy-names = "dphy";
1010                                 resets = <&src IMX8MQ_RESET_MIPI_DSI_RESET_BYTE_N>,
1011                                          <&src IMX8MQ_RESET_MIPI_DSI_DPI_RESET_N>,
1012                                          <&src IMX8MQ_RESET_MIPI_DSI_ESC_RESET_N>,
1013                                          <&src IMX8MQ_RESET_MIPI_DSI_PCLK_RESET_N>;
1014                                 reset-names = "byte", "dpi", "esc", "pclk";
1015                                 status = "disabled";
1016
1017                                 ports {
1018                                         #address-cells = <1>;
1019                                         #size-cells = <0>;
1020
1021                                         port@0 {
1022                                                 reg = <0>;
1023                                                 #address-cells = <1>;
1024                                                 #size-cells = <0>;
1025                                                 mipi_dsi_lcdif_in: endpoint@0 {
1026                                                         reg = <0>;
1027                                                         remote-endpoint = <&lcdif_mipi_dsi>;
1028                                                 };
1029                                         };
1030                                 };
1031                         };
1032
1033                         dphy: dphy@30a00300 {
1034                                 compatible = "fsl,imx8mq-mipi-dphy";
1035                                 reg = <0x30a00300 0x100>;
1036                                 clocks = <&clk IMX8MQ_CLK_DSI_PHY_REF>;
1037                                 clock-names = "phy_ref";
1038                                 assigned-clocks = <&clk IMX8MQ_VIDEO_PLL1_REF_SEL>,
1039                                                   <&clk IMX8MQ_VIDEO_PLL1_BYPASS>,
1040                                                   <&clk IMX8MQ_CLK_DSI_PHY_REF>,
1041                                                   <&clk IMX8MQ_VIDEO_PLL1>;
1042                                 assigned-clock-parents = <&clk IMX8MQ_CLK_25M>,
1043                                                   <&clk IMX8MQ_VIDEO_PLL1>,
1044                                                   <&clk IMX8MQ_VIDEO_PLL1_OUT>;
1045                                 assigned-clock-rates = <0>, <0>, <24000000>, <594000000>;
1046                                 #phy-cells = <0>;
1047                                 power-domains = <&pgc_mipi>;
1048                                 status = "disabled";
1049                         };
1050
1051                         i2c1: i2c@30a20000 {
1052                                 compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c";
1053                                 reg = <0x30a20000 0x10000>;
1054                                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
1055                                 clocks = <&clk IMX8MQ_CLK_I2C1_ROOT>;
1056                                 #address-cells = <1>;
1057                                 #size-cells = <0>;
1058                                 status = "disabled";
1059                         };
1060
1061                         i2c2: i2c@30a30000 {
1062                                 compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c";
1063                                 reg = <0x30a30000 0x10000>;
1064                                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
1065                                 clocks = <&clk IMX8MQ_CLK_I2C2_ROOT>;
1066                                 #address-cells = <1>;
1067                                 #size-cells = <0>;
1068                                 status = "disabled";
1069                         };
1070
1071                         i2c3: i2c@30a40000 {
1072                                 compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c";
1073                                 reg = <0x30a40000 0x10000>;
1074                                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
1075                                 clocks = <&clk IMX8MQ_CLK_I2C3_ROOT>;
1076                                 #address-cells = <1>;
1077                                 #size-cells = <0>;
1078                                 status = "disabled";
1079                         };
1080
1081                         i2c4: i2c@30a50000 {
1082                                 compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c";
1083                                 reg = <0x30a50000 0x10000>;
1084                                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
1085                                 clocks = <&clk IMX8MQ_CLK_I2C4_ROOT>;
1086                                 #address-cells = <1>;
1087                                 #size-cells = <0>;
1088                                 status = "disabled";
1089                         };
1090
1091                         uart4: serial@30a60000 {
1092                                 compatible = "fsl,imx8mq-uart",
1093                                              "fsl,imx6q-uart";
1094                                 reg = <0x30a60000 0x10000>;
1095                                 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
1096                                 clocks = <&clk IMX8MQ_CLK_UART4_ROOT>,
1097                                          <&clk IMX8MQ_CLK_UART4_ROOT>;
1098                                 clock-names = "ipg", "per";
1099                                 status = "disabled";
1100                         };
1101
1102                         mu: mailbox@30aa0000 {
1103                                 compatible = "fsl,imx8mq-mu", "fsl,imx6sx-mu";
1104                                 reg = <0x30aa0000 0x10000>;
1105                                 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
1106                                 clocks = <&clk IMX8MQ_CLK_MU_ROOT>;
1107                                 #mbox-cells = <2>;
1108                         };
1109
1110                         usdhc1: mmc@30b40000 {
1111                                 compatible = "fsl,imx8mq-usdhc",
1112                                              "fsl,imx7d-usdhc";
1113                                 reg = <0x30b40000 0x10000>;
1114                                 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
1115                                 clocks = <&clk IMX8MQ_CLK_IPG_ROOT>,
1116                                          <&clk IMX8MQ_CLK_NAND_USDHC_BUS>,
1117                                          <&clk IMX8MQ_CLK_USDHC1_ROOT>;
1118                                 clock-names = "ipg", "ahb", "per";
1119                                 fsl,tuning-start-tap = <20>;
1120                                 fsl,tuning-step = <2>;
1121                                 bus-width = <4>;
1122                                 status = "disabled";
1123                         };
1124
1125                         usdhc2: mmc@30b50000 {
1126                                 compatible = "fsl,imx8mq-usdhc",
1127                                              "fsl,imx7d-usdhc";
1128                                 reg = <0x30b50000 0x10000>;
1129                                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
1130                                 clocks = <&clk IMX8MQ_CLK_IPG_ROOT>,
1131                                          <&clk IMX8MQ_CLK_NAND_USDHC_BUS>,
1132                                          <&clk IMX8MQ_CLK_USDHC2_ROOT>;
1133                                 clock-names = "ipg", "ahb", "per";
1134                                 fsl,tuning-start-tap = <20>;
1135                                 fsl,tuning-step = <2>;
1136                                 bus-width = <4>;
1137                                 status = "disabled";
1138                         };
1139
1140                         qspi0: spi@30bb0000 {
1141                                 #address-cells = <1>;
1142                                 #size-cells = <0>;
1143                                 compatible = "fsl,imx8mq-qspi", "fsl,imx7d-qspi";
1144                                 reg = <0x30bb0000 0x10000>,
1145                                       <0x08000000 0x10000000>;
1146                                 reg-names = "QuadSPI", "QuadSPI-memory";
1147                                 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
1148                                 clocks = <&clk IMX8MQ_CLK_QSPI_ROOT>,
1149                                          <&clk IMX8MQ_CLK_QSPI_ROOT>;
1150                                 clock-names = "qspi_en", "qspi";
1151                                 status = "disabled";
1152                         };
1153
1154                         sdma1: sdma@30bd0000 {
1155                                 compatible = "fsl,imx8mq-sdma","fsl,imx7d-sdma";
1156                                 reg = <0x30bd0000 0x10000>;
1157                                 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
1158                                 clocks = <&clk IMX8MQ_CLK_SDMA1_ROOT>,
1159                                          <&clk IMX8MQ_CLK_AHB>;
1160                                 clock-names = "ipg", "ahb";
1161                                 #dma-cells = <3>;
1162                                 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
1163                         };
1164
1165                         fec1: ethernet@30be0000 {
1166                                 compatible = "fsl,imx8mq-fec", "fsl,imx6sx-fec";
1167                                 reg = <0x30be0000 0x10000>;
1168                                 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
1169                                              <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
1170                                              <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
1171                                              <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
1172                                 clocks = <&clk IMX8MQ_CLK_ENET1_ROOT>,
1173                                          <&clk IMX8MQ_CLK_ENET1_ROOT>,
1174                                          <&clk IMX8MQ_CLK_ENET_TIMER>,
1175                                          <&clk IMX8MQ_CLK_ENET_REF>,
1176                                          <&clk IMX8MQ_CLK_ENET_PHY_REF>;
1177                                 clock-names = "ipg", "ahb", "ptp",
1178                                               "enet_clk_ref", "enet_out";
1179                                 assigned-clocks = <&clk IMX8MQ_CLK_ENET_AXI>,
1180                                                   <&clk IMX8MQ_CLK_ENET_TIMER>,
1181                                                   <&clk IMX8MQ_CLK_ENET_REF>,
1182                                                   <&clk IMX8MQ_CLK_ENET_PHY_REF>;
1183                                 assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_266M>,
1184                                                          <&clk IMX8MQ_SYS2_PLL_100M>,
1185                                                          <&clk IMX8MQ_SYS2_PLL_125M>,
1186                                                          <&clk IMX8MQ_SYS2_PLL_50M>;
1187                                 assigned-clock-rates = <0>, <100000000>, <125000000>, <0>;
1188                                 fsl,num-tx-queues = <3>;
1189                                 fsl,num-rx-queues = <3>;
1190                                 nvmem-cells = <&fec_mac_address>;
1191                                 nvmem-cell-names = "mac-address";
1192                                 nvmem_macaddr_swap;
1193                                 fsl,stop-mode = <&iomuxc_gpr 0x10 3>;
1194                                 status = "disabled";
1195                         };
1196                 };
1197
1198                 noc: interconnect@32700000 {
1199                         compatible = "fsl,imx8mq-noc", "fsl,imx8m-noc";
1200                         reg = <0x32700000 0x100000>;
1201                         clocks = <&clk IMX8MQ_CLK_NOC>;
1202                         fsl,ddrc = <&ddrc>;
1203                         #interconnect-cells = <1>;
1204                         operating-points-v2 = <&noc_opp_table>;
1205
1206                         noc_opp_table: opp-table {
1207                                 compatible = "operating-points-v2";
1208
1209                                 opp-133M {
1210                                         opp-hz = /bits/ 64 <133333333>;
1211                                 };
1212
1213                                 opp-400M {
1214                                         opp-hz = /bits/ 64 <400000000>;
1215                                 };
1216
1217                                 opp-800M {
1218                                         opp-hz = /bits/ 64 <800000000>;
1219                                 };
1220                         };
1221                 };
1222
1223                 bus@32c00000 { /* AIPS4 */
1224                         compatible = "fsl,aips-bus", "simple-bus";
1225                         reg = <0x32c00000 0x400000>;
1226                         #address-cells = <1>;
1227                         #size-cells = <1>;
1228                         ranges = <0x32c00000 0x32c00000 0x400000>;
1229
1230                         irqsteer: interrupt-controller@32e2d000 {
1231                                 compatible = "fsl,imx8m-irqsteer", "fsl,imx-irqsteer";
1232                                 reg = <0x32e2d000 0x1000>;
1233                                 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
1234                                 clocks = <&clk IMX8MQ_CLK_DISP_APB_ROOT>;
1235                                 clock-names = "ipg";
1236                                 fsl,channel = <0>;
1237                                 fsl,num-irqs = <64>;
1238                                 interrupt-controller;
1239                                 #interrupt-cells = <1>;
1240                         };
1241                 };
1242
1243                 gpu: gpu@38000000 {
1244                         compatible = "vivante,gc";
1245                         reg = <0x38000000 0x40000>;
1246                         interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
1247                         clocks = <&clk IMX8MQ_CLK_GPU_ROOT>,
1248                                  <&clk IMX8MQ_CLK_GPU_SHADER_DIV>,
1249                                  <&clk IMX8MQ_CLK_GPU_AXI>,
1250                                  <&clk IMX8MQ_CLK_GPU_AHB>;
1251                         clock-names = "core", "shader", "bus", "reg";
1252                         #cooling-cells = <2>;
1253                         assigned-clocks = <&clk IMX8MQ_CLK_GPU_CORE_SRC>,
1254                                           <&clk IMX8MQ_CLK_GPU_SHADER_SRC>,
1255                                           <&clk IMX8MQ_CLK_GPU_AXI>,
1256                                           <&clk IMX8MQ_CLK_GPU_AHB>,
1257                                           <&clk IMX8MQ_GPU_PLL_BYPASS>;
1258                         assigned-clock-parents = <&clk IMX8MQ_GPU_PLL_OUT>,
1259                                                  <&clk IMX8MQ_GPU_PLL_OUT>,
1260                                                  <&clk IMX8MQ_GPU_PLL_OUT>,
1261                                                  <&clk IMX8MQ_GPU_PLL_OUT>,
1262                                                  <&clk IMX8MQ_GPU_PLL>;
1263                         assigned-clock-rates = <800000000>, <800000000>,
1264                                                <800000000>, <800000000>, <0>;
1265                         power-domains = <&pgc_gpu>;
1266                 };
1267
1268                 usb_dwc3_0: usb@38100000 {
1269                         compatible = "fsl,imx8mq-dwc3", "snps,dwc3";
1270                         reg = <0x38100000 0x10000>;
1271                         clocks = <&clk IMX8MQ_CLK_USB1_CTRL_ROOT>,
1272                                  <&clk IMX8MQ_CLK_USB_CORE_REF>,
1273                                  <&clk IMX8MQ_CLK_32K>;
1274                         clock-names = "bus_early", "ref", "suspend";
1275                         assigned-clocks = <&clk IMX8MQ_CLK_USB_BUS>,
1276                                           <&clk IMX8MQ_CLK_USB_CORE_REF>;
1277                         assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_500M>,
1278                                                  <&clk IMX8MQ_SYS1_PLL_100M>;
1279                         assigned-clock-rates = <500000000>, <100000000>;
1280                         interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
1281                         phys = <&usb3_phy0>, <&usb3_phy0>;
1282                         phy-names = "usb2-phy", "usb3-phy";
1283                         power-domains = <&pgc_otg1>;
1284                         usb3-resume-missing-cas;
1285                         status = "disabled";
1286                 };
1287
1288                 usb3_phy0: usb-phy@381f0040 {
1289                         compatible = "fsl,imx8mq-usb-phy";
1290                         reg = <0x381f0040 0x40>;
1291                         clocks = <&clk IMX8MQ_CLK_USB1_PHY_ROOT>;
1292                         clock-names = "phy";
1293                         assigned-clocks = <&clk IMX8MQ_CLK_USB_PHY_REF>;
1294                         assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_100M>;
1295                         assigned-clock-rates = <100000000>;
1296                         #phy-cells = <0>;
1297                         status = "disabled";
1298                 };
1299
1300                 usb_dwc3_1: usb@38200000 {
1301                         compatible = "fsl,imx8mq-dwc3", "snps,dwc3";
1302                         reg = <0x38200000 0x10000>;
1303                         clocks = <&clk IMX8MQ_CLK_USB2_CTRL_ROOT>,
1304                                  <&clk IMX8MQ_CLK_USB_CORE_REF>,
1305                                  <&clk IMX8MQ_CLK_32K>;
1306                         clock-names = "bus_early", "ref", "suspend";
1307                         assigned-clocks = <&clk IMX8MQ_CLK_USB_BUS>,
1308                                           <&clk IMX8MQ_CLK_USB_CORE_REF>;
1309                         assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_500M>,
1310                                                  <&clk IMX8MQ_SYS1_PLL_100M>;
1311                         assigned-clock-rates = <500000000>, <100000000>;
1312                         interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
1313                         phys = <&usb3_phy1>, <&usb3_phy1>;
1314                         phy-names = "usb2-phy", "usb3-phy";
1315                         power-domains = <&pgc_otg2>;
1316                         usb3-resume-missing-cas;
1317                         status = "disabled";
1318                 };
1319
1320                 usb3_phy1: usb-phy@382f0040 {
1321                         compatible = "fsl,imx8mq-usb-phy";
1322                         reg = <0x382f0040 0x40>;
1323                         clocks = <&clk IMX8MQ_CLK_USB2_PHY_ROOT>;
1324                         clock-names = "phy";
1325                         assigned-clocks = <&clk IMX8MQ_CLK_USB_PHY_REF>;
1326                         assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_100M>;
1327                         assigned-clock-rates = <100000000>;
1328                         #phy-cells = <0>;
1329                         status = "disabled";
1330                 };
1331
1332                 vpu: video-codec@38300000 {
1333                         compatible = "nxp,imx8mq-vpu";
1334                         reg = <0x38300000 0x10000>,
1335                               <0x38310000 0x10000>,
1336                               <0x38320000 0x10000>;
1337                         reg-names = "g1", "g2", "ctrl";
1338                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
1339                                      <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1340                         interrupt-names = "g1", "g2";
1341                         clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>,
1342                                  <&clk IMX8MQ_CLK_VPU_G2_ROOT>,
1343                                  <&clk IMX8MQ_CLK_VPU_DEC_ROOT>;
1344                         clock-names = "g1", "g2", "bus";
1345                         assigned-clocks = <&clk IMX8MQ_CLK_VPU_G1>,
1346                                           <&clk IMX8MQ_CLK_VPU_G2>,
1347                                           <&clk IMX8MQ_CLK_VPU_BUS>,
1348                                           <&clk IMX8MQ_VPU_PLL_BYPASS>;
1349                         assigned-clock-parents = <&clk IMX8MQ_VPU_PLL_OUT>,
1350                                                  <&clk IMX8MQ_VPU_PLL_OUT>,
1351                                                  <&clk IMX8MQ_SYS1_PLL_800M>,
1352                                                  <&clk IMX8MQ_VPU_PLL>;
1353                         assigned-clock-rates = <600000000>, <600000000>,
1354                                                <800000000>, <0>;
1355                         power-domains = <&pgc_vpu>;
1356                 };
1357
1358                 pcie0: pcie@33800000 {
1359                         compatible = "fsl,imx8mq-pcie";
1360                         reg = <0x33800000 0x400000>,
1361                               <0x1ff00000 0x80000>;
1362                         reg-names = "dbi", "config";
1363                         #address-cells = <3>;
1364                         #size-cells = <2>;
1365                         device_type = "pci";
1366                         bus-range = <0x00 0xff>;
1367                         ranges = <0x81000000 0 0x00000000 0x1ff80000 0 0x00010000 /* downstream I/O 64KB */
1368                                   0x82000000 0 0x18000000 0x18000000 0 0x07f00000>; /* non-prefetchable memory */
1369                         num-lanes = <1>;
1370                         num-viewport = <4>;
1371                         interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
1372                         interrupt-names = "msi";
1373                         #interrupt-cells = <1>;
1374                         interrupt-map-mask = <0 0 0 0x7>;
1375                         interrupt-map = <0 0 0 1 &gic GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
1376                                         <0 0 0 2 &gic GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
1377                                         <0 0 0 3 &gic GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
1378                                         <0 0 0 4 &gic GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
1379                         fsl,max-link-speed = <2>;
1380                         linux,pci-domain = <0>;
1381                         power-domains = <&pgc_pcie>;
1382                         resets = <&src IMX8MQ_RESET_PCIEPHY>,
1383                                  <&src IMX8MQ_RESET_PCIE_CTRL_APPS_EN>,
1384                                  <&src IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF>;
1385                         reset-names = "pciephy", "apps", "turnoff";
1386                         assigned-clocks = <&clk IMX8MQ_CLK_PCIE1_CTRL>,
1387                                           <&clk IMX8MQ_CLK_PCIE1_PHY>,
1388                                           <&clk IMX8MQ_CLK_PCIE1_AUX>;
1389                         assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_250M>,
1390                                                  <&clk IMX8MQ_SYS2_PLL_100M>,
1391                                                  <&clk IMX8MQ_SYS1_PLL_80M>;
1392                         assigned-clock-rates = <250000000>, <100000000>,
1393                                                <10000000>;
1394                         status = "disabled";
1395                 };
1396
1397                 pcie1: pcie@33c00000 {
1398                         compatible = "fsl,imx8mq-pcie";
1399                         reg = <0x33c00000 0x400000>,
1400                               <0x27f00000 0x80000>;
1401                         reg-names = "dbi", "config";
1402                         #address-cells = <3>;
1403                         #size-cells = <2>;
1404                         device_type = "pci";
1405                         ranges =  <0x81000000 0 0x00000000 0x27f80000 0 0x00010000 /* downstream I/O 64KB */
1406                                    0x82000000 0 0x20000000 0x20000000 0 0x07f00000>; /* non-prefetchable memory */
1407                         num-lanes = <1>;
1408                         num-viewport = <4>;
1409                         interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
1410                         interrupt-names = "msi";
1411                         #interrupt-cells = <1>;
1412                         interrupt-map-mask = <0 0 0 0x7>;
1413                         interrupt-map = <0 0 0 1 &gic GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
1414                                         <0 0 0 2 &gic GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
1415                                         <0 0 0 3 &gic GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
1416                                         <0 0 0 4 &gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
1417                         fsl,max-link-speed = <2>;
1418                         linux,pci-domain = <1>;
1419                         power-domains = <&pgc_pcie>;
1420                         resets = <&src IMX8MQ_RESET_PCIEPHY2>,
1421                                  <&src IMX8MQ_RESET_PCIE2_CTRL_APPS_EN>,
1422                                  <&src IMX8MQ_RESET_PCIE2_CTRL_APPS_TURNOFF>;
1423                         reset-names = "pciephy", "apps", "turnoff";
1424                         assigned-clocks = <&clk IMX8MQ_CLK_PCIE2_CTRL>,
1425                                           <&clk IMX8MQ_CLK_PCIE2_PHY>,
1426                                           <&clk IMX8MQ_CLK_PCIE2_AUX>;
1427                         assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_250M>,
1428                                                  <&clk IMX8MQ_SYS2_PLL_100M>,
1429                                                  <&clk IMX8MQ_SYS1_PLL_80M>;
1430                         assigned-clock-rates = <250000000>, <100000000>,
1431                                                <10000000>;
1432                         status = "disabled";
1433                 };
1434
1435                 gic: interrupt-controller@38800000 {
1436                         compatible = "arm,gic-v3";
1437                         reg = <0x38800000 0x10000>,     /* GIC Dist */
1438                               <0x38880000 0xc0000>,     /* GICR */
1439                               <0x31000000 0x2000>,      /* GICC */
1440                               <0x31010000 0x2000>,      /* GICV */
1441                               <0x31020000 0x2000>;      /* GICH */
1442                         #interrupt-cells = <3>;
1443                         interrupt-controller;
1444                         interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
1445                         interrupt-parent = <&gic>;
1446                 };
1447
1448                 ddrc: memory-controller@3d400000 {
1449                         compatible = "fsl,imx8mq-ddrc", "fsl,imx8m-ddrc";
1450                         reg = <0x3d400000 0x400000>;
1451                         clock-names = "core", "pll", "alt", "apb";
1452                         clocks = <&clk IMX8MQ_CLK_DRAM_CORE>,
1453                                  <&clk IMX8MQ_DRAM_PLL_OUT>,
1454                                  <&clk IMX8MQ_CLK_DRAM_ALT>,
1455                                  <&clk IMX8MQ_CLK_DRAM_APB>;
1456                 };
1457
1458                 ddr-pmu@3d800000 {
1459                         compatible = "fsl,imx8mq-ddr-pmu", "fsl,imx8m-ddr-pmu";
1460                         reg = <0x3d800000 0x400000>;
1461                         interrupt-parent = <&gic>;
1462                         interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1463                 };
1464         };
1465 };