arch/arm64/boot/dts/freescale/imx8mp.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Copyright 2019 NXP
   4  */
   5
   6 #include <dt-bindings/clock/imx8mp-clock.h>
   7 #include <dt-bindings/gpio/gpio.h>
   8 #include <dt-bindings/input/input.h>
   9 #include <dt-bindings/interrupt-controller/arm-gic.h>
  10 #include <dt-bindings/thermal/thermal.h>
  11
  12 #include "imx8mp-pinfunc.h"
  13
  14 / {
  15         interrupt-parent = <&gic>;
  16         #address-cells = <2>;
  17         #size-cells = <2>;
  18
  19         aliases {
  20                 ethernet0 = &fec;
  21                 ethernet1 = &eqos;
  22                 gpio0 = &gpio1;
  23                 gpio1 = &gpio2;
  24                 gpio2 = &gpio3;
  25                 gpio3 = &gpio4;
  26                 gpio4 = &gpio5;
  27                 i2c0 = &i2c1;
  28                 i2c1 = &i2c2;
  29                 i2c2 = &i2c3;
  30                 i2c3 = &i2c4;
  31                 i2c4 = &i2c5;
  32                 i2c5 = &i2c6;
  33                 mmc0 = &usdhc1;
  34                 mmc1 = &usdhc2;
  35                 mmc2 = &usdhc3;
  36                 serial0 = &uart1;
  37                 serial1 = &uart2;
  38                 serial2 = &uart3;
  39                 serial3 = &uart4;
  40                 spi0 = &flexspi;
  41         };
  42
  43         cpus {
  44                 #address-cells = <1>;
  45                 #size-cells = <0>;
  46
  47                 A53_0: cpu@0 {
  48                         device_type = "cpu";
  49                         compatible = "arm,cortex-a53";
  50                         reg = <0x0>;
  51                         clock-latency = <61036>;
  52                         clocks = <&clk IMX8MP_CLK_ARM>;
  53                         enable-method = "psci";
  54                         next-level-cache = <&A53_L2>;
  55                         #cooling-cells = <2>;
  56                 };
  57
  58                 A53_1: cpu@1 {
  59                         device_type = "cpu";
  60                         compatible = "arm,cortex-a53";
  61                         reg = <0x1>;
  62                         clock-latency = <61036>;
  63                         clocks = <&clk IMX8MP_CLK_ARM>;
  64                         enable-method = "psci";
  65                         next-level-cache = <&A53_L2>;
  66                         #cooling-cells = <2>;
  67                 };
  68
  69                 A53_2: cpu@2 {
  70                         device_type = "cpu";
  71                         compatible = "arm,cortex-a53";
  72                         reg = <0x2>;
  73                         clock-latency = <61036>;
  74                         clocks = <&clk IMX8MP_CLK_ARM>;
  75                         enable-method = "psci";
  76                         next-level-cache = <&A53_L2>;
  77                         #cooling-cells = <2>;
  78                 };
  79
  80                 A53_3: cpu@3 {
  81                         device_type = "cpu";
  82                         compatible = "arm,cortex-a53";
  83                         reg = <0x3>;
  84                         clock-latency = <61036>;
  85                         clocks = <&clk IMX8MP_CLK_ARM>;
  86                         enable-method = "psci";
  87                         next-level-cache = <&A53_L2>;
  88                         #cooling-cells = <2>;
  89                 };
  90
  91                 A53_L2: l2-cache0 {
  92                         compatible = "cache";
  93                 };
  94         };
  95
  96         osc_32k: clock-osc-32k {
  97                 compatible = "fixed-clock";
  98                 #clock-cells = <0>;
  99                 clock-frequency = <32768>;
 100                 clock-output-names = "osc_32k";
 101         };
 102
 103         osc_24m: clock-osc-24m {
 104                 compatible = "fixed-clock";
 105                 #clock-cells = <0>;
 106                 clock-frequency = <24000000>;
 107                 clock-output-names = "osc_24m";
 108         };
 109
 110         clk_ext1: clock-ext1 {
 111                 compatible = "fixed-clock";
 112                 #clock-cells = <0>;
 113                 clock-frequency = <133000000>;
 114                 clock-output-names = "clk_ext1";
 115         };
 116
 117         clk_ext2: clock-ext2 {
 118                 compatible = "fixed-clock";
 119                 #clock-cells = <0>;
 120                 clock-frequency = <133000000>;
 121                 clock-output-names = "clk_ext2";
 122         };
 123
 124         clk_ext3: clock-ext3 {
 125                 compatible = "fixed-clock";
 126                 #clock-cells = <0>;
 127                 clock-frequency = <133000000>;
 128                 clock-output-names = "clk_ext3";
 129         };
 130
 131         clk_ext4: clock-ext4 {
 132                 compatible = "fixed-clock";
 133                 #clock-cells = <0>;
 134                 clock-frequency= <133000000>;
 135                 clock-output-names = "clk_ext4";
 136         };
 137
 138         pmu {
 139                 compatible = "arm,cortex-a53-pmu";
 140                 interrupts = <GIC_PPI 7
 141                              (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 142                 interrupt-affinity = <&A53_0>, <&A53_1>, <&A53_2>, <&A53_3>;
 143         };
 144
 145         psci {
 146                 compatible = "arm,psci-1.0";
 147                 method = "smc";
 148         };
 149
 150         thermal-zones {
 151                 cpu-thermal {
 152                         polling-delay-passive = <250>;
 153                         polling-delay = <2000>;
 154                         thermal-sensors = <&tmu 0>;
 155                         trips {
 156                                 cpu_alert0: trip0 {
 157                                         temperature = <85000>;
 158                                         hysteresis = <2000>;
 159                                         type = "passive";
 160                                 };
 161
 162                                 cpu_crit0: trip1 {
 163                                         temperature = <95000>;
 164                                         hysteresis = <2000>;
 165                                         type = "critical";
 166                                 };
 167                         };
 168
 169                         cooling-maps {
 170                                 map0 {
 171                                         trip = <&cpu_alert0>;
 172                                         cooling-device =
 173                                                 <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 174                                                 <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 175                                                 <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 176                                                 <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 177                                 };
 178                         };
 179                 };
 180
 181                 soc-thermal {
 182                         polling-delay-passive = <250>;
 183                         polling-delay = <2000>;
 184                         thermal-sensors = <&tmu 1>;
 185                         trips {
 186                                 soc_alert0: trip0 {
 187                                         temperature = <85000>;
 188                                         hysteresis = <2000>;
 189                                         type = "passive";
 190                                 };
 191
 192                                 soc_crit0: trip1 {
 193                                         temperature = <95000>;
 194                                         hysteresis = <2000>;
 195                                         type = "critical";
 196                                 };
 197                         };
 198
 199                         cooling-maps {
 200                                 map0 {
 201                                         trip = <&soc_alert0>;
 202                                         cooling-device =
 203                                                 <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 204                                                 <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 205                                                 <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 206                                                 <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 207                                 };
 208                         };
 209                 };
 210         };
 211
 212         timer {
 213                 compatible = "arm,armv8-timer";
 214                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 215                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 216                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 217                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 218                 clock-frequency = <8000000>;
 219                 arm,no-tick-in-suspend;
 220         };
 221
 222         soc@0 {
 223                 compatible = "fsl,imx8mp-soc", "simple-bus";
 224                 #address-cells = <1>;
 225                 #size-cells = <1>;
 226                 ranges = <0x0 0x0 0x0 0x3e000000>;
 227                 nvmem-cells = <&imx8mp_uid>;
 228                 nvmem-cell-names = "soc_unique_id";
 229
 230                 aips1: bus@30000000 {
 231                         compatible = "fsl,aips-bus", "simple-bus";
 232                         reg = <0x30000000 0x400000>;
 233                         #address-cells = <1>;
 234                         #size-cells = <1>;
 235                         ranges;
 236
 237                         gpio1: gpio@30200000 {
 238                                 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio";
 239                                 reg = <0x30200000 0x10000>;
 240                                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
 241                                              <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 242                                 clocks = <&clk IMX8MP_CLK_GPIO1_ROOT>;
 243                                 gpio-controller;
 244                                 #gpio-cells = <2>;
 245                                 interrupt-controller;
 246                                 #interrupt-cells = <2>;
 247                                 gpio-ranges = <&iomuxc 0 5 30>;
 248                         };
 249
 250                         gpio2: gpio@30210000 {
 251                                 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio";
 252                                 reg = <0x30210000 0x10000>;
 253                                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
 254                                              <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
 255                                 clocks = <&clk IMX8MP_CLK_GPIO2_ROOT>;
 256                                 gpio-controller;
 257                                 #gpio-cells = <2>;
 258                                 interrupt-controller;
 259                                 #interrupt-cells = <2>;
 260                                 gpio-ranges = <&iomuxc 0 35 21>;
 261                         };
 262
 263                         gpio3: gpio@30220000 {
 264                                 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio";
 265                                 reg = <0x30220000 0x10000>;
 266                                 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
 267                                              <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
 268                                 clocks = <&clk IMX8MP_CLK_GPIO3_ROOT>;
 269                                 gpio-controller;
 270                                 #gpio-cells = <2>;
 271                                 interrupt-controller;
 272                                 #interrupt-cells = <2>;
 273                                 gpio-ranges = <&iomuxc 0 56 26>, <&iomuxc 26 144 4>;
 274                         };
 275
 276                         gpio4: gpio@30230000 {
 277                                 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio";
 278                                 reg = <0x30230000 0x10000>;
 279                                 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
 280                                              <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 281                                 clocks = <&clk IMX8MP_CLK_GPIO4_ROOT>;
 282                                 gpio-controller;
 283                                 #gpio-cells = <2>;
 284                                 interrupt-controller;
 285                                 #interrupt-cells = <2>;
 286                                 gpio-ranges = <&iomuxc 0 82 32>;
 287                         };
 288
 289                         gpio5: gpio@30240000 {
 290                                 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio";
 291                                 reg = <0x30240000 0x10000>;
 292                                 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
 293                                              <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 294                                 clocks = <&clk IMX8MP_CLK_GPIO5_ROOT>;
 295                                 gpio-controller;
 296                                 #gpio-cells = <2>;
 297                                 interrupt-controller;
 298                                 #interrupt-cells = <2>;
 299                                 gpio-ranges = <&iomuxc 0 114 30>;
 300                         };
 301
 302                         tmu: tmu@30260000 {
 303                                 compatible = "fsl,imx8mp-tmu";
 304                                 reg = <0x30260000 0x10000>;
 305                                 clocks = <&clk IMX8MP_CLK_TSENSOR_ROOT>;
 306                                 #thermal-sensor-cells = <1>;
 307                         };
 308
 309                         wdog1: watchdog@30280000 {
 310                                 compatible = "fsl,imx8mp-wdt", "fsl,imx21-wdt";
 311                                 reg = <0x30280000 0x10000>;
 312                                 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
 313                                 clocks = <&clk IMX8MP_CLK_WDOG1_ROOT>;
 314                                 status = "disabled";
 315                         };
 316
 317                         wdog2: watchdog@30290000 {
 318                                 compatible = "fsl,imx8mp-wdt", "fsl,imx21-wdt";
 319                                 reg = <0x30290000 0x10000>;
 320                                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 321                                 clocks = <&clk IMX8MP_CLK_WDOG2_ROOT>;
 322                                 status = "disabled";
 323                         };
 324
 325                         wdog3: watchdog@302a0000 {
 326                                 compatible = "fsl,imx8mp-wdt", "fsl,imx21-wdt";
 327                                 reg = <0x302a0000 0x10000>;
 328                                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 329                                 clocks = <&clk IMX8MP_CLK_WDOG3_ROOT>;
 330                                 status = "disabled";
 331                         };
 332
 333                         iomuxc: pinctrl@30330000 {
 334                                 compatible = "fsl,imx8mp-iomuxc";
 335                                 reg = <0x30330000 0x10000>;
 336                         };
 337
 338                         gpr: iomuxc-gpr@30340000 {
 339                                 compatible = "fsl,imx8mp-iomuxc-gpr", "syscon";
 340                                 reg = <0x30340000 0x10000>;
 341                         };
 342
 343                         ocotp: efuse@30350000 {
 344                                 compatible = "fsl,imx8mp-ocotp", "fsl,imx8mm-ocotp", "syscon";
 345                                 reg = <0x30350000 0x10000>;
 346                                 clocks = <&clk IMX8MP_CLK_OCOTP_ROOT>;
 347                                 /* For nvmem subnodes */
 348                                 #address-cells = <1>;
 349                                 #size-cells = <1>;
 350
 351                                 imx8mp_uid: unique-id@420 {
 352                                         reg = <0x8 0x8>;
 353                                 };
 354
 355                                 cpu_speed_grade: speed-grade@10 {
 356                                         reg = <0x10 4>;
 357                                 };
 358
 359                                 eth_mac1: mac-address@90 {
 360                                         reg = <0x90 6>;
 361                                 };
 362                         };
 363
 364                         anatop: anatop@30360000 {
 365                                 compatible = "fsl,imx8mp-anatop", "fsl,imx8mm-anatop",
 366                                              "syscon";
 367                                 reg = <0x30360000 0x10000>;
 368                         };
 369
 370                         snvs: snvs@30370000 {
 371                                 compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd";
 372                                 reg = <0x30370000 0x10000>;
 373
 374                                 snvs_rtc: snvs-rtc-lp {
 375                                         compatible = "fsl,sec-v4.0-mon-rtc-lp";
 376                                         regmap =<&snvs>;
 377                                         offset = <0x34>;
 378                                         interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
 379                                                      <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 380                                         clocks = <&clk IMX8MP_CLK_SNVS_ROOT>;
 381                                         clock-names = "snvs-rtc";
 382                                 };
 383
 384                                 snvs_pwrkey: snvs-powerkey {
 385                                         compatible = "fsl,sec-v4.0-pwrkey";
 386                                         regmap = <&snvs>;
 387                                         interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 388                                         clocks = <&clk IMX8MP_CLK_SNVS_ROOT>;
 389                                         clock-names = "snvs-pwrkey";
 390                                         linux,keycode = <KEY_POWER>;
 391                                         wakeup-source;
 392                                         status = "disabled";
 393                                 };
 394                         };
 395
 396                         clk: clock-controller@30380000 {
 397                                 compatible = "fsl,imx8mp-ccm";
 398                                 reg = <0x30380000 0x10000>;
 399                                 #clock-cells = <1>;
 400                                 clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>,
 401                                          <&clk_ext3>, <&clk_ext4>;
 402                                 clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2",
 403                                               "clk_ext3", "clk_ext4";
 404                                 assigned-clocks = <&clk IMX8MP_CLK_A53_SRC>,
 405                                                   <&clk IMX8MP_CLK_A53_CORE>,
 406                                                   <&clk IMX8MP_CLK_NOC>,
 407                                                   <&clk IMX8MP_CLK_NOC_IO>,
 408                                                   <&clk IMX8MP_CLK_GIC>,
 409                                                   <&clk IMX8MP_CLK_AUDIO_AHB>,
 410                                                   <&clk IMX8MP_CLK_AUDIO_AXI_SRC>,
 411                                                   <&clk IMX8MP_AUDIO_PLL1>,
 412                                                   <&clk IMX8MP_AUDIO_PLL2>;
 413                                 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,
 414                                                          <&clk IMX8MP_ARM_PLL_OUT>,
 415                                                          <&clk IMX8MP_SYS_PLL2_1000M>,
 416                                                          <&clk IMX8MP_SYS_PLL1_800M>,
 417                                                          <&clk IMX8MP_SYS_PLL2_500M>,
 418                                                          <&clk IMX8MP_SYS_PLL1_800M>,
 419                                                          <&clk IMX8MP_SYS_PLL1_800M>;
 420                                 assigned-clock-rates = <0>, <0>,
 421                                                        <1000000000>,
 422                                                        <800000000>,
 423                                                        <500000000>,
 424                                                        <400000000>,
 425                                                        <800000000>,
 426                                                        <393216000>,
 427                                                        <361267200>;
 428                         };
 429
 430                         src: reset-controller@30390000 {
 431                                 compatible = "fsl,imx8mp-src", "syscon";
 432                                 reg = <0x30390000 0x10000>;
 433                                 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
 434                                 #reset-cells = <1>;
 435                         };
 436                 };
 437
 438                 aips2: bus@30400000 {
 439                         compatible = "fsl,aips-bus", "simple-bus";
 440                         reg = <0x30400000 0x400000>;
 441                         #address-cells = <1>;
 442                         #size-cells = <1>;
 443                         ranges;
 444
 445                         pwm1: pwm@30660000 {
 446                                 compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm";
 447                                 reg = <0x30660000 0x10000>;
 448                                 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
 449                                 clocks = <&clk IMX8MP_CLK_PWM1_ROOT>,
 450                                          <&clk IMX8MP_CLK_PWM1_ROOT>;
 451                                 clock-names = "ipg", "per";
 452                                 #pwm-cells = <2>;
 453                                 status = "disabled";
 454                         };
 455
 456                         pwm2: pwm@30670000 {
 457                                 compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm";
 458                                 reg = <0x30670000 0x10000>;
 459                                 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 460                                 clocks = <&clk IMX8MP_CLK_PWM2_ROOT>,
 461                                          <&clk IMX8MP_CLK_PWM2_ROOT>;
 462                                 clock-names = "ipg", "per";
 463                                 #pwm-cells = <2>;
 464                                 status = "disabled";
 465                         };
 466
 467                         pwm3: pwm@30680000 {
 468                                 compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm";
 469                                 reg = <0x30680000 0x10000>;
 470                                 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 471                                 clocks = <&clk IMX8MP_CLK_PWM3_ROOT>,
 472                                          <&clk IMX8MP_CLK_PWM3_ROOT>;
 473                                 clock-names = "ipg", "per";
 474                                 #pwm-cells = <2>;
 475                                 status = "disabled";
 476                         };
 477
 478                         pwm4: pwm@30690000 {
 479                                 compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm";
 480                                 reg = <0x30690000 0x10000>;
 481                                 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 482                                 clocks = <&clk IMX8MP_CLK_PWM4_ROOT>,
 483                                          <&clk IMX8MP_CLK_PWM4_ROOT>;
 484                                 clock-names = "ipg", "per";
 485                                 #pwm-cells = <2>;
 486                                 status = "disabled";
 487                         };
 488
 489                         system_counter: timer@306a0000 {
 490                                 compatible = "nxp,sysctr-timer";
 491                                 reg = <0x306a0000 0x20000>;
 492                                 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
 493                                 clocks = <&osc_24m>;
 494                                 clock-names = "per";
 495                         };
 496                 };
 497
 498                 aips3: bus@30800000 {
 499                         compatible = "fsl,aips-bus", "simple-bus";
 500                         reg = <0x30800000 0x400000>;
 501                         #address-cells = <1>;
 502                         #size-cells = <1>;
 503                         ranges;
 504
 505                         ecspi1: spi@30820000 {
 506                                 #address-cells = <1>;
 507                                 #size-cells = <0>;
 508                                 compatible = "fsl,imx8mp-ecspi", "fsl,imx51-ecspi";
 509                                 reg = <0x30820000 0x10000>;
 510                                 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 511                                 clocks = <&clk IMX8MP_CLK_ECSPI1_ROOT>,
 512                                          <&clk IMX8MP_CLK_ECSPI1_ROOT>;
 513                                 clock-names = "ipg", "per";
 514                                 dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>;
 515                                 dma-names = "rx", "tx";
 516                                 status = "disabled";
 517                         };
 518
 519                         ecspi2: spi@30830000 {
 520                                 #address-cells = <1>;
 521                                 #size-cells = <0>;
 522                                 compatible = "fsl,imx8mp-ecspi", "fsl,imx51-ecspi";
 523                                 reg = <0x30830000 0x10000>;
 524                                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 525                                 clocks = <&clk IMX8MP_CLK_ECSPI2_ROOT>,
 526                                          <&clk IMX8MP_CLK_ECSPI2_ROOT>;
 527                                 clock-names = "ipg", "per";
 528                                 dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>;
 529                                 dma-names = "rx", "tx";
 530                                 status = "disabled";
 531                         };
 532
 533                         ecspi3: spi@30840000 {
 534                                 #address-cells = <1>;
 535                                 #size-cells = <0>;
 536                                 compatible = "fsl,imx8mp-ecspi", "fsl,imx51-ecspi";
 537                                 reg = <0x30840000 0x10000>;
 538                                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 539                                 clocks = <&clk IMX8MP_CLK_ECSPI3_ROOT>,
 540                                          <&clk IMX8MP_CLK_ECSPI3_ROOT>;
 541                                 clock-names = "ipg", "per";
 542                                 dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>;
 543                                 dma-names = "rx", "tx";
 544                                 status = "disabled";
 545                         };
 546
 547                         uart1: serial@30860000 {
 548                                 compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";
 549                                 reg = <0x30860000 0x10000>;
 550                                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 551                                 clocks = <&clk IMX8MP_CLK_UART1_ROOT>,
 552                                          <&clk IMX8MP_CLK_UART1_ROOT>;
 553                                 clock-names = "ipg", "per";
 554                                 dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>;
 555                                 dma-names = "rx", "tx";
 556                                 status = "disabled";
 557                         };
 558
 559                         uart3: serial@30880000 {
 560                                 compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";
 561                                 reg = <0x30880000 0x10000>;
 562                                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 563                                 clocks = <&clk IMX8MP_CLK_UART3_ROOT>,
 564                                          <&clk IMX8MP_CLK_UART3_ROOT>;
 565                                 clock-names = "ipg", "per";
 566                                 dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>;
 567                                 dma-names = "rx", "tx";
 568                                 status = "disabled";
 569                         };
 570
 571                         uart2: serial@30890000 {
 572                                 compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";
 573                                 reg = <0x30890000 0x10000>;
 574                                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 575                                 clocks = <&clk IMX8MP_CLK_UART2_ROOT>,
 576                                          <&clk IMX8MP_CLK_UART2_ROOT>;
 577                                 clock-names = "ipg", "per";
 578                                 status = "disabled";
 579                         };
 580
 581                         flexcan1: can@308c0000 {
 582                                 compatible = "fsl,imx8mp-flexcan", "fsl,imx6q-flexcan";
 583                                 reg = <0x308c0000 0x10000>;
 584                                 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
 585                                 clocks = <&clk IMX8MP_CLK_IPG_ROOT>,
 586                                          <&clk IMX8MP_CLK_CAN1_ROOT>;
 587                                 clock-names = "ipg", "per";
 588                                 assigned-clocks = <&clk IMX8MP_CLK_CAN1>;
 589                                 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_40M>;
 590                                 assigned-clock-rates = <40000000>;
 591                                 fsl,clk-source = /bits/ 8 <0>;
 592                                 fsl,stop-mode = <&gpr 0x10 4>;
 593                                 status = "disabled";
 594                         };
 595
 596                         flexcan2: can@308d0000 {
 597                                 compatible = "fsl,imx8mp-flexcan", "fsl,imx6q-flexcan";
 598                                 reg = <0x308d0000 0x10000>;
 599                                 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
 600                                 clocks = <&clk IMX8MP_CLK_IPG_ROOT>,
 601                                          <&clk IMX8MP_CLK_CAN2_ROOT>;
 602                                 clock-names = "ipg", "per";
 603                                 assigned-clocks = <&clk IMX8MP_CLK_CAN2>;
 604                                 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_40M>;
 605                                 assigned-clock-rates = <40000000>;
 606                                 fsl,clk-source = /bits/ 8 <0>;
 607                                 fsl,stop-mode = <&gpr 0x10 5>;
 608                                 status = "disabled";
 609                         };
 610
 611                         crypto: crypto@30900000 {
 612                                 compatible = "fsl,sec-v4.0";
 613                                 #address-cells = <1>;
 614                                 #size-cells = <1>;
 615                                 reg = <0x30900000 0x40000>;
 616                                 ranges = <0 0x30900000 0x40000>;
 617                                 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
 618                                 clocks = <&clk IMX8MP_CLK_AHB>,
 619                                          <&clk IMX8MP_CLK_IPG_ROOT>;
 620                                 clock-names = "aclk", "ipg";
 621
 622                                 sec_jr0: jr@1000 {
 623                                         compatible = "fsl,sec-v4.0-job-ring";
 624                                         reg = <0x1000 0x1000>;
 625                                         interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
 626                                 };
 627
 628                                 sec_jr1: jr@2000 {
 629                                         compatible = "fsl,sec-v4.0-job-ring";
 630                                         reg = <0x2000 0x1000>;
 631                                         interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
 632                                 };
 633
 634                                 sec_jr2: jr@3000 {
 635                                         compatible = "fsl,sec-v4.0-job-ring";
 636                                         reg = <0x3000 0x1000>;
 637                                         interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
 638                                 };
 639                         };
 640
 641                         i2c1: i2c@30a20000 {
 642                                 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
 643                                 #address-cells = <1>;
 644                                 #size-cells = <0>;
 645                                 reg = <0x30a20000 0x10000>;
 646                                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 647                                 clocks = <&clk IMX8MP_CLK_I2C1_ROOT>;
 648                                 status = "disabled";
 649                         };
 650
 651                         i2c2: i2c@30a30000 {
 652                                 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
 653                                 #address-cells = <1>;
 654                                 #size-cells = <0>;
 655                                 reg = <0x30a30000 0x10000>;
 656                                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 657                                 clocks = <&clk IMX8MP_CLK_I2C2_ROOT>;
 658                                 status = "disabled";
 659                         };
 660
 661                         i2c3: i2c@30a40000 {
 662                                 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
 663                                 #address-cells = <1>;
 664                                 #size-cells = <0>;
 665                                 reg = <0x30a40000 0x10000>;
 666                                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 667                                 clocks = <&clk IMX8MP_CLK_I2C3_ROOT>;
 668                                 status = "disabled";
 669                         };
 670
 671                         i2c4: i2c@30a50000 {
 672                                 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
 673                                 #address-cells = <1>;
 674                                 #size-cells = <0>;
 675                                 reg = <0x30a50000 0x10000>;
 676                                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 677                                 clocks = <&clk IMX8MP_CLK_I2C4_ROOT>;
 678                                 status = "disabled";
 679                         };
 680
 681                         uart4: serial@30a60000 {
 682                                 compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";
 683                                 reg = <0x30a60000 0x10000>;
 684                                 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 685                                 clocks = <&clk IMX8MP_CLK_UART4_ROOT>,
 686                                          <&clk IMX8MP_CLK_UART4_ROOT>;
 687                                 clock-names = "ipg", "per";
 688                                 dmas = <&sdma1 28 4 0>, <&sdma1 29 4 0>;
 689                                 dma-names = "rx", "tx";
 690                                 status = "disabled";
 691                         };
 692
 693                         mu: mailbox@30aa0000 {
 694                                 compatible = "fsl,imx8mp-mu", "fsl,imx6sx-mu";
 695                                 reg = <0x30aa0000 0x10000>;
 696                                 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
 697                                 clocks = <&clk IMX8MP_CLK_MU_ROOT>;
 698                                 #mbox-cells = <2>;
 699                         };
 700
 701                         i2c5: i2c@30ad0000 {
 702                                 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
 703                                 #address-cells = <1>;
 704                                 #size-cells = <0>;
 705                                 reg = <0x30ad0000 0x10000>;
 706                                 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
 707                                 clocks = <&clk IMX8MP_CLK_I2C5_ROOT>;
 708                                 status = "disabled";
 709                         };
 710
 711                         i2c6: i2c@30ae0000 {
 712                                 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
 713                                 #address-cells = <1>;
 714                                 #size-cells = <0>;
 715                                 reg = <0x30ae0000 0x10000>;
 716                                 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
 717                                 clocks = <&clk IMX8MP_CLK_I2C6_ROOT>;
 718                                 status = "disabled";
 719                         };
 720
 721                         usdhc1: mmc@30b40000 {
 722                                 compatible = "fsl,imx8mp-usdhc", "fsl,imx7d-usdhc";
 723                                 reg = <0x30b40000 0x10000>;
 724                                 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
 725                                 clocks = <&clk IMX8MP_CLK_DUMMY>,
 726                                          <&clk IMX8MP_CLK_NAND_USDHC_BUS>,
 727                                          <&clk IMX8MP_CLK_USDHC1_ROOT>;
 728                                 clock-names = "ipg", "ahb", "per";
 729                                 fsl,tuning-start-tap = <20>;
 730                                 fsl,tuning-step= <2>;
 731                                 bus-width = <4>;
 732                                 status = "disabled";
 733                         };
 734
 735                         usdhc2: mmc@30b50000 {
 736                                 compatible = "fsl,imx8mp-usdhc", "fsl,imx7d-usdhc";
 737                                 reg = <0x30b50000 0x10000>;
 738                                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 739                                 clocks = <&clk IMX8MP_CLK_DUMMY>,
 740                                          <&clk IMX8MP_CLK_NAND_USDHC_BUS>,
 741                                          <&clk IMX8MP_CLK_USDHC2_ROOT>;
 742                                 clock-names = "ipg", "ahb", "per";
 743                                 fsl,tuning-start-tap = <20>;
 744                                 fsl,tuning-step= <2>;
 745                                 bus-width = <4>;
 746                                 status = "disabled";
 747                         };
 748
 749                         usdhc3: mmc@30b60000 {
 750                                 compatible = "fsl,imx8mp-usdhc", "fsl,imx7d-usdhc";
 751                                 reg = <0x30b60000 0x10000>;
 752                                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 753                                 clocks = <&clk IMX8MP_CLK_DUMMY>,
 754                                          <&clk IMX8MP_CLK_NAND_USDHC_BUS>,
 755                                          <&clk IMX8MP_CLK_USDHC3_ROOT>;
 756                                 clock-names = "ipg", "ahb", "per";
 757                                 fsl,tuning-start-tap = <20>;
 758                                 fsl,tuning-step= <2>;
 759                                 bus-width = <4>;
 760                                 status = "disabled";
 761                         };
 762
 763                         flexspi: spi@30bb0000 {
 764                                 compatible = "nxp,imx8mp-fspi";
 765                                 reg = <0x30bb0000 0x10000>, <0x8000000 0x10000000>;
 766                                 reg-names = "fspi_base", "fspi_mmap";
 767                                 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
 768                                 clocks = <&clk IMX8MP_CLK_QSPI_ROOT>,
 769                                          <&clk IMX8MP_CLK_QSPI_ROOT>;
 770                                 clock-names = "fspi", "fspi_en";
 771                                 assigned-clock-rates = <80000000>;
 772                                 assigned-clocks = <&clk IMX8MP_CLK_QSPI>;
 773                                 #address-cells = <1>;
 774                                 #size-cells = <0>;
 775                                 status = "disabled";
 776                         };
 777
 778                         sdma1: dma-controller@30bd0000 {
 779                                 compatible = "fsl,imx8mp-sdma", "fsl,imx8mq-sdma";
 780                                 reg = <0x30bd0000 0x10000>;
 781                                 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
 782                                 clocks = <&clk IMX8MP_CLK_SDMA1_ROOT>,
 783                                          <&clk IMX8MP_CLK_AHB>;
 784                                 clock-names = "ipg", "ahb";
 785                                 #dma-cells = <3>;
 786                                 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
 787                         };
 788
 789                         fec: ethernet@30be0000 {
 790                                 compatible = "fsl,imx8mp-fec", "fsl,imx8mq-fec", "fsl,imx6sx-fec";
 791                                 reg = <0x30be0000 0x10000>;
 792                                 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
 793                                              <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
 794                                              <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
 795                                              <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
 796                                 clocks = <&clk IMX8MP_CLK_ENET1_ROOT>,
 797                                          <&clk IMX8MP_CLK_SIM_ENET_ROOT>,
 798                                          <&clk IMX8MP_CLK_ENET_TIMER>,
 799                                          <&clk IMX8MP_CLK_ENET_REF>,
 800                                          <&clk IMX8MP_CLK_ENET_PHY_REF>;
 801                                 clock-names = "ipg", "ahb", "ptp",
 802                                               "enet_clk_ref", "enet_out";
 803                                 assigned-clocks = <&clk IMX8MP_CLK_ENET_AXI>,
 804                                                   <&clk IMX8MP_CLK_ENET_TIMER>,
 805                                                   <&clk IMX8MP_CLK_ENET_REF>,
 806                                                   <&clk IMX8MP_CLK_ENET_PHY_REF>;
 807                                 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>,
 808                                                          <&clk IMX8MP_SYS_PLL2_100M>,
 809                                                          <&clk IMX8MP_SYS_PLL2_125M>,
 810                                                          <&clk IMX8MP_SYS_PLL2_50M>;
 811                                 assigned-clock-rates = <0>, <100000000>, <125000000>, <0>;
 812                                 fsl,num-tx-queues = <3>;
 813                                 fsl,num-rx-queues = <3>;
 814                                 nvmem-cells = <&eth_mac1>;
 815                                 nvmem-cell-names = "mac-address";
 816                                 fsl,stop-mode = <&gpr 0x10 3>;
 817                                 nvmem_macaddr_swap;
 818                                 status = "disabled";
 819                         };
 820
 821                         eqos: ethernet@30bf0000 {
 822                                 compatible = "nxp,imx8mp-dwmac-eqos", "snps,dwmac-5.10a";
 823                                 reg = <0x30bf0000 0x10000>;
 824                                 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
 825                                              <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
 826                                 interrupt-names = "macirq", "eth_wake_irq";
 827                                 clocks = <&clk IMX8MP_CLK_ENET_QOS_ROOT>,
 828                                          <&clk IMX8MP_CLK_QOS_ENET_ROOT>,
 829                                          <&clk IMX8MP_CLK_ENET_QOS_TIMER>,
 830                                          <&clk IMX8MP_CLK_ENET_QOS>;
 831                                 clock-names = "stmmaceth", "pclk", "ptp_ref", "tx";
 832                                 assigned-clocks = <&clk IMX8MP_CLK_ENET_AXI>,
 833                                                   <&clk IMX8MP_CLK_ENET_QOS_TIMER>,
 834                                                   <&clk IMX8MP_CLK_ENET_QOS>;
 835                                 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>,
 836                                                          <&clk IMX8MP_SYS_PLL2_100M>,
 837                                                          <&clk IMX8MP_SYS_PLL2_125M>;
 838                                 assigned-clock-rates = <0>, <100000000>, <125000000>;
 839                                 intf_mode = <&gpr 0x4>;
 840                                 status = "disabled";
 841                         };
 842                 };
 843
 844                 gic: interrupt-controller@38800000 {
 845                         compatible = "arm,gic-v3";
 846                         reg = <0x38800000 0x10000>,
 847                               <0x38880000 0xc0000>;
 848                         #interrupt-cells = <3>;
 849                         interrupt-controller;
 850                         interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
 851                         interrupt-parent = <&gic>;
 852                 };
 853
 854                 ddr-pmu@3d800000 {
 855                         compatible = "fsl,imx8mp-ddr-pmu", "fsl,imx8m-ddr-pmu";
 856                         reg = <0x3d800000 0x400000>;
 857                         interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
 858                 };
 859
 860                 usb3_phy0: usb-phy@381f0040 {
 861                         compatible = "fsl,imx8mp-usb-phy";
 862                         reg = <0x381f0040 0x40>;
 863                         clocks = <&clk IMX8MP_CLK_USB_PHY_ROOT>;
 864                         clock-names = "phy";
 865                         assigned-clocks = <&clk IMX8MP_CLK_USB_PHY_REF>;
 866                         assigned-clock-parents = <&clk IMX8MP_CLK_24M>;
 867                         #phy-cells = <0>;
 868                         status = "disabled";
 869                 };
 870
 871                 usb3_0: usb@32f10100 {
 872                         compatible = "fsl,imx8mp-dwc3";
 873                         reg = <0x32f10100 0x8>;
 874                         clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,
 875                                  <&clk IMX8MP_CLK_USB_ROOT>;
 876                         clock-names = "hsio", "suspend";
 877                         interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
 878                         #address-cells = <1>;
 879                         #size-cells = <1>;
 880                         dma-ranges = <0x40000000 0x40000000 0xc0000000>;
 881                         ranges;
 882                         status = "disabled";
 883
 884                         usb_dwc3_0: usb@38100000 {
 885                                 compatible = "snps,dwc3";
 886                                 reg = <0x38100000 0x10000>;
 887                                 clocks = <&clk IMX8MP_CLK_HSIO_AXI>,
 888                                          <&clk IMX8MP_CLK_USB_CORE_REF>,
 889                                          <&clk IMX8MP_CLK_USB_ROOT>;
 890                                 clock-names = "bus_early", "ref", "suspend";
 891                                 assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>;
 892                                 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>;
 893                                 assigned-clock-rates = <500000000>;
 894                                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 895                                 phys = <&usb3_phy0>, <&usb3_phy0>;
 896                                 phy-names = "usb2-phy", "usb3-phy";
 897                                 snps,dis-u2-freeclk-exists-quirk;
 898                         };
 899
 900                 };
 901
 902                 usb3_phy1: usb-phy@382f0040 {
 903                         compatible = "fsl,imx8mp-usb-phy";
 904                         reg = <0x382f0040 0x40>;
 905                         clocks = <&clk IMX8MP_CLK_USB_PHY_ROOT>;
 906                         clock-names = "phy";
 907                         assigned-clocks = <&clk IMX8MP_CLK_USB_PHY_REF>;
 908                         assigned-clock-parents = <&clk IMX8MP_CLK_24M>;
 909                         #phy-cells = <0>;
 910                 };
 911
 912                 usb3_1: usb@32f10108 {
 913                         compatible = "fsl,imx8mp-dwc3";
 914                         reg = <0x32f10108 0x8>;
 915                         clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,
 916                                  <&clk IMX8MP_CLK_USB_ROOT>;
 917                         clock-names = "hsio", "suspend";
 918                         interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
 919                         #address-cells = <1>;
 920                         #size-cells = <1>;
 921                         dma-ranges = <0x40000000 0x40000000 0xc0000000>;
 922                         ranges;
 923                         status = "disabled";
 924
 925                         usb_dwc3_1: usb@38200000 {
 926                                 compatible = "snps,dwc3";
 927                                 reg = <0x38200000 0x10000>;
 928                                 clocks = <&clk IMX8MP_CLK_HSIO_AXI>,
 929                                          <&clk IMX8MP_CLK_USB_CORE_REF>,
 930                                          <&clk IMX8MP_CLK_USB_ROOT>;
 931                                 clock-names = "bus_early", "ref", "suspend";
 932                                 assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>;
 933                                 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>;
 934                                 assigned-clock-rates = <500000000>;
 935                                 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 936                                 phys = <&usb3_phy1>, <&usb3_phy1>;
 937                                 phy-names = "usb2-phy", "usb3-phy";
 938                                 snps,dis-u2-freeclk-exists-quirk;
 939                         };
 940                 };
 941         };
 942 };