arch/arm64/boot/dts/freescale/imx8mp.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Copyright 2019 NXP
   4  */
   5
   6 #include <dt-bindings/clock/imx8mp-clock.h>
   7 #include <dt-bindings/power/imx8mp-power.h>
   8 #include <dt-bindings/gpio/gpio.h>
   9 #include <dt-bindings/input/input.h>
  10 #include <dt-bindings/interrupt-controller/arm-gic.h>
  11 #include <dt-bindings/thermal/thermal.h>
  12
  13 #include "imx8mp-pinfunc.h"
  14
  15 / {
  16         interrupt-parent = <&gic>;
  17         #address-cells = <2>;
  18         #size-cells = <2>;
  19
  20         aliases {
  21                 ethernet0 = &fec;
  22                 ethernet1 = &eqos;
  23                 gpio0 = &gpio1;
  24                 gpio1 = &gpio2;
  25                 gpio2 = &gpio3;
  26                 gpio3 = &gpio4;
  27                 gpio4 = &gpio5;
  28                 i2c0 = &i2c1;
  29                 i2c1 = &i2c2;
  30                 i2c2 = &i2c3;
  31                 i2c3 = &i2c4;
  32                 i2c4 = &i2c5;
  33                 i2c5 = &i2c6;
  34                 mmc0 = &usdhc1;
  35                 mmc1 = &usdhc2;
  36                 mmc2 = &usdhc3;
  37                 serial0 = &uart1;
  38                 serial1 = &uart2;
  39                 serial2 = &uart3;
  40                 serial3 = &uart4;
  41                 spi0 = &flexspi;
  42         };
  43
  44         cpus {
  45                 #address-cells = <1>;
  46                 #size-cells = <0>;
  47
  48                 A53_0: cpu@0 {
  49                         device_type = "cpu";
  50                         compatible = "arm,cortex-a53";
  51                         reg = <0x0>;
  52                         clock-latency = <61036>;
  53                         clocks = <&clk IMX8MP_CLK_ARM>;
  54                         enable-method = "psci";
  55                         i-cache-size = <0x8000>;
  56                         i-cache-line-size = <64>;
  57                         i-cache-sets = <256>;
  58                         d-cache-size = <0x8000>;
  59                         d-cache-line-size = <64>;
  60                         d-cache-sets = <128>;
  61                         next-level-cache = <&A53_L2>;
  62                         nvmem-cells = <&cpu_speed_grade>;
  63                         nvmem-cell-names = "speed_grade";
  64                         operating-points-v2 = <&a53_opp_table>;
  65                         #cooling-cells = <2>;
  66                 };
  67
  68                 A53_1: cpu@1 {
  69                         device_type = "cpu";
  70                         compatible = "arm,cortex-a53";
  71                         reg = <0x1>;
  72                         clock-latency = <61036>;
  73                         clocks = <&clk IMX8MP_CLK_ARM>;
  74                         enable-method = "psci";
  75                         i-cache-size = <0x8000>;
  76                         i-cache-line-size = <64>;
  77                         i-cache-sets = <256>;
  78                         d-cache-size = <0x8000>;
  79                         d-cache-line-size = <64>;
  80                         d-cache-sets = <128>;
  81                         next-level-cache = <&A53_L2>;
  82                         operating-points-v2 = <&a53_opp_table>;
  83                         #cooling-cells = <2>;
  84                 };
  85
  86                 A53_2: cpu@2 {
  87                         device_type = "cpu";
  88                         compatible = "arm,cortex-a53";
  89                         reg = <0x2>;
  90                         clock-latency = <61036>;
  91                         clocks = <&clk IMX8MP_CLK_ARM>;
  92                         enable-method = "psci";
  93                         i-cache-size = <0x8000>;
  94                         i-cache-line-size = <64>;
  95                         i-cache-sets = <256>;
  96                         d-cache-size = <0x8000>;
  97                         d-cache-line-size = <64>;
  98                         d-cache-sets = <128>;
  99                         next-level-cache = <&A53_L2>;
 100                         operating-points-v2 = <&a53_opp_table>;
 101                         #cooling-cells = <2>;
 102                 };
 103
 104                 A53_3: cpu@3 {
 105                         device_type = "cpu";
 106                         compatible = "arm,cortex-a53";
 107                         reg = <0x3>;
 108                         clock-latency = <61036>;
 109                         clocks = <&clk IMX8MP_CLK_ARM>;
 110                         enable-method = "psci";
 111                         i-cache-size = <0x8000>;
 112                         i-cache-line-size = <64>;
 113                         i-cache-sets = <256>;
 114                         d-cache-size = <0x8000>;
 115                         d-cache-line-size = <64>;
 116                         d-cache-sets = <128>;
 117                         next-level-cache = <&A53_L2>;
 118                         operating-points-v2 = <&a53_opp_table>;
 119                         #cooling-cells = <2>;
 120                 };
 121
 122                 A53_L2: l2-cache0 {
 123                         compatible = "cache";
 124                         cache-level = <2>;
 125                         cache-size = <0x80000>;
 126                         cache-line-size = <64>;
 127                         cache-sets = <512>;
 128                 };
 129         };
 130
 131         a53_opp_table: opp-table {
 132                 compatible = "operating-points-v2";
 133                 opp-shared;
 134
 135                 opp-1200000000 {
 136                         opp-hz = /bits/ 64 <1200000000>;
 137                         opp-microvolt = <850000>;
 138                         opp-supported-hw = <0x8a0>, <0x7>;
 139                         clock-latency-ns = <150000>;
 140                         opp-suspend;
 141                 };
 142
 143                 opp-1600000000 {
 144                         opp-hz = /bits/ 64 <1600000000>;
 145                         opp-microvolt = <950000>;
 146                         opp-supported-hw = <0xa0>, <0x7>;
 147                         clock-latency-ns = <150000>;
 148                         opp-suspend;
 149                 };
 150
 151                 opp-1800000000 {
 152                         opp-hz = /bits/ 64 <1800000000>;
 153                         opp-microvolt = <1000000>;
 154                         opp-supported-hw = <0x20>, <0x3>;
 155                         clock-latency-ns = <150000>;
 156                         opp-suspend;
 157                 };
 158         };
 159
 160         osc_32k: clock-osc-32k {
 161                 compatible = "fixed-clock";
 162                 #clock-cells = <0>;
 163                 clock-frequency = <32768>;
 164                 clock-output-names = "osc_32k";
 165         };
 166
 167         osc_24m: clock-osc-24m {
 168                 compatible = "fixed-clock";
 169                 #clock-cells = <0>;
 170                 clock-frequency = <24000000>;
 171                 clock-output-names = "osc_24m";
 172         };
 173
 174         clk_ext1: clock-ext1 {
 175                 compatible = "fixed-clock";
 176                 #clock-cells = <0>;
 177                 clock-frequency = <133000000>;
 178                 clock-output-names = "clk_ext1";
 179         };
 180
 181         clk_ext2: clock-ext2 {
 182                 compatible = "fixed-clock";
 183                 #clock-cells = <0>;
 184                 clock-frequency = <133000000>;
 185                 clock-output-names = "clk_ext2";
 186         };
 187
 188         clk_ext3: clock-ext3 {
 189                 compatible = "fixed-clock";
 190                 #clock-cells = <0>;
 191                 clock-frequency = <133000000>;
 192                 clock-output-names = "clk_ext3";
 193         };
 194
 195         clk_ext4: clock-ext4 {
 196                 compatible = "fixed-clock";
 197                 #clock-cells = <0>;
 198                 clock-frequency= <133000000>;
 199                 clock-output-names = "clk_ext4";
 200         };
 201
 202         reserved-memory {
 203                 #address-cells = <2>;
 204                 #size-cells = <2>;
 205                 ranges;
 206
 207                 dsp_reserved: dsp@92400000 {
 208                         reg = <0 0x92400000 0 0x2000000>;
 209                         no-map;
 210                 };
 211         };
 212
 213         pmu {
 214                 compatible = "arm,cortex-a53-pmu";
 215                 interrupts = <GIC_PPI 7
 216                              (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 217         };
 218
 219         psci {
 220                 compatible = "arm,psci-1.0";
 221                 method = "smc";
 222         };
 223
 224         thermal-zones {
 225                 cpu-thermal {
 226                         polling-delay-passive = <250>;
 227                         polling-delay = <2000>;
 228                         thermal-sensors = <&tmu 0>;
 229                         trips {
 230                                 cpu_alert0: trip0 {
 231                                         temperature = <85000>;
 232                                         hysteresis = <2000>;
 233                                         type = "passive";
 234                                 };
 235
 236                                 cpu_crit0: trip1 {
 237                                         temperature = <95000>;
 238                                         hysteresis = <2000>;
 239                                         type = "critical";
 240                                 };
 241                         };
 242
 243                         cooling-maps {
 244                                 map0 {
 245                                         trip = <&cpu_alert0>;
 246                                         cooling-device =
 247                                                 <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 248                                                 <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 249                                                 <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 250                                                 <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 251                                 };
 252                         };
 253                 };
 254
 255                 soc-thermal {
 256                         polling-delay-passive = <250>;
 257                         polling-delay = <2000>;
 258                         thermal-sensors = <&tmu 1>;
 259                         trips {
 260                                 soc_alert0: trip0 {
 261                                         temperature = <85000>;
 262                                         hysteresis = <2000>;
 263                                         type = "passive";
 264                                 };
 265
 266                                 soc_crit0: trip1 {
 267                                         temperature = <95000>;
 268                                         hysteresis = <2000>;
 269                                         type = "critical";
 270                                 };
 271                         };
 272
 273                         cooling-maps {
 274                                 map0 {
 275                                         trip = <&soc_alert0>;
 276                                         cooling-device =
 277                                                 <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 278                                                 <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 279                                                 <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 280                                                 <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 281                                 };
 282                         };
 283                 };
 284         };
 285
 286         timer {
 287                 compatible = "arm,armv8-timer";
 288                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 289                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 290                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 291                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 292                 clock-frequency = <8000000>;
 293                 arm,no-tick-in-suspend;
 294         };
 295
 296         soc@0 {
 297                 compatible = "fsl,imx8mp-soc", "simple-bus";
 298                 #address-cells = <1>;
 299                 #size-cells = <1>;
 300                 ranges = <0x0 0x0 0x0 0x3e000000>;
 301                 nvmem-cells = <&imx8mp_uid>;
 302                 nvmem-cell-names = "soc_unique_id";
 303
 304                 aips1: bus@30000000 {
 305                         compatible = "fsl,aips-bus", "simple-bus";
 306                         reg = <0x30000000 0x400000>;
 307                         #address-cells = <1>;
 308                         #size-cells = <1>;
 309                         ranges;
 310
 311                         gpio1: gpio@30200000 {
 312                                 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio";
 313                                 reg = <0x30200000 0x10000>;
 314                                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
 315                                              <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 316                                 clocks = <&clk IMX8MP_CLK_GPIO1_ROOT>;
 317                                 gpio-controller;
 318                                 #gpio-cells = <2>;
 319                                 interrupt-controller;
 320                                 #interrupt-cells = <2>;
 321                                 gpio-ranges = <&iomuxc 0 5 30>;
 322                         };
 323
 324                         gpio2: gpio@30210000 {
 325                                 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio";
 326                                 reg = <0x30210000 0x10000>;
 327                                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
 328                                              <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
 329                                 clocks = <&clk IMX8MP_CLK_GPIO2_ROOT>;
 330                                 gpio-controller;
 331                                 #gpio-cells = <2>;
 332                                 interrupt-controller;
 333                                 #interrupt-cells = <2>;
 334                                 gpio-ranges = <&iomuxc 0 35 21>;
 335                         };
 336
 337                         gpio3: gpio@30220000 {
 338                                 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio";
 339                                 reg = <0x30220000 0x10000>;
 340                                 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
 341                                              <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
 342                                 clocks = <&clk IMX8MP_CLK_GPIO3_ROOT>;
 343                                 gpio-controller;
 344                                 #gpio-cells = <2>;
 345                                 interrupt-controller;
 346                                 #interrupt-cells = <2>;
 347                                 gpio-ranges = <&iomuxc 0 56 26>, <&iomuxc 26 144 4>;
 348                         };
 349
 350                         gpio4: gpio@30230000 {
 351                                 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio";
 352                                 reg = <0x30230000 0x10000>;
 353                                 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
 354                                              <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 355                                 clocks = <&clk IMX8MP_CLK_GPIO4_ROOT>;
 356                                 gpio-controller;
 357                                 #gpio-cells = <2>;
 358                                 interrupt-controller;
 359                                 #interrupt-cells = <2>;
 360                                 gpio-ranges = <&iomuxc 0 82 32>;
 361                         };
 362
 363                         gpio5: gpio@30240000 {
 364                                 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio";
 365                                 reg = <0x30240000 0x10000>;
 366                                 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
 367                                              <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 368                                 clocks = <&clk IMX8MP_CLK_GPIO5_ROOT>;
 369                                 gpio-controller;
 370                                 #gpio-cells = <2>;
 371                                 interrupt-controller;
 372                                 #interrupt-cells = <2>;
 373                                 gpio-ranges = <&iomuxc 0 114 30>;
 374                         };
 375
 376                         tmu: tmu@30260000 {
 377                                 compatible = "fsl,imx8mp-tmu";
 378                                 reg = <0x30260000 0x10000>;
 379                                 clocks = <&clk IMX8MP_CLK_TSENSOR_ROOT>;
 380                                 #thermal-sensor-cells = <1>;
 381                         };
 382
 383                         wdog1: watchdog@30280000 {
 384                                 compatible = "fsl,imx8mp-wdt", "fsl,imx21-wdt";
 385                                 reg = <0x30280000 0x10000>;
 386                                 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
 387                                 clocks = <&clk IMX8MP_CLK_WDOG1_ROOT>;
 388                                 status = "disabled";
 389                         };
 390
 391                         wdog2: watchdog@30290000 {
 392                                 compatible = "fsl,imx8mp-wdt", "fsl,imx21-wdt";
 393                                 reg = <0x30290000 0x10000>;
 394                                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 395                                 clocks = <&clk IMX8MP_CLK_WDOG2_ROOT>;
 396                                 status = "disabled";
 397                         };
 398
 399                         wdog3: watchdog@302a0000 {
 400                                 compatible = "fsl,imx8mp-wdt", "fsl,imx21-wdt";
 401                                 reg = <0x302a0000 0x10000>;
 402                                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 403                                 clocks = <&clk IMX8MP_CLK_WDOG3_ROOT>;
 404                                 status = "disabled";
 405                         };
 406
 407                         iomuxc: pinctrl@30330000 {
 408                                 compatible = "fsl,imx8mp-iomuxc";
 409                                 reg = <0x30330000 0x10000>;
 410                         };
 411
 412                         gpr: iomuxc-gpr@30340000 {
 413                                 compatible = "fsl,imx8mp-iomuxc-gpr", "syscon";
 414                                 reg = <0x30340000 0x10000>;
 415                         };
 416
 417                         ocotp: efuse@30350000 {
 418                                 compatible = "fsl,imx8mp-ocotp", "fsl,imx8mm-ocotp", "syscon";
 419                                 reg = <0x30350000 0x10000>;
 420                                 clocks = <&clk IMX8MP_CLK_OCOTP_ROOT>;
 421                                 /* For nvmem subnodes */
 422                                 #address-cells = <1>;
 423                                 #size-cells = <1>;
 424
 425                                 imx8mp_uid: unique-id@420 {
 426                                         reg = <0x8 0x8>;
 427                                 };
 428
 429                                 cpu_speed_grade: speed-grade@10 {
 430                                         reg = <0x10 4>;
 431                                 };
 432
 433                                 eth_mac1: mac-address@90 {
 434                                         reg = <0x90 6>;
 435                                 };
 436
 437                                 eth_mac2: mac-address@96 {
 438                                         reg = <0x96 6>;
 439                                 };
 440                         };
 441
 442                         anatop: anatop@30360000 {
 443                                 compatible = "fsl,imx8mp-anatop", "fsl,imx8mm-anatop",
 444                                              "syscon";
 445                                 reg = <0x30360000 0x10000>;
 446                         };
 447
 448                         snvs: snvs@30370000 {
 449                                 compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd";
 450                                 reg = <0x30370000 0x10000>;
 451
 452                                 snvs_rtc: snvs-rtc-lp {
 453                                         compatible = "fsl,sec-v4.0-mon-rtc-lp";
 454                                         regmap =<&snvs>;
 455                                         offset = <0x34>;
 456                                         interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
 457                                                      <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 458                                         clocks = <&clk IMX8MP_CLK_SNVS_ROOT>;
 459                                         clock-names = "snvs-rtc";
 460                                 };
 461
 462                                 snvs_pwrkey: snvs-powerkey {
 463                                         compatible = "fsl,sec-v4.0-pwrkey";
 464                                         regmap = <&snvs>;
 465                                         interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 466                                         clocks = <&clk IMX8MP_CLK_SNVS_ROOT>;
 467                                         clock-names = "snvs-pwrkey";
 468                                         linux,keycode = <KEY_POWER>;
 469                                         wakeup-source;
 470                                         status = "disabled";
 471                                 };
 472                         };
 473
 474                         clk: clock-controller@30380000 {
 475                                 compatible = "fsl,imx8mp-ccm";
 476                                 reg = <0x30380000 0x10000>;
 477                                 #clock-cells = <1>;
 478                                 clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>,
 479                                          <&clk_ext3>, <&clk_ext4>;
 480                                 clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2",
 481                                               "clk_ext3", "clk_ext4";
 482                                 assigned-clocks = <&clk IMX8MP_CLK_A53_SRC>,
 483                                                   <&clk IMX8MP_CLK_A53_CORE>,
 484                                                   <&clk IMX8MP_CLK_NOC>,
 485                                                   <&clk IMX8MP_CLK_NOC_IO>,
 486                                                   <&clk IMX8MP_CLK_GIC>,
 487                                                   <&clk IMX8MP_CLK_AUDIO_AHB>,
 488                                                   <&clk IMX8MP_CLK_AUDIO_AXI_SRC>,
 489                                                   <&clk IMX8MP_AUDIO_PLL1>,
 490                                                   <&clk IMX8MP_AUDIO_PLL2>;
 491                                 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,
 492                                                          <&clk IMX8MP_ARM_PLL_OUT>,
 493                                                          <&clk IMX8MP_SYS_PLL2_1000M>,
 494                                                          <&clk IMX8MP_SYS_PLL1_800M>,
 495                                                          <&clk IMX8MP_SYS_PLL2_500M>,
 496                                                          <&clk IMX8MP_SYS_PLL1_800M>,
 497                                                          <&clk IMX8MP_SYS_PLL1_800M>;
 498                                 assigned-clock-rates = <0>, <0>,
 499                                                        <1000000000>,
 500                                                        <800000000>,
 501                                                        <500000000>,
 502                                                        <400000000>,
 503                                                        <800000000>,
 504                                                        <393216000>,
 505                                                        <361267200>;
 506                         };
 507
 508                         src: reset-controller@30390000 {
 509                                 compatible = "fsl,imx8mp-src", "syscon";
 510                                 reg = <0x30390000 0x10000>;
 511                                 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
 512                                 #reset-cells = <1>;
 513                         };
 514
 515                         gpc: gpc@303a0000 {
 516                                 compatible = "fsl,imx8mp-gpc";
 517                                 reg = <0x303a0000 0x1000>;
 518                                 interrupt-parent = <&gic>;
 519                                 interrupt-controller;
 520                                 #interrupt-cells = <3>;
 521
 522                                 pgc {
 523                                         #address-cells = <1>;
 524                                         #size-cells = <0>;
 525
 526                                         pgc_mipi_phy1: power-domain@0 {
 527                                                 #power-domain-cells = <0>;
 528                                                 reg = <IMX8MP_POWER_DOMAIN_MIPI_PHY1>;
 529                                         };
 530
 531                                         pgc_pcie_phy: power-domain@1 {
 532                                                 #power-domain-cells = <0>;
 533                                                 reg = <IMX8MP_POWER_DOMAIN_PCIE_PHY>;
 534                                         };
 535
 536                                         pgc_usb1_phy: power-domain@2 {
 537                                                 #power-domain-cells = <0>;
 538                                                 reg = <IMX8MP_POWER_DOMAIN_USB1_PHY>;
 539                                         };
 540
 541                                         pgc_usb2_phy: power-domain@3 {
 542                                                 #power-domain-cells = <0>;
 543                                                 reg = <IMX8MP_POWER_DOMAIN_USB2_PHY>;
 544                                         };
 545
 546                                         pgc_gpu2d: power-domain@6 {
 547                                                 #power-domain-cells = <0>;
 548                                                 reg = <IMX8MP_POWER_DOMAIN_GPU2D>;
 549                                                 clocks = <&clk IMX8MP_CLK_GPU2D_ROOT>;
 550                                                 power-domains = <&pgc_gpumix>;
 551                                         };
 552
 553                                         pgc_gpumix: power-domain@7 {
 554                                                 #power-domain-cells = <0>;
 555                                                 reg = <IMX8MP_POWER_DOMAIN_GPUMIX>;
 556                                                 clocks = <&clk IMX8MP_CLK_GPU_ROOT>,
 557                                                          <&clk IMX8MP_CLK_GPU_AHB>;
 558                                                 assigned-clocks = <&clk IMX8MP_CLK_GPU_AXI>,
 559                                                                   <&clk IMX8MP_CLK_GPU_AHB>;
 560                                                 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,
 561                                                                          <&clk IMX8MP_SYS_PLL1_800M>;
 562                                                 assigned-clock-rates = <800000000>, <400000000>;
 563                                         };
 564
 565                                         pgc_gpu3d: power-domain@9 {
 566                                                 #power-domain-cells = <0>;
 567                                                 reg = <IMX8MP_POWER_DOMAIN_GPU3D>;
 568                                                 clocks = <&clk IMX8MP_CLK_GPU3D_ROOT>,
 569                                                          <&clk IMX8MP_CLK_GPU3D_SHADER_CORE>;
 570                                                 power-domains = <&pgc_gpumix>;
 571                                         };
 572
 573                                         pgc_mediamix: power-domain@10 {
 574                                                 #power-domain-cells = <0>;
 575                                                 reg = <IMX8MP_POWER_DOMAIN_MEDIAMIX>;
 576                                                 clocks = <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>,
 577                                                          <&clk IMX8MP_CLK_MEDIA_APB_ROOT>;
 578                                         };
 579
 580                                         pgc_mipi_phy2: power-domain@16 {
 581                                                 #power-domain-cells = <0>;
 582                                                 reg = <IMX8MP_POWER_DOMAIN_MIPI_PHY2>;
 583                                         };
 584
 585                                         pgc_hsiomix: power-domains@17 {
 586                                                 #power-domain-cells = <0>;
 587                                                 reg = <IMX8MP_POWER_DOMAIN_HSIOMIX>;
 588                                                 clocks = <&clk IMX8MP_CLK_HSIO_AXI>,
 589                                                          <&clk IMX8MP_CLK_HSIO_ROOT>;
 590                                                 assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>;
 591                                                 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>;
 592                                                 assigned-clock-rates = <500000000>;
 593                                         };
 594
 595                                         pgc_ispdwp: power-domain@18 {
 596                                                 #power-domain-cells = <0>;
 597                                                 reg = <IMX8MP_POWER_DOMAIN_MEDIAMIX_ISPDWP>;
 598                                                 clocks = <&clk IMX8MP_CLK_MEDIA_ISP_ROOT>;
 599                                         };
 600                                 };
 601                         };
 602                 };
 603
 604                 aips2: bus@30400000 {
 605                         compatible = "fsl,aips-bus", "simple-bus";
 606                         reg = <0x30400000 0x400000>;
 607                         #address-cells = <1>;
 608                         #size-cells = <1>;
 609                         ranges;
 610
 611                         pwm1: pwm@30660000 {
 612                                 compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm";
 613                                 reg = <0x30660000 0x10000>;
 614                                 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
 615                                 clocks = <&clk IMX8MP_CLK_PWM1_ROOT>,
 616                                          <&clk IMX8MP_CLK_PWM1_ROOT>;
 617                                 clock-names = "ipg", "per";
 618                                 #pwm-cells = <3>;
 619                                 status = "disabled";
 620                         };
 621
 622                         pwm2: pwm@30670000 {
 623                                 compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm";
 624                                 reg = <0x30670000 0x10000>;
 625                                 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 626                                 clocks = <&clk IMX8MP_CLK_PWM2_ROOT>,
 627                                          <&clk IMX8MP_CLK_PWM2_ROOT>;
 628                                 clock-names = "ipg", "per";
 629                                 #pwm-cells = <3>;
 630                                 status = "disabled";
 631                         };
 632
 633                         pwm3: pwm@30680000 {
 634                                 compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm";
 635                                 reg = <0x30680000 0x10000>;
 636                                 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 637                                 clocks = <&clk IMX8MP_CLK_PWM3_ROOT>,
 638                                          <&clk IMX8MP_CLK_PWM3_ROOT>;
 639                                 clock-names = "ipg", "per";
 640                                 #pwm-cells = <3>;
 641                                 status = "disabled";
 642                         };
 643
 644                         pwm4: pwm@30690000 {
 645                                 compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm";
 646                                 reg = <0x30690000 0x10000>;
 647                                 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 648                                 clocks = <&clk IMX8MP_CLK_PWM4_ROOT>,
 649                                          <&clk IMX8MP_CLK_PWM4_ROOT>;
 650                                 clock-names = "ipg", "per";
 651                                 #pwm-cells = <3>;
 652                                 status = "disabled";
 653                         };
 654
 655                         system_counter: timer@306a0000 {
 656                                 compatible = "nxp,sysctr-timer";
 657                                 reg = <0x306a0000 0x20000>;
 658                                 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
 659                                 clocks = <&osc_24m>;
 660                                 clock-names = "per";
 661                         };
 662                 };
 663
 664                 aips3: bus@30800000 {
 665                         compatible = "fsl,aips-bus", "simple-bus";
 666                         reg = <0x30800000 0x400000>;
 667                         #address-cells = <1>;
 668                         #size-cells = <1>;
 669                         ranges;
 670
 671                         ecspi1: spi@30820000 {
 672                                 #address-cells = <1>;
 673                                 #size-cells = <0>;
 674                                 compatible = "fsl,imx8mp-ecspi", "fsl,imx51-ecspi";
 675                                 reg = <0x30820000 0x10000>;
 676                                 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 677                                 clocks = <&clk IMX8MP_CLK_ECSPI1_ROOT>,
 678                                          <&clk IMX8MP_CLK_ECSPI1_ROOT>;
 679                                 clock-names = "ipg", "per";
 680                                 dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>;
 681                                 dma-names = "rx", "tx";
 682                                 status = "disabled";
 683                         };
 684
 685                         ecspi2: spi@30830000 {
 686                                 #address-cells = <1>;
 687                                 #size-cells = <0>;
 688                                 compatible = "fsl,imx8mp-ecspi", "fsl,imx51-ecspi";
 689                                 reg = <0x30830000 0x10000>;
 690                                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 691                                 clocks = <&clk IMX8MP_CLK_ECSPI2_ROOT>,
 692                                          <&clk IMX8MP_CLK_ECSPI2_ROOT>;
 693                                 clock-names = "ipg", "per";
 694                                 dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>;
 695                                 dma-names = "rx", "tx";
 696                                 status = "disabled";
 697                         };
 698
 699                         ecspi3: spi@30840000 {
 700                                 #address-cells = <1>;
 701                                 #size-cells = <0>;
 702                                 compatible = "fsl,imx8mp-ecspi", "fsl,imx51-ecspi";
 703                                 reg = <0x30840000 0x10000>;
 704                                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 705                                 clocks = <&clk IMX8MP_CLK_ECSPI3_ROOT>,
 706                                          <&clk IMX8MP_CLK_ECSPI3_ROOT>;
 707                                 clock-names = "ipg", "per";
 708                                 dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>;
 709                                 dma-names = "rx", "tx";
 710                                 status = "disabled";
 711                         };
 712
 713                         uart1: serial@30860000 {
 714                                 compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";
 715                                 reg = <0x30860000 0x10000>;
 716                                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 717                                 clocks = <&clk IMX8MP_CLK_UART1_ROOT>,
 718                                          <&clk IMX8MP_CLK_UART1_ROOT>;
 719                                 clock-names = "ipg", "per";
 720                                 dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>;
 721                                 dma-names = "rx", "tx";
 722                                 status = "disabled";
 723                         };
 724
 725                         uart3: serial@30880000 {
 726                                 compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";
 727                                 reg = <0x30880000 0x10000>;
 728                                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 729                                 clocks = <&clk IMX8MP_CLK_UART3_ROOT>,
 730                                          <&clk IMX8MP_CLK_UART3_ROOT>;
 731                                 clock-names = "ipg", "per";
 732                                 dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>;
 733                                 dma-names = "rx", "tx";
 734                                 status = "disabled";
 735                         };
 736
 737                         uart2: serial@30890000 {
 738                                 compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";
 739                                 reg = <0x30890000 0x10000>;
 740                                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 741                                 clocks = <&clk IMX8MP_CLK_UART2_ROOT>,
 742                                          <&clk IMX8MP_CLK_UART2_ROOT>;
 743                                 clock-names = "ipg", "per";
 744                                 dmas = <&sdma1 24 4 0>, <&sdma1 25 4 0>;
 745                                 dma-names = "rx", "tx";
 746                                 status = "disabled";
 747                         };
 748
 749                         flexcan1: can@308c0000 {
 750                                 compatible = "fsl,imx8mp-flexcan";
 751                                 reg = <0x308c0000 0x10000>;
 752                                 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
 753                                 clocks = <&clk IMX8MP_CLK_IPG_ROOT>,
 754                                          <&clk IMX8MP_CLK_CAN1_ROOT>;
 755                                 clock-names = "ipg", "per";
 756                                 assigned-clocks = <&clk IMX8MP_CLK_CAN1>;
 757                                 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_40M>;
 758                                 assigned-clock-rates = <40000000>;
 759                                 fsl,clk-source = /bits/ 8 <0>;
 760                                 fsl,stop-mode = <&gpr 0x10 4>;
 761                                 status = "disabled";
 762                         };
 763
 764                         flexcan2: can@308d0000 {
 765                                 compatible = "fsl,imx8mp-flexcan";
 766                                 reg = <0x308d0000 0x10000>;
 767                                 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
 768                                 clocks = <&clk IMX8MP_CLK_IPG_ROOT>,
 769                                          <&clk IMX8MP_CLK_CAN2_ROOT>;
 770                                 clock-names = "ipg", "per";
 771                                 assigned-clocks = <&clk IMX8MP_CLK_CAN2>;
 772                                 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_40M>;
 773                                 assigned-clock-rates = <40000000>;
 774                                 fsl,clk-source = /bits/ 8 <0>;
 775                                 fsl,stop-mode = <&gpr 0x10 5>;
 776                                 status = "disabled";
 777                         };
 778
 779                         crypto: crypto@30900000 {
 780                                 compatible = "fsl,sec-v4.0";
 781                                 #address-cells = <1>;
 782                                 #size-cells = <1>;
 783                                 reg = <0x30900000 0x40000>;
 784                                 ranges = <0 0x30900000 0x40000>;
 785                                 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
 786                                 clocks = <&clk IMX8MP_CLK_AHB>,
 787                                          <&clk IMX8MP_CLK_IPG_ROOT>;
 788                                 clock-names = "aclk", "ipg";
 789
 790                                 sec_jr0: jr@1000 {
 791                                         compatible = "fsl,sec-v4.0-job-ring";
 792                                         reg = <0x1000 0x1000>;
 793                                         interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
 794                                 };
 795
 796                                 sec_jr1: jr@2000 {
 797                                         compatible = "fsl,sec-v4.0-job-ring";
 798                                         reg = <0x2000 0x1000>;
 799                                         interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
 800                                 };
 801
 802                                 sec_jr2: jr@3000 {
 803                                         compatible = "fsl,sec-v4.0-job-ring";
 804                                         reg = <0x3000 0x1000>;
 805                                         interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
 806                                 };
 807                         };
 808
 809                         i2c1: i2c@30a20000 {
 810                                 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
 811                                 #address-cells = <1>;
 812                                 #size-cells = <0>;
 813                                 reg = <0x30a20000 0x10000>;
 814                                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 815                                 clocks = <&clk IMX8MP_CLK_I2C1_ROOT>;
 816                                 status = "disabled";
 817                         };
 818
 819                         i2c2: i2c@30a30000 {
 820                                 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
 821                                 #address-cells = <1>;
 822                                 #size-cells = <0>;
 823                                 reg = <0x30a30000 0x10000>;
 824                                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 825                                 clocks = <&clk IMX8MP_CLK_I2C2_ROOT>;
 826                                 status = "disabled";
 827                         };
 828
 829                         i2c3: i2c@30a40000 {
 830                                 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
 831                                 #address-cells = <1>;
 832                                 #size-cells = <0>;
 833                                 reg = <0x30a40000 0x10000>;
 834                                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 835                                 clocks = <&clk IMX8MP_CLK_I2C3_ROOT>;
 836                                 status = "disabled";
 837                         };
 838
 839                         i2c4: i2c@30a50000 {
 840                                 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
 841                                 #address-cells = <1>;
 842                                 #size-cells = <0>;
 843                                 reg = <0x30a50000 0x10000>;
 844                                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 845                                 clocks = <&clk IMX8MP_CLK_I2C4_ROOT>;
 846                                 status = "disabled";
 847                         };
 848
 849                         uart4: serial@30a60000 {
 850                                 compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";
 851                                 reg = <0x30a60000 0x10000>;
 852                                 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 853                                 clocks = <&clk IMX8MP_CLK_UART4_ROOT>,
 854                                          <&clk IMX8MP_CLK_UART4_ROOT>;
 855                                 clock-names = "ipg", "per";
 856                                 dmas = <&sdma1 28 4 0>, <&sdma1 29 4 0>;
 857                                 dma-names = "rx", "tx";
 858                                 status = "disabled";
 859                         };
 860
 861                         mu: mailbox@30aa0000 {
 862                                 compatible = "fsl,imx8mp-mu", "fsl,imx6sx-mu";
 863                                 reg = <0x30aa0000 0x10000>;
 864                                 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
 865                                 clocks = <&clk IMX8MP_CLK_MU_ROOT>;
 866                                 #mbox-cells = <2>;
 867                         };
 868
 869                         mu2: mailbox@30e60000 {
 870                                 compatible = "fsl,imx8mp-mu", "fsl,imx6sx-mu";
 871                                 reg = <0x30e60000 0x10000>;
 872                                 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
 873                                 #mbox-cells = <2>;
 874                                 status = "disabled";
 875                         };
 876
 877                         i2c5: i2c@30ad0000 {
 878                                 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
 879                                 #address-cells = <1>;
 880                                 #size-cells = <0>;
 881                                 reg = <0x30ad0000 0x10000>;
 882                                 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
 883                                 clocks = <&clk IMX8MP_CLK_I2C5_ROOT>;
 884                                 status = "disabled";
 885                         };
 886
 887                         i2c6: i2c@30ae0000 {
 888                                 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
 889                                 #address-cells = <1>;
 890                                 #size-cells = <0>;
 891                                 reg = <0x30ae0000 0x10000>;
 892                                 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
 893                                 clocks = <&clk IMX8MP_CLK_I2C6_ROOT>;
 894                                 status = "disabled";
 895                         };
 896
 897                         usdhc1: mmc@30b40000 {
 898                                 compatible = "fsl,imx8mp-usdhc", "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
 899                                 reg = <0x30b40000 0x10000>;
 900                                 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
 901                                 clocks = <&clk IMX8MP_CLK_DUMMY>,
 902                                          <&clk IMX8MP_CLK_NAND_USDHC_BUS>,
 903                                          <&clk IMX8MP_CLK_USDHC1_ROOT>;
 904                                 clock-names = "ipg", "ahb", "per";
 905                                 fsl,tuning-start-tap = <20>;
 906                                 fsl,tuning-step= <2>;
 907                                 bus-width = <4>;
 908                                 status = "disabled";
 909                         };
 910
 911                         usdhc2: mmc@30b50000 {
 912                                 compatible = "fsl,imx8mp-usdhc", "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
 913                                 reg = <0x30b50000 0x10000>;
 914                                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 915                                 clocks = <&clk IMX8MP_CLK_DUMMY>,
 916                                          <&clk IMX8MP_CLK_NAND_USDHC_BUS>,
 917                                          <&clk IMX8MP_CLK_USDHC2_ROOT>;
 918                                 clock-names = "ipg", "ahb", "per";
 919                                 fsl,tuning-start-tap = <20>;
 920                                 fsl,tuning-step= <2>;
 921                                 bus-width = <4>;
 922                                 status = "disabled";
 923                         };
 924
 925                         usdhc3: mmc@30b60000 {
 926                                 compatible = "fsl,imx8mp-usdhc", "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
 927                                 reg = <0x30b60000 0x10000>;
 928                                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 929                                 clocks = <&clk IMX8MP_CLK_DUMMY>,
 930                                          <&clk IMX8MP_CLK_NAND_USDHC_BUS>,
 931                                          <&clk IMX8MP_CLK_USDHC3_ROOT>;
 932                                 clock-names = "ipg", "ahb", "per";
 933                                 fsl,tuning-start-tap = <20>;
 934                                 fsl,tuning-step= <2>;
 935                                 bus-width = <4>;
 936                                 status = "disabled";
 937                         };
 938
 939                         flexspi: spi@30bb0000 {
 940                                 compatible = "nxp,imx8mp-fspi";
 941                                 reg = <0x30bb0000 0x10000>, <0x8000000 0x10000000>;
 942                                 reg-names = "fspi_base", "fspi_mmap";
 943                                 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
 944                                 clocks = <&clk IMX8MP_CLK_QSPI_ROOT>,
 945                                          <&clk IMX8MP_CLK_QSPI_ROOT>;
 946                                 clock-names = "fspi_en", "fspi";
 947                                 assigned-clock-rates = <80000000>;
 948                                 assigned-clocks = <&clk IMX8MP_CLK_QSPI>;
 949                                 #address-cells = <1>;
 950                                 #size-cells = <0>;
 951                                 status = "disabled";
 952                         };
 953
 954                         sdma1: dma-controller@30bd0000 {
 955                                 compatible = "fsl,imx8mp-sdma", "fsl,imx8mq-sdma";
 956                                 reg = <0x30bd0000 0x10000>;
 957                                 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
 958                                 clocks = <&clk IMX8MP_CLK_SDMA1_ROOT>,
 959                                          <&clk IMX8MP_CLK_AHB>;
 960                                 clock-names = "ipg", "ahb";
 961                                 #dma-cells = <3>;
 962                                 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
 963                         };
 964
 965                         fec: ethernet@30be0000 {
 966                                 compatible = "fsl,imx8mp-fec", "fsl,imx8mq-fec", "fsl,imx6sx-fec";
 967                                 reg = <0x30be0000 0x10000>;
 968                                 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
 969                                              <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
 970                                              <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
 971                                              <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
 972                                 clocks = <&clk IMX8MP_CLK_ENET1_ROOT>,
 973                                          <&clk IMX8MP_CLK_SIM_ENET_ROOT>,
 974                                          <&clk IMX8MP_CLK_ENET_TIMER>,
 975                                          <&clk IMX8MP_CLK_ENET_REF>,
 976                                          <&clk IMX8MP_CLK_ENET_PHY_REF>;
 977                                 clock-names = "ipg", "ahb", "ptp",
 978                                               "enet_clk_ref", "enet_out";
 979                                 assigned-clocks = <&clk IMX8MP_CLK_ENET_AXI>,
 980                                                   <&clk IMX8MP_CLK_ENET_TIMER>,
 981                                                   <&clk IMX8MP_CLK_ENET_REF>,
 982                                                   <&clk IMX8MP_CLK_ENET_PHY_REF>;
 983                                 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>,
 984                                                          <&clk IMX8MP_SYS_PLL2_100M>,
 985                                                          <&clk IMX8MP_SYS_PLL2_125M>,
 986                                                          <&clk IMX8MP_SYS_PLL2_50M>;
 987                                 assigned-clock-rates = <0>, <100000000>, <125000000>, <0>;
 988                                 fsl,num-tx-queues = <3>;
 989                                 fsl,num-rx-queues = <3>;
 990                                 nvmem-cells = <&eth_mac1>;
 991                                 nvmem-cell-names = "mac-address";
 992                                 fsl,stop-mode = <&gpr 0x10 3>;
 993                                 status = "disabled";
 994                         };
 995
 996                         eqos: ethernet@30bf0000 {
 997                                 compatible = "nxp,imx8mp-dwmac-eqos", "snps,dwmac-5.10a";
 998                                 reg = <0x30bf0000 0x10000>;
 999                                 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
1000                                              <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
1001                                 interrupt-names = "macirq", "eth_wake_irq";
1002                                 clocks = <&clk IMX8MP_CLK_ENET_QOS_ROOT>,
1003                                          <&clk IMX8MP_CLK_QOS_ENET_ROOT>,
1004                                          <&clk IMX8MP_CLK_ENET_QOS_TIMER>,
1005                                          <&clk IMX8MP_CLK_ENET_QOS>;
1006                                 clock-names = "stmmaceth", "pclk", "ptp_ref", "tx";
1007                                 assigned-clocks = <&clk IMX8MP_CLK_ENET_AXI>,
1008                                                   <&clk IMX8MP_CLK_ENET_QOS_TIMER>,
1009                                                   <&clk IMX8MP_CLK_ENET_QOS>;
1010                                 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>,
1011                                                          <&clk IMX8MP_SYS_PLL2_100M>,
1012                                                          <&clk IMX8MP_SYS_PLL2_125M>;
1013                                 assigned-clock-rates = <0>, <100000000>, <125000000>;
1014                                 nvmem-cells = <&eth_mac2>;
1015                                 nvmem-cell-names = "mac-address";
1016                                 intf_mode = <&gpr 0x4>;
1017                                 status = "disabled";
1018                         };
1019                 };
1020
1021                 aips4: bus@32c00000 {
1022                         compatible = "fsl,aips-bus", "simple-bus";
1023                         reg = <0x32c00000 0x400000>;
1024                         #address-cells = <1>;
1025                         #size-cells = <1>;
1026                         ranges;
1027
1028                         media_blk_ctrl: blk-ctrl@32ec0000 {
1029                                 compatible = "fsl,imx8mp-media-blk-ctrl",
1030                                              "syscon";
1031                                 reg = <0x32ec0000 0x10000>;
1032                                 power-domains = <&pgc_mediamix>,
1033                                                 <&pgc_mipi_phy1>,
1034                                                 <&pgc_mipi_phy1>,
1035                                                 <&pgc_mediamix>,
1036                                                 <&pgc_mediamix>,
1037                                                 <&pgc_mipi_phy2>,
1038                                                 <&pgc_mediamix>,
1039                                                 <&pgc_ispdwp>,
1040                                                 <&pgc_ispdwp>,
1041                                                 <&pgc_mipi_phy2>;
1042                                 power-domain-names = "bus", "mipi-dsi1", "mipi-csi1",
1043                                                      "lcdif1", "isi", "mipi-csi2",
1044                                                      "lcdif2", "isp", "dwe",
1045                                                      "mipi-dsi2";
1046                                 clocks = <&clk IMX8MP_CLK_MEDIA_APB_ROOT>,
1047                                          <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>,
1048                                          <&clk IMX8MP_CLK_MEDIA_CAM1_PIX_ROOT>,
1049                                          <&clk IMX8MP_CLK_MEDIA_CAM2_PIX_ROOT>,
1050                                          <&clk IMX8MP_CLK_MEDIA_DISP1_PIX_ROOT>,
1051                                          <&clk IMX8MP_CLK_MEDIA_DISP2_PIX_ROOT>,
1052                                          <&clk IMX8MP_CLK_MEDIA_ISP_ROOT>,
1053                                          <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF_ROOT>;
1054                                 clock-names = "apb", "axi", "cam1", "cam2",
1055                                               "disp1", "disp2", "isp", "phy";
1056
1057                                 assigned-clocks = <&clk IMX8MP_CLK_MEDIA_AXI>,
1058                                                   <&clk IMX8MP_CLK_MEDIA_APB>;
1059                                 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>,
1060                                                          <&clk IMX8MP_SYS_PLL1_800M>;
1061                                 assigned-clock-rates = <500000000>, <200000000>;
1062
1063                                 #power-domain-cells = <1>;
1064                         };
1065
1066                         hsio_blk_ctrl: blk-ctrl@32f10000 {
1067                                 compatible = "fsl,imx8mp-hsio-blk-ctrl", "syscon";
1068                                 reg = <0x32f10000 0x24>;
1069                                 clocks = <&clk IMX8MP_CLK_USB_ROOT>,
1070                                          <&clk IMX8MP_CLK_PCIE_ROOT>;
1071                                 clock-names = "usb", "pcie";
1072                                 power-domains = <&pgc_hsiomix>, <&pgc_hsiomix>,
1073                                                 <&pgc_usb1_phy>, <&pgc_usb2_phy>,
1074                                                 <&pgc_hsiomix>, <&pgc_pcie_phy>;
1075                                 power-domain-names = "bus", "usb", "usb-phy1",
1076                                                      "usb-phy2", "pcie", "pcie-phy";
1077                                 #power-domain-cells = <1>;
1078                         };
1079                 };
1080
1081                 gpu3d: gpu@38000000 {
1082                         compatible = "vivante,gc";
1083                         reg = <0x38000000 0x8000>;
1084                         interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
1085                         clocks = <&clk IMX8MP_CLK_GPU3D_ROOT>,
1086                                  <&clk IMX8MP_CLK_GPU3D_SHADER_CORE>,
1087                                  <&clk IMX8MP_CLK_GPU_ROOT>,
1088                                  <&clk IMX8MP_CLK_GPU_AHB>;
1089                         clock-names = "core", "shader", "bus", "reg";
1090                         assigned-clocks = <&clk IMX8MP_CLK_GPU3D_CORE>,
1091                                           <&clk IMX8MP_CLK_GPU3D_SHADER_CORE>;
1092                         assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,
1093                                                  <&clk IMX8MP_SYS_PLL1_800M>;
1094                         assigned-clock-rates = <800000000>, <800000000>;
1095                         power-domains = <&pgc_gpu3d>;
1096                 };
1097
1098                 gpu2d: gpu@38008000 {
1099                         compatible = "vivante,gc";
1100                         reg = <0x38008000 0x8000>;
1101                         interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
1102                         clocks = <&clk IMX8MP_CLK_GPU2D_ROOT>,
1103                                  <&clk IMX8MP_CLK_GPU_ROOT>,
1104                                  <&clk IMX8MP_CLK_GPU_AHB>;
1105                         clock-names = "core", "bus", "reg";
1106                         assigned-clocks = <&clk IMX8MP_CLK_GPU2D_CORE>;
1107                         assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>;
1108                         assigned-clock-rates = <800000000>;
1109                         power-domains = <&pgc_gpu2d>;
1110                 };
1111
1112                 gic: interrupt-controller@38800000 {
1113                         compatible = "arm,gic-v3";
1114                         reg = <0x38800000 0x10000>,
1115                               <0x38880000 0xc0000>;
1116                         #interrupt-cells = <3>;
1117                         interrupt-controller;
1118                         interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
1119                         interrupt-parent = <&gic>;
1120                 };
1121
1122                 edacmc: memory-controller@3d400000 {
1123                         compatible = "snps,ddrc-3.80a";
1124                         reg = <0x3d400000 0x400000>;
1125                         interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
1126                 };
1127
1128                 ddr-pmu@3d800000 {
1129                         compatible = "fsl,imx8mp-ddr-pmu", "fsl,imx8m-ddr-pmu";
1130                         reg = <0x3d800000 0x400000>;
1131                         interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1132                 };
1133
1134                 usb3_phy0: usb-phy@381f0040 {
1135                         compatible = "fsl,imx8mp-usb-phy";
1136                         reg = <0x381f0040 0x40>;
1137                         clocks = <&clk IMX8MP_CLK_USB_PHY_ROOT>;
1138                         clock-names = "phy";
1139                         assigned-clocks = <&clk IMX8MP_CLK_USB_PHY_REF>;
1140                         assigned-clock-parents = <&clk IMX8MP_CLK_24M>;
1141                         power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB_PHY1>;
1142                         #phy-cells = <0>;
1143                         status = "disabled";
1144                 };
1145
1146                 usb3_0: usb@32f10100 {
1147                         compatible = "fsl,imx8mp-dwc3";
1148                         reg = <0x32f10100 0x8>,
1149                               <0x381f0000 0x20>;
1150                         clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,
1151                                  <&clk IMX8MP_CLK_USB_ROOT>;
1152                         clock-names = "hsio", "suspend";
1153                         interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
1154                         power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB>;
1155                         #address-cells = <1>;
1156                         #size-cells = <1>;
1157                         dma-ranges = <0x40000000 0x40000000 0xc0000000>;
1158                         ranges;
1159                         status = "disabled";
1160
1161                         usb_dwc3_0: usb@38100000 {
1162                                 compatible = "snps,dwc3";
1163                                 reg = <0x38100000 0x10000>;
1164                                 clocks = <&clk IMX8MP_CLK_HSIO_AXI>,
1165                                          <&clk IMX8MP_CLK_USB_CORE_REF>,
1166                                          <&clk IMX8MP_CLK_USB_ROOT>;
1167                                 clock-names = "bus_early", "ref", "suspend";
1168                                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
1169                                 phys = <&usb3_phy0>, <&usb3_phy0>;
1170                                 phy-names = "usb2-phy", "usb3-phy";
1171                                 snps,dis-u2-freeclk-exists-quirk;
1172                         };
1173
1174                 };
1175
1176                 usb3_phy1: usb-phy@382f0040 {
1177                         compatible = "fsl,imx8mp-usb-phy";
1178                         reg = <0x382f0040 0x40>;
1179                         clocks = <&clk IMX8MP_CLK_USB_PHY_ROOT>;
1180                         clock-names = "phy";
1181                         assigned-clocks = <&clk IMX8MP_CLK_USB_PHY_REF>;
1182                         assigned-clock-parents = <&clk IMX8MP_CLK_24M>;
1183                         power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB_PHY2>;
1184                         #phy-cells = <0>;
1185                         status = "disabled";
1186                 };
1187
1188                 usb3_1: usb@32f10108 {
1189                         compatible = "fsl,imx8mp-dwc3";
1190                         reg = <0x32f10108 0x8>,
1191                               <0x382f0000 0x20>;
1192                         clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,
1193                                  <&clk IMX8MP_CLK_USB_ROOT>;
1194                         clock-names = "hsio", "suspend";
1195                         interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
1196                         power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB>;
1197                         #address-cells = <1>;
1198                         #size-cells = <1>;
1199                         dma-ranges = <0x40000000 0x40000000 0xc0000000>;
1200                         ranges;
1201                         status = "disabled";
1202
1203                         usb_dwc3_1: usb@38200000 {
1204                                 compatible = "snps,dwc3";
1205                                 reg = <0x38200000 0x10000>;
1206                                 clocks = <&clk IMX8MP_CLK_HSIO_AXI>,
1207                                          <&clk IMX8MP_CLK_USB_CORE_REF>,
1208                                          <&clk IMX8MP_CLK_USB_ROOT>;
1209                                 clock-names = "bus_early", "ref", "suspend";
1210                                 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
1211                                 phys = <&usb3_phy1>, <&usb3_phy1>;
1212                                 phy-names = "usb2-phy", "usb3-phy";
1213                                 snps,dis-u2-freeclk-exists-quirk;
1214                         };
1215                 };
1216
1217                 dsp: dsp@3b6e8000 {
1218                         compatible = "fsl,imx8mp-dsp";
1219                         reg = <0x3b6e8000 0x88000>;
1220                         mbox-names = "txdb0", "txdb1",
1221                                 "rxdb0", "rxdb1";
1222                         mboxes = <&mu2 2 0>, <&mu2 2 1>,
1223                                 <&mu2 3 0>, <&mu2 3 1>;
1224                         memory-region = <&dsp_reserved>;
1225                         status = "disabled";
1226                 };
1227         };
1228 };