arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) 2020 PHYTEC Messtechnik GmbH
   4  * Author: Teresa Remmet <t.remmet@phytec.de>
   5  */
   6
   7 /dts-v1/;
   8
   9 #include <dt-bindings/leds/leds-pca9532.h>
  10 #include <dt-bindings/pwm/pwm.h>
  11 #include "imx8mp-phycore-som.dtsi"
  12
  13 / {
  14         model = "PHYTEC phyBOARD-Pollux i.MX8MP";
  15         compatible = "phytec,imx8mp-phyboard-pollux-rdk",
  16                      "phytec,imx8mp-phycore-som", "fsl,imx8mp";
  17
  18         chosen {
  19                 stdout-path = &uart1;
  20         };
  21
  22         reg_usdhc2_vmmc: regulator-usdhc2 {
  23                 compatible = "regulator-fixed";
  24                 pinctrl-names = "default";
  25                 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
  26                 regulator-name = "VSD_3V3";
  27                 regulator-min-microvolt = <3300000>;
  28                 regulator-max-microvolt = <3300000>;
  29                 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
  30                 enable-active-high;
  31                 startup-delay-us = <100>;
  32                 off-on-delay-us = <12000>;
  33         };
  34 };
  35
  36 &eqos {
  37         pinctrl-names = "default";
  38         pinctrl-0 = <&pinctrl_eqos>;
  39         phy-mode = "rgmii-id";
  40         phy-handle = <&ethphy0>;
  41         status = "okay";
  42
  43         mdio {
  44                 compatible = "snps,dwmac-mdio";
  45                 #address-cells = <1>;
  46                 #size-cells = <0>;
  47
  48                 ethphy0: ethernet-phy@1 {
  49                         compatible = "ethernet-phy-ieee802.3-c22";
  50                         reg = <0x1>;
  51                         ti,rx-internal-delay = <DP83867_RGMIIDCTL_1_50_NS>;
  52                         ti,tx-internal-delay = <DP83867_RGMIIDCTL_1_50_NS>;
  53                         ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
  54                         ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
  55                         enet-phy-lane-no-swap;
  56                 };
  57         };
  58 };
  59
  60 &i2c2 {
  61         clock-frequency = <400000>;
  62         pinctrl-names = "default", "gpio";
  63         pinctrl-0 = <&pinctrl_i2c2>;
  64         pinctrl-1 = <&pinctrl_i2c2_gpio>;
  65         sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
  66         scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
  67         status = "okay";
  68
  69         eeprom@51 {
  70                 compatible = "atmel,24c02";
  71                 reg = <0x51>;
  72                 pagesize = <16>;
  73         };
  74
  75         leds@62 {
  76                 compatible = "nxp,pca9533";
  77                 reg = <0x62>;
  78
  79                 led1 {
  80                         type = <PCA9532_TYPE_LED>;
  81                 };
  82
  83                 led2 {
  84                         type = <PCA9532_TYPE_LED>;
  85                 };
  86
  87                 led3 {
  88                         type = <PCA9532_TYPE_LED>;
  89                 };
  90         };
  91 };
  92
  93 &snvs_pwrkey {
  94         status = "okay";
  95 };
  96
  97 /* debug console */
  98 &uart1 {
  99         pinctrl-names = "default";
 100         pinctrl-0 = <&pinctrl_uart1>;
 101         status = "okay";
 102 };
 103
 104 /* SD-Card */
 105 &usdhc2 {
 106         pinctrl-names = "default", "state_100mhz", "state_200mhz";
 107         pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_pins>;
 108         pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_pins>;
 109         pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_pins>;
 110         cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
 111         vmmc-supply = <&reg_usdhc2_vmmc>;
 112         bus-width = <4>;
 113         status = "okay";
 114 };
 115
 116 &iomuxc {
 117         pinctrl_eqos: eqosgrp {
 118                 fsl,pins = <
 119                         MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC                     0x3
 120                         MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO                   0x3
 121                         MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0               0x91
 122                         MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1               0x91
 123                         MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2               0x91
 124                         MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3               0x91
 125                         MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK       0x91
 126                         MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL         0x91
 127                         MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0               0x1f
 128                         MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1               0x1f
 129                         MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2               0x1f
 130                         MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3               0x1f
 131                         MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL         0x1f
 132                         MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK       0x1f
 133                         MX8MP_IOMUXC_SAI1_MCLK__GPIO4_IO20                      0x10
 134                 >;
 135         };
 136
 137         pinctrl_i2c2: i2c2grp {
 138                 fsl,pins = <
 139                         MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL         0x400001c3
 140                         MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA         0x400001c3
 141                 >;
 142         };
 143
 144         pinctrl_i2c2_gpio: i2c2gpiogrp {
 145                 fsl,pins = <
 146                         MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16       0x1e3
 147                         MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17       0x1e3
 148                 >;
 149         };
 150
 151         pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
 152                 fsl,pins = <
 153                         MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19    0x41
 154                 >;
 155         };
 156
 157         pinctrl_uart1: uart1grp {
 158                 fsl,pins = <
 159                         MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX    0x49
 160                         MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX    0x49
 161                 >;
 162         };
 163
 164         pinctrl_usdhc2_pins: usdhc2-gpiogrp {
 165                 fsl,pins = <
 166                         MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12       0x1c4
 167                 >;
 168         };
 169
 170         pinctrl_usdhc2: usdhc2grp {
 171                 fsl,pins = <
 172                         MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK        0x190
 173                         MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD        0x1d0
 174                         MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0    0x1d0
 175                         MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1    0x1d0
 176                         MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2    0x1d0
 177                         MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3    0x1d0
 178                         MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
 179                 >;
 180         };
 181
 182         pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
 183                 fsl,pins = <
 184                         MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK        0x194
 185                         MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD        0x1d4
 186                         MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0    0x1d4
 187                         MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1    0x1d4
 188                         MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2    0x1d4
 189                         MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3    0x1d4
 190                         MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
 191                 >;
 192         };
 193
 194         pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
 195                 fsl,pins = <
 196                         MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK        0x196
 197                         MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD        0x1d6
 198                         MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0    0x1d6
 199                         MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1    0x1d6
 200                         MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2    0x1d6
 201                         MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3    0x1d6
 202                         MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
 203                 >;
 204         };
 205 };