arch/arm64/boot/dts/freescale/imx8mp-evk.dts

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Copyright 2019 NXP
   4  */
   5
   6 /dts-v1/;
   7
   8 #include "imx8mp.dtsi"
   9
  10 / {
  11         model = "NXP i.MX8MPlus EVK board";
  12         compatible = "fsl,imx8mp-evk", "fsl,imx8mp";
  13
  14         chosen {
  15                 stdout-path = &uart2;
  16         };
  17
  18         gpio-leds {
  19                 compatible = "gpio-leds";
  20                 pinctrl-names = "default";
  21                 pinctrl-0 = <&pinctrl_gpio_led>;
  22
  23                 status {
  24                         label = "yellow:status";
  25                         gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>;
  26                         default-state = "on";
  27                 };
  28         };
  29
  30         memory@40000000 {
  31                 device_type = "memory";
  32                 reg = <0x0 0x40000000 0 0xc0000000>,
  33                       <0x1 0x00000000 0 0xc0000000>;
  34         };
  35
  36         reg_can1_stby: regulator-can1-stby {
  37                 compatible = "regulator-fixed";
  38                 regulator-name = "can1-stby";
  39                 pinctrl-names = "default";
  40                 pinctrl-0 = <&pinctrl_flexcan1_reg>;
  41                 regulator-min-microvolt = <3300000>;
  42                 regulator-max-microvolt = <3300000>;
  43                 gpio = <&gpio5 5 GPIO_ACTIVE_HIGH>;
  44                 enable-active-high;
  45         };
  46
  47         reg_can2_stby: regulator-can2-stby {
  48                 compatible = "regulator-fixed";
  49                 regulator-name = "can2-stby";
  50                 pinctrl-names = "default";
  51                 pinctrl-0 = <&pinctrl_flexcan2_reg>;
  52                 regulator-min-microvolt = <3300000>;
  53                 regulator-max-microvolt = <3300000>;
  54                 gpio = <&gpio4 27 GPIO_ACTIVE_HIGH>;
  55                 enable-active-high;
  56         };
  57
  58         reg_usdhc2_vmmc: regulator-usdhc2 {
  59                 compatible = "regulator-fixed";
  60                 pinctrl-names = "default";
  61                 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
  62                 regulator-name = "VSD_3V3";
  63                 regulator-min-microvolt = <3300000>;
  64                 regulator-max-microvolt = <3300000>;
  65                 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
  66                 enable-active-high;
  67         };
  68 };
  69
  70 &flexcan1 {
  71         pinctrl-names = "default";
  72         pinctrl-0 = <&pinctrl_flexcan1>;
  73         xceiver-supply = <&reg_can1_stby>;
  74         status = "okay";
  75 };
  76
  77 &flexcan2 {
  78         pinctrl-names = "default";
  79         pinctrl-0 = <&pinctrl_flexcan2>;
  80         xceiver-supply = <&reg_can2_stby>;
  81         status = "disabled";/* can2 pin conflict with pdm */
  82 };
  83
  84 &eqos {
  85         pinctrl-names = "default";
  86         pinctrl-0 = <&pinctrl_eqos>;
  87         phy-mode = "rgmii-id";
  88         phy-handle = <&ethphy0>;
  89         status = "okay";
  90
  91         mdio {
  92                 compatible = "snps,dwmac-mdio";
  93                 #address-cells = <1>;
  94                 #size-cells = <0>;
  95
  96                 ethphy0: ethernet-phy@1 {
  97                         compatible = "ethernet-phy-ieee802.3-c22";
  98                         reg = <1>;
  99                         eee-broken-1000t;
 100                 };
 101         };
 102 };
 103
 104 &fec {
 105         pinctrl-names = "default";
 106         pinctrl-0 = <&pinctrl_fec>;
 107         phy-mode = "rgmii-id";
 108         phy-handle = <&ethphy1>;
 109         fsl,magic-packet;
 110         status = "okay";
 111
 112         mdio {
 113                 #address-cells = <1>;
 114                 #size-cells = <0>;
 115
 116                 ethphy1: ethernet-phy@1 {
 117                         compatible = "ethernet-phy-ieee802.3-c22";
 118                         reg = <1>;
 119                         eee-broken-1000t;
 120                         reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>;
 121                         reset-assert-us = <10000>;
 122                         reset-deassert-us = <80000>;
 123                 };
 124         };
 125 };
 126
 127 &i2c1 {
 128         clock-frequency = <400000>;
 129         pinctrl-names = "default";
 130         pinctrl-0 = <&pinctrl_i2c1>;
 131         status = "okay";
 132
 133         pmic@25 {
 134                 compatible = "nxp,pca9450c";
 135                 reg = <0x25>;
 136                 pinctrl-names = "default";
 137                 pinctrl-0 = <&pinctrl_pmic>;
 138                 interrupt-parent = <&gpio1>;
 139                 interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
 140
 141                 regulators {
 142                         BUCK1 {
 143                                 regulator-name = "BUCK1";
 144                                 regulator-min-microvolt = <720000>;
 145                                 regulator-max-microvolt = <1000000>;
 146                                 regulator-boot-on;
 147                                 regulator-always-on;
 148                                 regulator-ramp-delay = <3125>;
 149                         };
 150
 151                         BUCK2 {
 152                                 regulator-name = "BUCK2";
 153                                 regulator-min-microvolt = <720000>;
 154                                 regulator-max-microvolt = <1025000>;
 155                                 regulator-boot-on;
 156                                 regulator-always-on;
 157                                 regulator-ramp-delay = <3125>;
 158                                 nxp,dvs-run-voltage = <950000>;
 159                                 nxp,dvs-standby-voltage = <850000>;
 160                         };
 161
 162                         BUCK4 {
 163                                 regulator-name = "BUCK4";
 164                                 regulator-min-microvolt = <3000000>;
 165                                 regulator-max-microvolt = <3600000>;
 166                                 regulator-boot-on;
 167                                 regulator-always-on;
 168                         };
 169
 170                         BUCK5 {
 171                                 regulator-name = "BUCK5";
 172                                 regulator-min-microvolt = <1650000>;
 173                                 regulator-max-microvolt = <1950000>;
 174                                 regulator-boot-on;
 175                                 regulator-always-on;
 176                         };
 177
 178                         BUCK6 {
 179                                 regulator-name = "BUCK6";
 180                                 regulator-min-microvolt = <1045000>;
 181                                 regulator-max-microvolt = <1155000>;
 182                                 regulator-boot-on;
 183                                 regulator-always-on;
 184                         };
 185
 186                         LDO1 {
 187                                 regulator-name = "LDO1";
 188                                 regulator-min-microvolt = <1650000>;
 189                                 regulator-max-microvolt = <1950000>;
 190                                 regulator-boot-on;
 191                                 regulator-always-on;
 192                         };
 193
 194                         LDO3 {
 195                                 regulator-name = "LDO3";
 196                                 regulator-min-microvolt = <1710000>;
 197                                 regulator-max-microvolt = <1890000>;
 198                                 regulator-boot-on;
 199                                 regulator-always-on;
 200                         };
 201
 202                         LDO5 {
 203                                 regulator-name = "LDO5";
 204                                 regulator-min-microvolt = <1800000>;
 205                                 regulator-max-microvolt = <3300000>;
 206                                 regulator-boot-on;
 207                                 regulator-always-on;
 208                         };
 209                 };
 210         };
 211 };
 212
 213 &i2c3 {
 214         clock-frequency = <400000>;
 215         pinctrl-names = "default";
 216         pinctrl-0 = <&pinctrl_i2c3>;
 217         status = "okay";
 218
 219         pca6416: gpio@20 {
 220                 compatible = "ti,tca6416";
 221                 reg = <0x20>;
 222                 gpio-controller;
 223                 #gpio-cells = <2>;
 224         };
 225 };
 226
 227 &snvs_pwrkey {
 228         status = "okay";
 229 };
 230
 231 &uart2 {
 232         /* console */
 233         pinctrl-names = "default";
 234         pinctrl-0 = <&pinctrl_uart2>;
 235         status = "okay";
 236 };
 237
 238 &usb3_phy1 {
 239         status = "okay";
 240 };
 241
 242 &usb3_1 {
 243         status = "okay";
 244 };
 245
 246 &usb_dwc3_1 {
 247         pinctrl-names = "default";
 248         pinctrl-0 = <&pinctrl_usb1_vbus>;
 249         dr_mode = "host";
 250         status = "okay";
 251 };
 252
 253 &usdhc2 {
 254         assigned-clocks = <&clk IMX8MP_CLK_USDHC2>;
 255         assigned-clock-rates = <400000000>;
 256         pinctrl-names = "default", "state_100mhz", "state_200mhz";
 257         pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
 258         pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
 259         pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
 260         cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
 261         vmmc-supply = <&reg_usdhc2_vmmc>;
 262         bus-width = <4>;
 263         status = "okay";
 264 };
 265
 266 &usdhc3 {
 267         assigned-clocks = <&clk IMX8MP_CLK_USDHC3>;
 268         assigned-clock-rates = <400000000>;
 269         pinctrl-names = "default", "state_100mhz", "state_200mhz";
 270         pinctrl-0 = <&pinctrl_usdhc3>;
 271         pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
 272         pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
 273         bus-width = <8>;
 274         non-removable;
 275         status = "okay";
 276 };
 277
 278 &wdog1 {
 279         pinctrl-names = "default";
 280         pinctrl-0 = <&pinctrl_wdog>;
 281         fsl,ext-reset-output;
 282         status = "okay";
 283 };
 284
 285 &iomuxc {
 286         pinctrl_eqos: eqosgrp {
 287                 fsl,pins = <
 288                         MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC                             0x3
 289                         MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO                           0x3
 290                         MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0                       0x91
 291                         MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1                       0x91
 292                         MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2                       0x91
 293                         MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3                       0x91
 294                         MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK       0x91
 295                         MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL                 0x91
 296                         MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0                       0x1f
 297                         MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1                       0x1f
 298                         MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2                       0x1f
 299                         MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3                       0x1f
 300                         MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL                 0x1f
 301                         MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK       0x1f
 302                         MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22                               0x19
 303                 >;
 304         };
 305
 306         pinctrl_fec: fecgrp {
 307                 fsl,pins = <
 308                         MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC               0x3
 309                         MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO              0x3
 310                         MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0         0x91
 311                         MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1         0x91
 312                         MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2         0x91
 313                         MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3         0x91
 314                         MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC          0x91
 315                         MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL      0x91
 316                         MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0         0x1f
 317                         MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1         0x1f
 318                         MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2         0x1f
 319                         MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3         0x1f
 320                         MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL      0x1f
 321                         MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC         0x1f
 322                         MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02              0x19
 323                 >;
 324         };
 325
 326         pinctrl_flexcan1: flexcan1grp {
 327                 fsl,pins = <
 328                         MX8MP_IOMUXC_SPDIF_RX__CAN1_RX          0x154
 329                         MX8MP_IOMUXC_SPDIF_TX__CAN1_TX          0x154
 330                 >;
 331         };
 332
 333         pinctrl_flexcan2: flexcan2grp {
 334                 fsl,pins = <
 335                         MX8MP_IOMUXC_SAI5_MCLK__CAN2_RX         0x154
 336                         MX8MP_IOMUXC_SAI5_RXD3__CAN2_TX         0x154
 337                 >;
 338         };
 339
 340         pinctrl_flexcan1_reg: flexcan1reggrp {
 341                 fsl,pins = <
 342                         MX8MP_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO05  0x154   /* CAN1_STBY */
 343                 >;
 344         };
 345
 346         pinctrl_flexcan2_reg: flexcan2reggrp {
 347                 fsl,pins = <
 348                         MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27      0x154   /* CAN2_STBY */
 349                 >;
 350         };
 351
 352         pinctrl_gpio_led: gpioledgrp {
 353                 fsl,pins = <
 354                         MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16   0x19
 355                 >;
 356         };
 357
 358         pinctrl_i2c1: i2c1grp {
 359                 fsl,pins = <
 360                         MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL         0x400001c3
 361                         MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA         0x400001c3
 362                 >;
 363         };
 364
 365         pinctrl_i2c3: i2c3grp {
 366                 fsl,pins = <
 367                         MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL         0x400001c3
 368                         MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA         0x400001c3
 369                 >;
 370         };
 371
 372         pinctrl_pmic: pmicgrp {
 373                 fsl,pins = <
 374                         MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03     0x000001c0
 375                 >;
 376         };
 377
 378         pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
 379                 fsl,pins = <
 380                         MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19    0x41
 381                 >;
 382         };
 383
 384         pinctrl_uart2: uart2grp {
 385                 fsl,pins = <
 386                         MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX    0x49
 387                         MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX    0x49
 388                 >;
 389         };
 390
 391         pinctrl_usb1_vbus: usb1grp {
 392                 fsl,pins = <
 393                         MX8MP_IOMUXC_GPIO1_IO14__USB2_OTG_PWR   0x19
 394                 >;
 395         };
 396
 397         pinctrl_usdhc2: usdhc2grp {
 398                 fsl,pins = <
 399                         MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK        0x190
 400                         MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD        0x1d0
 401                         MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0    0x1d0
 402                         MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1    0x1d0
 403                         MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2    0x1d0
 404                         MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3    0x1d0
 405                         MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
 406                 >;
 407         };
 408
 409         pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
 410                 fsl,pins = <
 411                         MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK        0x194
 412                         MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD        0x1d4
 413                         MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0    0x1d4
 414                         MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1    0x1d4
 415                         MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2    0x1d4
 416                         MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3    0x1d4
 417                         MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
 418                 >;
 419         };
 420
 421         pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
 422                 fsl,pins = <
 423                         MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK        0x196
 424                         MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD        0x1d6
 425                         MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0    0x1d6
 426                         MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1    0x1d6
 427                         MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2    0x1d6
 428                         MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3    0x1d6
 429                         MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
 430                 >;
 431         };
 432
 433         pinctrl_usdhc2_gpio: usdhc2gpiogrp {
 434                 fsl,pins = <
 435                         MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12       0x1c4
 436                 >;
 437         };
 438
 439         pinctrl_usdhc3: usdhc3grp {
 440                 fsl,pins = <
 441                         MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK      0x190
 442                         MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD      0x1d0
 443                         MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0  0x1d0
 444                         MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1  0x1d0
 445                         MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2  0x1d0
 446                         MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3  0x1d0
 447                         MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4    0x1d0
 448                         MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5   0x1d0
 449                         MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6   0x1d0
 450                         MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7     0x1d0
 451                         MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE  0x190
 452                 >;
 453         };
 454
 455         pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
 456                 fsl,pins = <
 457                         MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK      0x194
 458                         MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD      0x1d4
 459                         MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0  0x1d4
 460                         MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1  0x1d4
 461                         MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2  0x1d4
 462                         MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3  0x1d4
 463                         MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4    0x1d4
 464                         MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5   0x1d4
 465                         MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6   0x1d4
 466                         MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7     0x1d4
 467                         MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE  0x194
 468                 >;
 469         };
 470
 471         pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
 472                 fsl,pins = <
 473                         MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK      0x196
 474                         MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD      0x1d6
 475                         MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0  0x1d6
 476                         MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1  0x1d6
 477                         MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2  0x1d6
 478                         MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3  0x1d6
 479                         MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4    0x1d6
 480                         MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5   0x1d6
 481                         MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6   0x1d6
 482                         MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7     0x1d6
 483                         MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE  0x196
 484                 >;
 485         };
 486
 487         pinctrl_wdog: wdoggrp {
 488                 fsl,pins = <
 489                         MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B   0x166
 490                 >;
 491         };
 492 };