arch/arm64/boot/dts/freescale/imx8mm-venice-gw71xx.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Copyright 2020 Gateworks Corporation
   4  */
   5
   6 #include <dt-bindings/gpio/gpio.h>
   7 #include <dt-bindings/leds/common.h>
   8 #include <dt-bindings/phy/phy-imx8-pcie.h>
   9
  10 / {
  11         aliases {
  12                 usb0 = &usbotg1;
  13                 usb1 = &usbotg2;
  14         };
  15
  16         led-controller {
  17                 compatible = "gpio-leds";
  18                 pinctrl-names = "default";
  19                 pinctrl-0 = <&pinctrl_gpio_leds>;
  20
  21                 led-0 {
  22                         function = LED_FUNCTION_STATUS;
  23                         color = <LED_COLOR_ID_GREEN>;
  24                         gpios = <&gpio5 5 GPIO_ACTIVE_HIGH>;
  25                         default-state = "on";
  26                         linux,default-trigger = "heartbeat";
  27                 };
  28
  29                 led-1 {
  30                         function = LED_FUNCTION_STATUS;
  31                         color = <LED_COLOR_ID_RED>;
  32                         gpios = <&gpio5 4 GPIO_ACTIVE_HIGH>;
  33                         default-state = "off";
  34                 };
  35         };
  36
  37         pcie0_refclk: pcie0-refclk {
  38                 compatible = "fixed-clock";
  39                 #clock-cells = <0>;
  40                 clock-frequency = <100000000>;
  41         };
  42
  43         pps {
  44                 compatible = "pps-gpio";
  45                 pinctrl-names = "default";
  46                 pinctrl-0 = <&pinctrl_pps>;
  47                 gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>;
  48                 status = "okay";
  49         };
  50
  51         reg_usb_otg1_vbus: regulator-usb-otg1 {
  52                 pinctrl-names = "default";
  53                 pinctrl-0 = <&pinctrl_reg_usb1_en>;
  54                 compatible = "regulator-fixed";
  55                 regulator-name = "usb_otg1_vbus";
  56                 gpio = <&gpio1 10 GPIO_ACTIVE_HIGH>;
  57                 enable-active-high;
  58                 regulator-min-microvolt = <5000000>;
  59                 regulator-max-microvolt = <5000000>;
  60         };
  61 };
  62
  63 /* off-board header */
  64 &ecspi2 {
  65         pinctrl-names = "default";
  66         pinctrl-0 = <&pinctrl_spi2>;
  67         cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
  68         status = "okay";
  69 };
  70
  71 &gpio1 {
  72         gpio-line-names = "", "", "", "", "", "", "pci_usb_sel", "dio0",
  73                 "", "dio1", "", "", "", "", "", "",
  74                 "", "", "", "", "", "", "", "",
  75                 "", "", "", "", "", "", "", "";
  76 };
  77
  78 &gpio4 {
  79         gpio-line-names = "", "", "", "dio2", "dio3", "", "", "pci_wdis#",
  80                 "", "", "", "", "", "", "", "",
  81                 "", "", "", "", "", "", "", "",
  82                 "", "", "", "", "", "", "", "";
  83 };
  84
  85 &i2c2 {
  86         clock-frequency = <400000>;
  87         pinctrl-names = "default";
  88         pinctrl-0 = <&pinctrl_i2c2>;
  89         status = "okay";
  90
  91         accelerometer@19 {
  92                 pinctrl-names = "default";
  93                 pinctrl-0 = <&pinctrl_accel>;
  94                 compatible = "st,lis2de12";
  95                 reg = <0x19>;
  96                 st,drdy-int-pin = <1>;
  97                 interrupt-parent = <&gpio4>;
  98                 interrupts = <5 IRQ_TYPE_LEVEL_LOW>;
  99                 interrupt-names = "INT1";
 100         };
 101 };
 102
 103 /* off-board header */
 104 &i2c3 {
 105         clock-frequency = <400000>;
 106         pinctrl-names = "default";
 107         pinctrl-0 = <&pinctrl_i2c3>;
 108         status = "okay";
 109 };
 110
 111 &pcie_phy {
 112         fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
 113         fsl,clkreq-unsupported;
 114         clocks = <&pcie0_refclk>;
 115         status = "okay";
 116 };
 117
 118 &pcie0 {
 119         pinctrl-names = "default";
 120         pinctrl-0 = <&pinctrl_pcie0>;
 121         reset-gpio = <&gpio4 6 GPIO_ACTIVE_LOW>;
 122         clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>,
 123                  <&pcie0_refclk>;
 124         clock-names = "pcie", "pcie_aux", "pcie_bus";
 125         assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
 126                           <&clk IMX8MM_CLK_PCIE1_CTRL>;
 127         assigned-clock-rates = <10000000>, <250000000>;
 128         assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
 129                                  <&clk IMX8MM_SYS_PLL2_250M>;
 130         status = "okay";
 131 };
 132
 133 /* GPS */
 134 &uart1 {
 135         pinctrl-names = "default";
 136         pinctrl-0 = <&pinctrl_uart1>;
 137         status = "okay";
 138 };
 139
 140 /* off-board header */
 141 &uart3 {
 142         pinctrl-names = "default";
 143         pinctrl-0 = <&pinctrl_uart3>;
 144         status = "okay";
 145 };
 146
 147 &usbotg1 {
 148         dr_mode = "otg";
 149         vbus-supply = <&reg_usb_otg1_vbus>;
 150         status = "okay";
 151 };
 152
 153 &usbotg2 {
 154         dr_mode = "host";
 155         status = "okay";
 156 };
 157
 158 &iomuxc {
 159         pinctrl-names = "default";
 160         pinctrl-0 = <&pinctrl_hog>;
 161
 162         pinctrl_hog: hoggrp {
 163                 fsl,pins = <
 164                         MX8MM_IOMUXC_SPDIF_TX_GPIO5_IO3         0x40000041 /* PLUG_TEST */
 165                         MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6       0x40000041 /* PCI_USBSEL */
 166                         MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7        0x40000041 /* PCIE_WDIS# */
 167                         MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7       0x40000041 /* DIO0 */
 168                         MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9       0x40000041 /* DIO1 */
 169                         MX8MM_IOMUXC_SAI1_RXD1_GPIO4_IO3        0x40000041 /* DIO2 */
 170                         MX8MM_IOMUXC_SAI1_RXD2_GPIO4_IO4        0x40000041 /* DIO2 */
 171                 >;
 172         };
 173
 174         pinctrl_accel: accelgrp {
 175                 fsl,pins = <
 176                         MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5        0x159
 177                 >;
 178         };
 179
 180         pinctrl_gpio_leds: gpioledgrp {
 181                 fsl,pins = <
 182                         MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5    0x19
 183                         MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4         0x19
 184                 >;
 185         };
 186
 187         pinctrl_i2c3: i2c3grp {
 188                 fsl,pins = <
 189                         MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL          0x400001c3
 190                         MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA          0x400001c3
 191                 >;
 192         };
 193
 194         pinctrl_pcie0: pcie0grp {
 195                 fsl,pins = <
 196                         MX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6        0x41
 197                 >;
 198         };
 199
 200         pinctrl_pps: ppsgrp {
 201                 fsl,pins = <
 202                         MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15      0x41
 203                 >;
 204         };
 205
 206         pinctrl_reg_usb1_en: regusb1grp {
 207                 fsl,pins = <
 208                         MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10      0x41
 209                         MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12      0x141
 210                         MX8MM_IOMUXC_GPIO1_IO13_USB1_OTG_OC     0x41
 211                 >;
 212         };
 213
 214         pinctrl_spi2: spi2grp {
 215                 fsl,pins = <
 216                         MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK    0xd6
 217                         MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI    0xd6
 218                         MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK    0xd6
 219                         MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13      0xd6
 220                 >;
 221         };
 222
 223         pinctrl_uart1: uart1grp {
 224                 fsl,pins = <
 225                         MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX     0x140
 226                         MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX     0x140
 227                 >;
 228         };
 229
 230         pinctrl_uart3: uart3grp {
 231                 fsl,pins = <
 232                         MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX     0x140
 233                         MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX     0x140
 234                 >;
 235         };
 236 };