1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2018-2019 NXP
4 * Dong Aisheng <aisheng.dong@nxp.com>
7 #include <dt-bindings/clock/imx8-lpcg.h>
8 #include <dt-bindings/firmware/imx/rsrc.h>
10 audio_subsys: bus@59000000 {
11 compatible = "simple-bus";
14 ranges = <0x59000000 0x0 0x59000000 0x1000000>;
16 audio_ipg_clk: clock-audio-ipg {
17 compatible = "fixed-clock";
19 clock-frequency = <120000000>;
20 clock-output-names = "audio_ipg_clk";
23 dsp_lpcg: clock-controller@59580000 {
24 compatible = "fsl,imx8qxp-lpcg";
25 reg = <0x59580000 0x10000>;
27 clocks = <&audio_ipg_clk>,
30 clock-indices = <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>,
32 clock-output-names = "dsp_lpcg_adb_clk",
35 power-domains = <&pd IMX_SC_R_DSP>;
38 dsp_ram_lpcg: clock-controller@59590000 {
39 compatible = "fsl,imx8qxp-lpcg";
40 reg = <0x59590000 0x10000>;
42 clocks = <&audio_ipg_clk>;
43 clock-indices = <IMX_LPCG_CLK_4>;
44 clock-output-names = "dsp_ram_lpcg_ipg_clk";
45 power-domains = <&pd IMX_SC_R_DSP_RAM>;
49 compatible = "fsl,imx8qxp-dsp";
50 reg = <0x596e8000 0x88000>;
51 clocks = <&dsp_lpcg IMX_LPCG_CLK_5>,
52 <&dsp_ram_lpcg IMX_LPCG_CLK_4>,
53 <&dsp_lpcg IMX_LPCG_CLK_7>;
54 clock-names = "ipg", "ocram", "core";
55 power-domains = <&pd IMX_SC_R_MU_13A>,
56 <&pd IMX_SC_R_MU_13B>,
58 <&pd IMX_SC_R_DSP_RAM>;
59 mbox-names = "txdb0", "txdb1",
61 mboxes = <&lsio_mu13 2 0>,
65 memory-region = <&dsp_reserved>;