arch/arm64/boot/dts/freescale/fsl-lx2162a-qds.dts

   1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
   2 //
   3 // Device Tree file for LX2162AQDS
   4 //
   5 // Copyright 2020 NXP
   6
   7 /dts-v1/;
   8
   9 #include "fsl-lx2160a.dtsi"
  10
  11 / {
  12         model = "NXP Layerscape LX2162AQDS";
  13         compatible = "fsl,lx2162a-qds", "fsl,lx2160a";
  14
  15         aliases {
  16                 crypto = &crypto;
  17                 mmc0 = &esdhc0;
  18                 mmc1 = &esdhc1;
  19                 serial0 = &uart0;
  20         };
  21
  22         chosen {
  23                 stdout-path = "serial0:115200n8";
  24         };
  25
  26         sb_3v3: regulator-sb3v3 {
  27                 compatible = "regulator-fixed";
  28                 regulator-name = "LTM4619-3.3VSB";
  29                 regulator-min-microvolt = <3300000>;
  30                 regulator-max-microvolt = <3300000>;
  31         };
  32
  33         mdio-mux-1 {
  34                 compatible = "mdio-mux-multiplexer";
  35                 mux-controls = <&mux 0>;
  36                 mdio-parent-bus = <&emdio1>;
  37                 #address-cells=<1>;
  38                 #size-cells = <0>;
  39
  40                 mdio@0 { /* On-board RTL8211F PHY #1 RGMII1 */
  41                         reg = <0x00>;
  42                         #address-cells = <1>;
  43                         #size-cells = <0>;
  44
  45                         rgmii_phy1: ethernet-phy@1 {
  46                                 compatible = "ethernet-phy-id001c.c916";
  47                                 reg = <0x1>;
  48                                 eee-broken-1000t;
  49                         };
  50                 };
  51
  52                 mdio@8 { /* On-board RTL8211F PHY #2 RGMII2 */
  53                         reg = <0x8>;
  54                         #address-cells = <1>;
  55                         #size-cells = <0>;
  56
  57                         rgmii_phy2: ethernet-phy@2 {
  58                                 compatible = "ethernet-phy-id001c.c916";
  59                                 reg = <0x2>;
  60                                 eee-broken-1000t;
  61                         };
  62                 };
  63
  64                 mdio@18 { /* Slot #1 */
  65                         reg = <0x18>;
  66                         #address-cells = <1>;
  67                         #size-cells = <0>;
  68                 };
  69
  70                 mdio@19 { /* Slot #2 */
  71                         reg = <0x19>;
  72                         #address-cells = <1>;
  73                         #size-cells = <0>;
  74                 };
  75
  76                 mdio@1a { /* Slot #3 */
  77                         reg = <0x1a>;
  78                         #address-cells = <1>;
  79                         #size-cells = <0>;
  80                 };
  81
  82                 mdio@1b { /* Slot #4 */
  83                         reg = <0x1b>;
  84                         #address-cells = <1>;
  85                         #size-cells = <0>;
  86                 };
  87
  88                 mdio@1c { /* Slot #5 */
  89                         reg = <0x1c>;
  90                         #address-cells = <1>;
  91                         #size-cells = <0>;
  92                 };
  93
  94                 mdio@1d { /* Slot #6 */
  95                         reg = <0x1d>;
  96                         #address-cells = <1>;
  97                         #size-cells = <0>;
  98                 };
  99
 100                 mdio@1e { /* Slot #7 */
 101                         reg = <0x1e>;
 102                         #address-cells = <1>;
 103                         #size-cells = <0>;
 104                 };
 105
 106                 mdio@1f { /* Slot #8 */
 107                         reg = <0x1f>;
 108                         #address-cells = <1>;
 109                         #size-cells = <0>;
 110                 };
 111         };
 112
 113         mdio-mux-2 {
 114                 compatible = "mdio-mux-multiplexer";
 115                 mux-controls = <&mux 1>;
 116                 mdio-parent-bus = <&emdio2>;
 117                 #address-cells=<1>;
 118                 #size-cells = <0>;
 119
 120                 mdio@0 { /* Slot #1 (secondary EMI) */
 121                         reg = <0x00>;
 122                         #address-cells = <1>;
 123                         #size-cells = <0>;
 124                 };
 125
 126                 mdio@1 { /* Slot #2 (secondary EMI) */
 127                         reg = <0x01>;
 128                         #address-cells = <1>;
 129                         #size-cells = <0>;
 130                 };
 131
 132                 mdio@2 { /* Slot #3 (secondary EMI) */
 133                         reg = <0x02>;
 134                         #address-cells = <1>;
 135                         #size-cells = <0>;
 136                 };
 137
 138                 mdio@3 { /* Slot #4 (secondary EMI) */
 139                         reg = <0x03>;
 140                         #address-cells = <1>;
 141                         #size-cells = <0>;
 142                 };
 143
 144                 mdio@4 { /* Slot #5 (secondary EMI) */
 145                         reg = <0x04>;
 146                         #address-cells = <1>;
 147                         #size-cells = <0>;
 148                 };
 149
 150                 mdio@5 { /* Slot #6 (secondary EMI) */
 151                         reg = <0x05>;
 152                         #address-cells = <1>;
 153                         #size-cells = <0>;
 154                 };
 155
 156                 mdio@6 { /* Slot #7 (secondary EMI) */
 157                         reg = <0x06>;
 158                         #address-cells = <1>;
 159                         #size-cells = <0>;
 160                 };
 161
 162                 mdio@7 { /* Slot #8 (secondary EMI) */
 163                         reg = <0x07>;
 164                         #address-cells = <1>;
 165                         #size-cells = <0>;
 166                 };
 167         };
 168 };
 169
 170 &crypto {
 171         status = "okay";
 172 };
 173
 174 &dpmac17 {
 175         phy-handle = <&rgmii_phy1>;
 176         phy-connection-type = "rgmii-id";
 177 };
 178
 179 &dpmac18 {
 180         phy-handle = <&rgmii_phy2>;
 181         phy-connection-type = "rgmii-id";
 182 };
 183
 184 &dspi0 {
 185         status = "okay";
 186
 187         dflash0: flash@0 {
 188                 #address-cells = <1>;
 189                 #size-cells = <1>;
 190                 compatible = "jedec,spi-nor";
 191                 reg = <0>;
 192                 spi-max-frequency = <1000000>;
 193         };
 194 };
 195
 196 &dspi1 {
 197         status = "okay";
 198
 199         dflash1: flash@0 {
 200                 #address-cells = <1>;
 201                 #size-cells = <1>;
 202                 compatible = "jedec,spi-nor";
 203                 reg = <0>;
 204                 spi-max-frequency = <1000000>;
 205         };
 206 };
 207
 208 &dspi2 {
 209         status = "okay";
 210
 211         dflash2: flash@0 {
 212                 #address-cells = <1>;
 213                 #size-cells = <1>;
 214                 compatible = "jedec,spi-nor";
 215                 reg = <0>;
 216                 spi-max-frequency = <1000000>;
 217         };
 218 };
 219
 220 &emdio1 {
 221         status = "okay";
 222 };
 223
 224 &emdio2 {
 225         status = "okay";
 226 };
 227
 228 &esdhc0 {
 229         status = "okay";
 230 };
 231
 232 &esdhc1 {
 233         status = "okay";
 234 };
 235
 236 &fspi {
 237         status = "okay";
 238
 239         mt35xu512aba0: flash@0 {
 240                 #address-cells = <1>;
 241                 #size-cells = <1>;
 242                 compatible = "jedec,spi-nor";
 243                 m25p,fast-read;
 244                 spi-max-frequency = <50000000>;
 245                 reg = <0>;
 246                 spi-rx-bus-width = <8>;
 247                 spi-tx-bus-width = <8>;
 248         };
 249 };
 250
 251 &i2c0 {
 252         status = "okay";
 253
 254         fpga@66 {
 255                 compatible = "fsl,lx2160aqds-fpga", "fsl,fpga-qixis-i2c",
 256                              "simple-mfd";
 257                 reg = <0x66>;
 258
 259                 mux: mux-controller {
 260                         compatible = "reg-mux";
 261                         #mux-control-cells = <1>;
 262                         mux-reg-masks = <0x54 0xf8>, /* 0: reg 0x54, bits 7:3 */
 263                                         <0x54 0x07>; /* 1: reg 0x54, bit 2:0 */
 264                 };
 265         };
 266
 267         i2c-mux@77 {
 268                 compatible = "nxp,pca9547";
 269                 reg = <0x77>;
 270                 #address-cells = <1>;
 271                 #size-cells = <0>;
 272
 273                 i2c@2 {
 274                         #address-cells = <1>;
 275                         #size-cells = <0>;
 276                         reg = <0x2>;
 277
 278                         power-monitor@40 {
 279                                 compatible = "ti,ina220";
 280                                 reg = <0x40>;
 281                                 shunt-resistor = <500>;
 282                         };
 283
 284                         power-monitor@41 {
 285                                 compatible = "ti,ina220";
 286                                 reg = <0x41>;
 287                                 shunt-resistor = <1000>;
 288                         };
 289                 };
 290
 291                 i2c@3 {
 292                         #address-cells = <1>;
 293                         #size-cells = <0>;
 294                         reg = <0x3>;
 295
 296                         temperature-sensor@4c {
 297                                 compatible = "nxp,sa56004";
 298                                 reg = <0x4c>;
 299                                 vcc-supply = <&sb_3v3>;
 300                         };
 301
 302                         rtc@51 {
 303                                 compatible = "nxp,pcf2129";
 304                                 reg = <0x51>;
 305                         };
 306                 };
 307         };
 308 };
 309
 310 &sata0 {
 311         status = "okay";
 312 };
 313
 314 &sata1 {
 315         status = "okay";
 316 };
 317
 318 &sata2 {
 319         status = "okay";
 320 };
 321
 322 &sata3 {
 323         status = "okay";
 324 };
 325
 326 &uart0 {
 327         status = "okay";
 328 };
 329
 330 &uart1 {
 331         status = "okay";
 332 };
 333
 334 &usb0 {
 335         status = "okay";
 336 };