arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
   2 //
   3 // Device Tree Include file for Layerscape-LX2160A family SoC.
   4 //
   5 // Copyright 2018-2020 NXP
   6
   7 #include <dt-bindings/gpio/gpio.h>
   8 #include <dt-bindings/interrupt-controller/arm-gic.h>
   9 #include <dt-bindings/thermal/thermal.h>
  10
  11 /memreserve/ 0x80000000 0x00010000;
  12
  13 / {
  14         compatible = "fsl,lx2160a";
  15         interrupt-parent = <&gic>;
  16         #address-cells = <2>;
  17         #size-cells = <2>;
  18
  19         aliases {
  20                 rtc1 = &ftm_alarm0;
  21         };
  22
  23         cpus {
  24                 #address-cells = <1>;
  25                 #size-cells = <0>;
  26
  27                 // 8 clusters having 2 Cortex-A72 cores each
  28                 cpu0: cpu@0 {
  29                         device_type = "cpu";
  30                         compatible = "arm,cortex-a72";
  31                         enable-method = "psci";
  32                         reg = <0x0>;
  33                         clocks = <&clockgen 1 0>;
  34                         d-cache-size = <0x8000>;
  35                         d-cache-line-size = <64>;
  36                         d-cache-sets = <128>;
  37                         i-cache-size = <0xC000>;
  38                         i-cache-line-size = <64>;
  39                         i-cache-sets = <192>;
  40                         next-level-cache = <&cluster0_l2>;
  41                         cpu-idle-states = <&cpu_pw15>;
  42                         #cooling-cells = <2>;
  43                 };
  44
  45                 cpu1: cpu@1 {
  46                         device_type = "cpu";
  47                         compatible = "arm,cortex-a72";
  48                         enable-method = "psci";
  49                         reg = <0x1>;
  50                         clocks = <&clockgen 1 0>;
  51                         d-cache-size = <0x8000>;
  52                         d-cache-line-size = <64>;
  53                         d-cache-sets = <128>;
  54                         i-cache-size = <0xC000>;
  55                         i-cache-line-size = <64>;
  56                         i-cache-sets = <192>;
  57                         next-level-cache = <&cluster0_l2>;
  58                         cpu-idle-states = <&cpu_pw15>;
  59                         #cooling-cells = <2>;
  60                 };
  61
  62                 cpu100: cpu@100 {
  63                         device_type = "cpu";
  64                         compatible = "arm,cortex-a72";
  65                         enable-method = "psci";
  66                         reg = <0x100>;
  67                         clocks = <&clockgen 1 1>;
  68                         d-cache-size = <0x8000>;
  69                         d-cache-line-size = <64>;
  70                         d-cache-sets = <128>;
  71                         i-cache-size = <0xC000>;
  72                         i-cache-line-size = <64>;
  73                         i-cache-sets = <192>;
  74                         next-level-cache = <&cluster1_l2>;
  75                         cpu-idle-states = <&cpu_pw15>;
  76                         #cooling-cells = <2>;
  77                 };
  78
  79                 cpu101: cpu@101 {
  80                         device_type = "cpu";
  81                         compatible = "arm,cortex-a72";
  82                         enable-method = "psci";
  83                         reg = <0x101>;
  84                         clocks = <&clockgen 1 1>;
  85                         d-cache-size = <0x8000>;
  86                         d-cache-line-size = <64>;
  87                         d-cache-sets = <128>;
  88                         i-cache-size = <0xC000>;
  89                         i-cache-line-size = <64>;
  90                         i-cache-sets = <192>;
  91                         next-level-cache = <&cluster1_l2>;
  92                         cpu-idle-states = <&cpu_pw15>;
  93                         #cooling-cells = <2>;
  94                 };
  95
  96                 cpu200: cpu@200 {
  97                         device_type = "cpu";
  98                         compatible = "arm,cortex-a72";
  99                         enable-method = "psci";
 100                         reg = <0x200>;
 101                         clocks = <&clockgen 1 2>;
 102                         d-cache-size = <0x8000>;
 103                         d-cache-line-size = <64>;
 104                         d-cache-sets = <128>;
 105                         i-cache-size = <0xC000>;
 106                         i-cache-line-size = <64>;
 107                         i-cache-sets = <192>;
 108                         next-level-cache = <&cluster2_l2>;
 109                         cpu-idle-states = <&cpu_pw15>;
 110                         #cooling-cells = <2>;
 111                 };
 112
 113                 cpu201: cpu@201 {
 114                         device_type = "cpu";
 115                         compatible = "arm,cortex-a72";
 116                         enable-method = "psci";
 117                         reg = <0x201>;
 118                         clocks = <&clockgen 1 2>;
 119                         d-cache-size = <0x8000>;
 120                         d-cache-line-size = <64>;
 121                         d-cache-sets = <128>;
 122                         i-cache-size = <0xC000>;
 123                         i-cache-line-size = <64>;
 124                         i-cache-sets = <192>;
 125                         next-level-cache = <&cluster2_l2>;
 126                         cpu-idle-states = <&cpu_pw15>;
 127                         #cooling-cells = <2>;
 128                 };
 129
 130                 cpu300: cpu@300 {
 131                         device_type = "cpu";
 132                         compatible = "arm,cortex-a72";
 133                         enable-method = "psci";
 134                         reg = <0x300>;
 135                         clocks = <&clockgen 1 3>;
 136                         d-cache-size = <0x8000>;
 137                         d-cache-line-size = <64>;
 138                         d-cache-sets = <128>;
 139                         i-cache-size = <0xC000>;
 140                         i-cache-line-size = <64>;
 141                         i-cache-sets = <192>;
 142                         next-level-cache = <&cluster3_l2>;
 143                         cpu-idle-states = <&cpu_pw15>;
 144                         #cooling-cells = <2>;
 145                 };
 146
 147                 cpu301: cpu@301 {
 148                         device_type = "cpu";
 149                         compatible = "arm,cortex-a72";
 150                         enable-method = "psci";
 151                         reg = <0x301>;
 152                         clocks = <&clockgen 1 3>;
 153                         d-cache-size = <0x8000>;
 154                         d-cache-line-size = <64>;
 155                         d-cache-sets = <128>;
 156                         i-cache-size = <0xC000>;
 157                         i-cache-line-size = <64>;
 158                         i-cache-sets = <192>;
 159                         next-level-cache = <&cluster3_l2>;
 160                         cpu-idle-states = <&cpu_pw15>;
 161                         #cooling-cells = <2>;
 162                 };
 163
 164                 cpu400: cpu@400 {
 165                         device_type = "cpu";
 166                         compatible = "arm,cortex-a72";
 167                         enable-method = "psci";
 168                         reg = <0x400>;
 169                         clocks = <&clockgen 1 4>;
 170                         d-cache-size = <0x8000>;
 171                         d-cache-line-size = <64>;
 172                         d-cache-sets = <128>;
 173                         i-cache-size = <0xC000>;
 174                         i-cache-line-size = <64>;
 175                         i-cache-sets = <192>;
 176                         next-level-cache = <&cluster4_l2>;
 177                         cpu-idle-states = <&cpu_pw15>;
 178                         #cooling-cells = <2>;
 179                 };
 180
 181                 cpu401: cpu@401 {
 182                         device_type = "cpu";
 183                         compatible = "arm,cortex-a72";
 184                         enable-method = "psci";
 185                         reg = <0x401>;
 186                         clocks = <&clockgen 1 4>;
 187                         d-cache-size = <0x8000>;
 188                         d-cache-line-size = <64>;
 189                         d-cache-sets = <128>;
 190                         i-cache-size = <0xC000>;
 191                         i-cache-line-size = <64>;
 192                         i-cache-sets = <192>;
 193                         next-level-cache = <&cluster4_l2>;
 194                         cpu-idle-states = <&cpu_pw15>;
 195                         #cooling-cells = <2>;
 196                 };
 197
 198                 cpu500: cpu@500 {
 199                         device_type = "cpu";
 200                         compatible = "arm,cortex-a72";
 201                         enable-method = "psci";
 202                         reg = <0x500>;
 203                         clocks = <&clockgen 1 5>;
 204                         d-cache-size = <0x8000>;
 205                         d-cache-line-size = <64>;
 206                         d-cache-sets = <128>;
 207                         i-cache-size = <0xC000>;
 208                         i-cache-line-size = <64>;
 209                         i-cache-sets = <192>;
 210                         next-level-cache = <&cluster5_l2>;
 211                         cpu-idle-states = <&cpu_pw15>;
 212                         #cooling-cells = <2>;
 213                 };
 214
 215                 cpu501: cpu@501 {
 216                         device_type = "cpu";
 217                         compatible = "arm,cortex-a72";
 218                         enable-method = "psci";
 219                         reg = <0x501>;
 220                         clocks = <&clockgen 1 5>;
 221                         d-cache-size = <0x8000>;
 222                         d-cache-line-size = <64>;
 223                         d-cache-sets = <128>;
 224                         i-cache-size = <0xC000>;
 225                         i-cache-line-size = <64>;
 226                         i-cache-sets = <192>;
 227                         next-level-cache = <&cluster5_l2>;
 228                         cpu-idle-states = <&cpu_pw15>;
 229                         #cooling-cells = <2>;
 230                 };
 231
 232                 cpu600: cpu@600 {
 233                         device_type = "cpu";
 234                         compatible = "arm,cortex-a72";
 235                         enable-method = "psci";
 236                         reg = <0x600>;
 237                         clocks = <&clockgen 1 6>;
 238                         d-cache-size = <0x8000>;
 239                         d-cache-line-size = <64>;
 240                         d-cache-sets = <128>;
 241                         i-cache-size = <0xC000>;
 242                         i-cache-line-size = <64>;
 243                         i-cache-sets = <192>;
 244                         next-level-cache = <&cluster6_l2>;
 245                         cpu-idle-states = <&cpu_pw15>;
 246                         #cooling-cells = <2>;
 247                 };
 248
 249                 cpu601: cpu@601 {
 250                         device_type = "cpu";
 251                         compatible = "arm,cortex-a72";
 252                         enable-method = "psci";
 253                         reg = <0x601>;
 254                         clocks = <&clockgen 1 6>;
 255                         d-cache-size = <0x8000>;
 256                         d-cache-line-size = <64>;
 257                         d-cache-sets = <128>;
 258                         i-cache-size = <0xC000>;
 259                         i-cache-line-size = <64>;
 260                         i-cache-sets = <192>;
 261                         next-level-cache = <&cluster6_l2>;
 262                         cpu-idle-states = <&cpu_pw15>;
 263                         #cooling-cells = <2>;
 264                 };
 265
 266                 cpu700: cpu@700 {
 267                         device_type = "cpu";
 268                         compatible = "arm,cortex-a72";
 269                         enable-method = "psci";
 270                         reg = <0x700>;
 271                         clocks = <&clockgen 1 7>;
 272                         d-cache-size = <0x8000>;
 273                         d-cache-line-size = <64>;
 274                         d-cache-sets = <128>;
 275                         i-cache-size = <0xC000>;
 276                         i-cache-line-size = <64>;
 277                         i-cache-sets = <192>;
 278                         next-level-cache = <&cluster7_l2>;
 279                         cpu-idle-states = <&cpu_pw15>;
 280                         #cooling-cells = <2>;
 281                 };
 282
 283                 cpu701: cpu@701 {
 284                         device_type = "cpu";
 285                         compatible = "arm,cortex-a72";
 286                         enable-method = "psci";
 287                         reg = <0x701>;
 288                         clocks = <&clockgen 1 7>;
 289                         d-cache-size = <0x8000>;
 290                         d-cache-line-size = <64>;
 291                         d-cache-sets = <128>;
 292                         i-cache-size = <0xC000>;
 293                         i-cache-line-size = <64>;
 294                         i-cache-sets = <192>;
 295                         next-level-cache = <&cluster7_l2>;
 296                         cpu-idle-states = <&cpu_pw15>;
 297                         #cooling-cells = <2>;
 298                 };
 299
 300                 cluster0_l2: l2-cache0 {
 301                         compatible = "cache";
 302                         cache-size = <0x100000>;
 303                         cache-line-size = <64>;
 304                         cache-sets = <1024>;
 305                         cache-level = <2>;
 306                 };
 307
 308                 cluster1_l2: l2-cache1 {
 309                         compatible = "cache";
 310                         cache-size = <0x100000>;
 311                         cache-line-size = <64>;
 312                         cache-sets = <1024>;
 313                         cache-level = <2>;
 314                 };
 315
 316                 cluster2_l2: l2-cache2 {
 317                         compatible = "cache";
 318                         cache-size = <0x100000>;
 319                         cache-line-size = <64>;
 320                         cache-sets = <1024>;
 321                         cache-level = <2>;
 322                 };
 323
 324                 cluster3_l2: l2-cache3 {
 325                         compatible = "cache";
 326                         cache-size = <0x100000>;
 327                         cache-line-size = <64>;
 328                         cache-sets = <1024>;
 329                         cache-level = <2>;
 330                 };
 331
 332                 cluster4_l2: l2-cache4 {
 333                         compatible = "cache";
 334                         cache-size = <0x100000>;
 335                         cache-line-size = <64>;
 336                         cache-sets = <1024>;
 337                         cache-level = <2>;
 338                 };
 339
 340                 cluster5_l2: l2-cache5 {
 341                         compatible = "cache";
 342                         cache-size = <0x100000>;
 343                         cache-line-size = <64>;
 344                         cache-sets = <1024>;
 345                         cache-level = <2>;
 346                 };
 347
 348                 cluster6_l2: l2-cache6 {
 349                         compatible = "cache";
 350                         cache-size = <0x100000>;
 351                         cache-line-size = <64>;
 352                         cache-sets = <1024>;
 353                         cache-level = <2>;
 354                 };
 355
 356                 cluster7_l2: l2-cache7 {
 357                         compatible = "cache";
 358                         cache-size = <0x100000>;
 359                         cache-line-size = <64>;
 360                         cache-sets = <1024>;
 361                         cache-level = <2>;
 362                 };
 363
 364                 cpu_pw15: cpu-pw15 {
 365                         compatible = "arm,idle-state";
 366                         idle-state-name = "PW15";
 367                         arm,psci-suspend-param = <0x0>;
 368                         entry-latency-us = <2000>;
 369                         exit-latency-us = <2000>;
 370                         min-residency-us = <6000>;
 371                   };
 372         };
 373
 374         gic: interrupt-controller@6000000 {
 375                 compatible = "arm,gic-v3";
 376                 reg = <0x0 0x06000000 0 0x10000>, // GIC Dist
 377                         <0x0 0x06200000 0 0x200000>, // GICR (RD_base +
 378                                                      // SGI_base)
 379                         <0x0 0x0c0c0000 0 0x2000>, // GICC
 380                         <0x0 0x0c0d0000 0 0x1000>, // GICH
 381                         <0x0 0x0c0e0000 0 0x20000>; // GICV
 382                 #interrupt-cells = <3>;
 383                 #address-cells = <2>;
 384                 #size-cells = <2>;
 385                 ranges;
 386                 interrupt-controller;
 387                 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
 388
 389                 its: gic-its@6020000 {
 390                         compatible = "arm,gic-v3-its";
 391                         msi-controller;
 392                         reg = <0x0 0x6020000 0 0x20000>;
 393                 };
 394         };
 395
 396         timer {
 397                 compatible = "arm,armv8-timer";
 398                 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>,
 399                              <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>,
 400                              <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>,
 401                              <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>;
 402         };
 403
 404         pmu {
 405                 compatible = "arm,cortex-a72-pmu";
 406                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
 407         };
 408
 409         psci {
 410                 compatible = "arm,psci-0.2";
 411                 method = "smc";
 412         };
 413
 414         memory@80000000 {
 415                 // DRAM space - 1, size : 2 GB DRAM
 416                 device_type = "memory";
 417                 reg = <0x00000000 0x80000000 0 0x80000000>;
 418         };
 419
 420         ddr1: memory-controller@1080000 {
 421                 compatible = "fsl,qoriq-memory-controller";
 422                 reg = <0x0 0x1080000 0x0 0x1000>;
 423                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 424                 little-endian;
 425         };
 426
 427         ddr2: memory-controller@1090000 {
 428                 compatible = "fsl,qoriq-memory-controller";
 429                 reg = <0x0 0x1090000 0x0 0x1000>;
 430                 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
 431                 little-endian;
 432         };
 433
 434         // One clock unit-sysclk node which bootloader require during DT fix-up
 435         sysclk: sysclk {
 436                 compatible = "fixed-clock";
 437                 #clock-cells = <0>;
 438                 clock-frequency = <100000000>; // fixed up by bootloader
 439                 clock-output-names = "sysclk";
 440         };
 441
 442         thermal-zones {
 443                 cluster6-7 {
 444                         polling-delay-passive = <1000>;
 445                         polling-delay = <5000>;
 446                         thermal-sensors = <&tmu 0>;
 447
 448                         trips {
 449                                 cluster6_7_alert: cluster6-7-alert {
 450                                         temperature = <85000>;
 451                                         hysteresis = <2000>;
 452                                         type = "passive";
 453                                 };
 454
 455                                 cluster6_7_crit: cluster6-7-crit {
 456                                         temperature = <95000>;
 457                                         hysteresis = <2000>;
 458                                         type = "critical";
 459                                 };
 460                         };
 461
 462                         cooling-maps {
 463                                 map0 {
 464                                         trip = <&cluster6_7_alert>;
 465                                         cooling-device =
 466                                                 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 467                                                 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 468                                                 <&cpu100 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 469                                                 <&cpu101 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 470                                                 <&cpu200 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 471                                                 <&cpu201 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 472                                                 <&cpu300 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 473                                                 <&cpu301 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 474                                                 <&cpu400 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 475                                                 <&cpu401 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 476                                                 <&cpu500 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 477                                                 <&cpu501 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 478                                                 <&cpu600 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 479                                                 <&cpu601 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 480                                                 <&cpu700 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 481                                                 <&cpu701 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 482                                 };
 483                         };
 484                 };
 485
 486                 ddr-cluster5 {
 487                         polling-delay-passive = <1000>;
 488                         polling-delay = <5000>;
 489                         thermal-sensors = <&tmu 1>;
 490
 491                         trips {
 492                                 ddr-cluster5-alert {
 493                                         temperature = <85000>;
 494                                         hysteresis = <2000>;
 495                                         type = "passive";
 496                                 };
 497
 498                                 ddr-cluster5-crit {
 499                                         temperature = <95000>;
 500                                         hysteresis = <2000>;
 501                                         type = "critical";
 502                                 };
 503                         };
 504                 };
 505
 506                 wriop {
 507                         polling-delay-passive = <1000>;
 508                         polling-delay = <5000>;
 509                         thermal-sensors = <&tmu 2>;
 510
 511                         trips {
 512                                 wriop-alert {
 513                                         temperature = <85000>;
 514                                         hysteresis = <2000>;
 515                                         type = "passive";
 516                                 };
 517
 518                                 wriop-crit {
 519                                         temperature = <95000>;
 520                                         hysteresis = <2000>;
 521                                         type = "critical";
 522                                 };
 523                         };
 524                 };
 525
 526                 dce-qbman-hsio2 {
 527                         polling-delay-passive = <1000>;
 528                         polling-delay = <5000>;
 529                         thermal-sensors = <&tmu 3>;
 530
 531                         trips {
 532                                 dce-qbman-alert {
 533                                         temperature = <85000>;
 534                                         hysteresis = <2000>;
 535                                         type = "passive";
 536                                 };
 537
 538                                 dce-qbman-crit {
 539                                         temperature = <95000>;
 540                                         hysteresis = <2000>;
 541                                         type = "critical";
 542                                 };
 543                         };
 544                 };
 545
 546                 ccn-dpaa-tbu {
 547                         polling-delay-passive = <1000>;
 548                         polling-delay = <5000>;
 549                         thermal-sensors = <&tmu 4>;
 550
 551                         trips {
 552                                 ccn-dpaa-alert {
 553                                         temperature = <85000>;
 554                                         hysteresis = <2000>;
 555                                         type = "passive";
 556                                 };
 557
 558                                 ccn-dpaa-crit {
 559                                         temperature = <95000>;
 560                                         hysteresis = <2000>;
 561                                         type = "critical";
 562                                 };
 563                         };
 564                 };
 565
 566                 cluster4-hsio3 {
 567                         polling-delay-passive = <1000>;
 568                         polling-delay = <5000>;
 569                         thermal-sensors = <&tmu 5>;
 570
 571                         trips {
 572                                 clust4-hsio3-alert {
 573                                         temperature = <85000>;
 574                                         hysteresis = <2000>;
 575                                         type = "passive";
 576                                 };
 577
 578                                 clust4-hsio3-crit {
 579                                         temperature = <95000>;
 580                                         hysteresis = <2000>;
 581                                         type = "critical";
 582                                 };
 583                         };
 584                 };
 585
 586                 cluster2-3 {
 587                         polling-delay-passive = <1000>;
 588                         polling-delay = <5000>;
 589                         thermal-sensors = <&tmu 6>;
 590
 591                         trips {
 592                                 cluster2-3-alert {
 593                                         temperature = <85000>;
 594                                         hysteresis = <2000>;
 595                                         type = "passive";
 596                                 };
 597
 598                                 cluster2-3-crit {
 599                                         temperature = <95000>;
 600                                         hysteresis = <2000>;
 601                                         type = "critical";
 602                                 };
 603                         };
 604                 };
 605         };
 606
 607         soc {
 608                 compatible = "simple-bus";
 609                 #address-cells = <2>;
 610                 #size-cells = <2>;
 611                 ranges;
 612                 dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>;
 613
 614                 crypto: crypto@8000000 {
 615                         compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
 616                         fsl,sec-era = <10>;
 617                         #address-cells = <1>;
 618                         #size-cells = <1>;
 619                         ranges = <0x0 0x00 0x8000000 0x100000>;
 620                         reg = <0x00 0x8000000 0x0 0x100000>;
 621                         interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
 622                         dma-coherent;
 623                         status = "disabled";
 624
 625                         sec_jr0: jr@10000 {
 626                                 compatible = "fsl,sec-v5.0-job-ring",
 627                                              "fsl,sec-v4.0-job-ring";
 628                                 reg        = <0x10000 0x10000>;
 629                                 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
 630                         };
 631
 632                         sec_jr1: jr@20000 {
 633                                 compatible = "fsl,sec-v5.0-job-ring",
 634                                              "fsl,sec-v4.0-job-ring";
 635                                 reg        = <0x20000 0x10000>;
 636                                 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
 637                         };
 638
 639                         sec_jr2: jr@30000 {
 640                                 compatible = "fsl,sec-v5.0-job-ring",
 641                                              "fsl,sec-v4.0-job-ring";
 642                                 reg        = <0x30000 0x10000>;
 643                                 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
 644                         };
 645
 646                         sec_jr3: jr@40000 {
 647                                 compatible = "fsl,sec-v5.0-job-ring",
 648                                              "fsl,sec-v4.0-job-ring";
 649                                 reg        = <0x40000 0x10000>;
 650                                 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
 651                         };
 652                 };
 653
 654                 clockgen: clock-controller@1300000 {
 655                         compatible = "fsl,lx2160a-clockgen";
 656                         reg = <0 0x1300000 0 0xa0000>;
 657                         #clock-cells = <2>;
 658                         clocks = <&sysclk>;
 659                 };
 660
 661                 dcfg: syscon@1e00000 {
 662                         compatible = "fsl,lx2160a-dcfg", "syscon";
 663                         reg = <0x0 0x1e00000 0x0 0x10000>;
 664                         little-endian;
 665                 };
 666
 667                 tmu: tmu@1f80000 {
 668                         compatible = "fsl,qoriq-tmu";
 669                         reg = <0x0 0x1f80000 0x0 0x10000>;
 670                         interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 671                         fsl,tmu-range = <0x800000e6 0x8001017d>;
 672                         fsl,tmu-calibration =
 673                                 /* Calibration data group 1 */
 674                                 <0x00000000 0x00000035
 675                                 /* Calibration data group 2 */
 676                                 0x00000001 0x00000154>;
 677                         little-endian;
 678                         #thermal-sensor-cells = <1>;
 679                 };
 680
 681                 i2c0: i2c@2000000 {
 682                         compatible = "fsl,vf610-i2c";
 683                         #address-cells = <1>;
 684                         #size-cells = <0>;
 685                         reg = <0x0 0x2000000 0x0 0x10000>;
 686                         interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 687                         clock-names = "i2c";
 688                         clocks = <&clockgen 4 15>;
 689                         scl-gpio = <&gpio2 15 GPIO_ACTIVE_HIGH>;
 690                         status = "disabled";
 691                 };
 692
 693                 i2c1: i2c@2010000 {
 694                         compatible = "fsl,vf610-i2c";
 695                         #address-cells = <1>;
 696                         #size-cells = <0>;
 697                         reg = <0x0 0x2010000 0x0 0x10000>;
 698                         interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 699                         clock-names = "i2c";
 700                         clocks = <&clockgen 4 15>;
 701                         status = "disabled";
 702                 };
 703
 704                 i2c2: i2c@2020000 {
 705                         compatible = "fsl,vf610-i2c";
 706                         #address-cells = <1>;
 707                         #size-cells = <0>;
 708                         reg = <0x0 0x2020000 0x0 0x10000>;
 709                         interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 710                         clock-names = "i2c";
 711                         clocks = <&clockgen 4 15>;
 712                         status = "disabled";
 713                 };
 714
 715                 i2c3: i2c@2030000 {
 716                         compatible = "fsl,vf610-i2c";
 717                         #address-cells = <1>;
 718                         #size-cells = <0>;
 719                         reg = <0x0 0x2030000 0x0 0x10000>;
 720                         interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 721                         clock-names = "i2c";
 722                         clocks = <&clockgen 4 15>;
 723                         status = "disabled";
 724                 };
 725
 726                 i2c4: i2c@2040000 {
 727                         compatible = "fsl,vf610-i2c";
 728                         #address-cells = <1>;
 729                         #size-cells = <0>;
 730                         reg = <0x0 0x2040000 0x0 0x10000>;
 731                         interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 732                         clock-names = "i2c";
 733                         clocks = <&clockgen 4 15>;
 734                         scl-gpio = <&gpio2 16 GPIO_ACTIVE_HIGH>;
 735                         status = "disabled";
 736                 };
 737
 738                 i2c5: i2c@2050000 {
 739                         compatible = "fsl,vf610-i2c";
 740                         #address-cells = <1>;
 741                         #size-cells = <0>;
 742                         reg = <0x0 0x2050000 0x0 0x10000>;
 743                         interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 744                         clock-names = "i2c";
 745                         clocks = <&clockgen 4 15>;
 746                         status = "disabled";
 747                 };
 748
 749                 i2c6: i2c@2060000 {
 750                         compatible = "fsl,vf610-i2c";
 751                         #address-cells = <1>;
 752                         #size-cells = <0>;
 753                         reg = <0x0 0x2060000 0x0 0x10000>;
 754                         interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 755                         clock-names = "i2c";
 756                         clocks = <&clockgen 4 15>;
 757                         status = "disabled";
 758                 };
 759
 760                 i2c7: i2c@2070000 {
 761                         compatible = "fsl,vf610-i2c";
 762                         #address-cells = <1>;
 763                         #size-cells = <0>;
 764                         reg = <0x0 0x2070000 0x0 0x10000>;
 765                         interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 766                         clock-names = "i2c";
 767                         clocks = <&clockgen 4 15>;
 768                         status = "disabled";
 769                 };
 770
 771                 fspi: spi@20c0000 {
 772                         compatible = "nxp,lx2160a-fspi";
 773                         #address-cells = <1>;
 774                         #size-cells = <0>;
 775                         reg = <0x0 0x20c0000 0x0 0x10000>,
 776                               <0x0 0x20000000 0x0 0x10000000>;
 777                         reg-names = "fspi_base", "fspi_mmap";
 778                         interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 779                         clocks = <&clockgen 4 3>, <&clockgen 4 3>;
 780                         clock-names = "fspi_en", "fspi";
 781                         status = "disabled";
 782                 };
 783
 784                 dspi0: spi@2100000 {
 785                         compatible = "fsl,lx2160a-dspi", "fsl,ls2085a-dspi";
 786                         #address-cells = <1>;
 787                         #size-cells = <0>;
 788                         reg = <0x0 0x2100000 0x0 0x10000>;
 789                         interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 790                         clocks = <&clockgen 4 7>;
 791                         clock-names = "dspi";
 792                         spi-num-chipselects = <5>;
 793                         bus-num = <0>;
 794                         status = "disabled";
 795                 };
 796
 797                 dspi1: spi@2110000 {
 798                         compatible = "fsl,lx2160a-dspi", "fsl,ls2085a-dspi";
 799                         #address-cells = <1>;
 800                         #size-cells = <0>;
 801                         reg = <0x0 0x2110000 0x0 0x10000>;
 802                         interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 803                         clocks = <&clockgen 4 7>;
 804                         clock-names = "dspi";
 805                         spi-num-chipselects = <5>;
 806                         bus-num = <1>;
 807                         status = "disabled";
 808                 };
 809
 810                 dspi2: spi@2120000 {
 811                         compatible = "fsl,lx2160a-dspi", "fsl,ls2085a-dspi";
 812                         #address-cells = <1>;
 813                         #size-cells = <0>;
 814                         reg = <0x0 0x2120000 0x0 0x10000>;
 815                         interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
 816                         clocks = <&clockgen 4 7>;
 817                         clock-names = "dspi";
 818                         spi-num-chipselects = <5>;
 819                         bus-num = <2>;
 820                         status = "disabled";
 821                 };
 822
 823                 esdhc0: esdhc@2140000 {
 824                         compatible = "fsl,esdhc";
 825                         reg = <0x0 0x2140000 0x0 0x10000>;
 826                         interrupts = <0 28 0x4>; /* Level high type */
 827                         clocks = <&clockgen 4 1>;
 828                         dma-coherent;
 829                         voltage-ranges = <1800 1800 3300 3300>;
 830                         sdhci,auto-cmd12;
 831                         little-endian;
 832                         bus-width = <4>;
 833                         status = "disabled";
 834                 };
 835
 836                 esdhc1: esdhc@2150000 {
 837                         compatible = "fsl,esdhc";
 838                         reg = <0x0 0x2150000 0x0 0x10000>;
 839                         interrupts = <0 63 0x4>; /* Level high type */
 840                         clocks = <&clockgen 4 1>;
 841                         dma-coherent;
 842                         voltage-ranges = <1800 1800 3300 3300>;
 843                         sdhci,auto-cmd12;
 844                         broken-cd;
 845                         little-endian;
 846                         bus-width = <4>;
 847                         status = "disabled";
 848                 };
 849
 850                 uart0: serial@21c0000 {
 851                         compatible = "arm,sbsa-uart","arm,pl011";
 852                         reg = <0x0 0x21c0000 0x0 0x1000>;
 853                         interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 854                         current-speed = <115200>;
 855                         status = "disabled";
 856                 };
 857
 858                 uart1: serial@21d0000 {
 859                         compatible = "arm,sbsa-uart","arm,pl011";
 860                         reg = <0x0 0x21d0000 0x0 0x1000>;
 861                         interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 862                         current-speed = <115200>;
 863                         status = "disabled";
 864                 };
 865
 866                 uart2: serial@21e0000 {
 867                         compatible = "arm,sbsa-uart","arm,pl011";
 868                         reg = <0x0 0x21e0000 0x0 0x1000>;
 869                         interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 870                         current-speed = <115200>;
 871                         status = "disabled";
 872                 };
 873
 874                 uart3: serial@21f0000 {
 875                         compatible = "arm,sbsa-uart","arm,pl011";
 876                         reg = <0x0 0x21f0000 0x0 0x1000>;
 877                         interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 878                         current-speed = <115200>;
 879                         status = "disabled";
 880                 };
 881
 882                 gpio0: gpio@2300000 {
 883                         compatible = "fsl,qoriq-gpio";
 884                         reg = <0x0 0x2300000 0x0 0x10000>;
 885                         interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 886                         gpio-controller;
 887                         little-endian;
 888                         #gpio-cells = <2>;
 889                         interrupt-controller;
 890                         #interrupt-cells = <2>;
 891                 };
 892
 893                 gpio1: gpio@2310000 {
 894                         compatible = "fsl,qoriq-gpio";
 895                         reg = <0x0 0x2310000 0x0 0x10000>;
 896                         interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 897                         gpio-controller;
 898                         little-endian;
 899                         #gpio-cells = <2>;
 900                         interrupt-controller;
 901                         #interrupt-cells = <2>;
 902                 };
 903
 904                 gpio2: gpio@2320000 {
 905                         compatible = "fsl,qoriq-gpio";
 906                         reg = <0x0 0x2320000 0x0 0x10000>;
 907                         interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 908                         gpio-controller;
 909                         little-endian;
 910                         #gpio-cells = <2>;
 911                         interrupt-controller;
 912                         #interrupt-cells = <2>;
 913                 };
 914
 915                 gpio3: gpio@2330000 {
 916                         compatible = "fsl,qoriq-gpio";
 917                         reg = <0x0 0x2330000 0x0 0x10000>;
 918                         interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 919                         gpio-controller;
 920                         little-endian;
 921                         #gpio-cells = <2>;
 922                         interrupt-controller;
 923                         #interrupt-cells = <2>;
 924                 };
 925
 926                 watchdog@23a0000 {
 927                         compatible = "arm,sbsa-gwdt";
 928                         reg = <0x0 0x23a0000 0 0x1000>,
 929                               <0x0 0x2390000 0 0x1000>;
 930                         interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 931                         timeout-sec = <30>;
 932                 };
 933
 934                 rcpm: power-controller@1e34040 {
 935                         compatible = "fsl,lx2160a-rcpm", "fsl,qoriq-rcpm-2.1+";
 936                         reg = <0x0 0x1e34040 0x0 0x1c>;
 937                         #fsl,rcpm-wakeup-cells = <7>;
 938                         little-endian;
 939                 };
 940
 941                 ftm_alarm0: timer@2800000 {
 942                         compatible = "fsl,lx2160a-ftm-alarm";
 943                         reg = <0x0 0x2800000 0x0 0x10000>;
 944                         fsl,rcpm-wakeup = <&rcpm 0x0 0x0 0x0 0x0 0x4000 0x0 0x0>;
 945                         interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 946                 };
 947
 948                 usb0: usb@3100000 {
 949                         compatible = "snps,dwc3";
 950                         reg = <0x0 0x3100000 0x0 0x10000>;
 951                         interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
 952                         dr_mode = "host";
 953                         snps,quirk-frame-length-adjustment = <0x20>;
 954                         snps,dis_rxdet_inp3_quirk;
 955                         snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
 956                         status = "disabled";
 957                 };
 958
 959                 usb1: usb@3110000 {
 960                         compatible = "snps,dwc3";
 961                         reg = <0x0 0x3110000 0x0 0x10000>;
 962                         interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
 963                         dr_mode = "host";
 964                         snps,quirk-frame-length-adjustment = <0x20>;
 965                         snps,dis_rxdet_inp3_quirk;
 966                         snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
 967                         status = "disabled";
 968                 };
 969
 970                 sata0: sata@3200000 {
 971                         compatible = "fsl,lx2160a-ahci";
 972                         reg = <0x0 0x3200000 0x0 0x10000>,
 973                               <0x7 0x100520 0x0 0x4>;
 974                         reg-names = "ahci", "sata-ecc";
 975                         interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
 976                         clocks = <&clockgen 4 3>;
 977                         dma-coherent;
 978                         status = "disabled";
 979                 };
 980
 981                 sata1: sata@3210000 {
 982                         compatible = "fsl,lx2160a-ahci";
 983                         reg = <0x0 0x3210000 0x0 0x10000>,
 984                               <0x7 0x100520 0x0 0x4>;
 985                         reg-names = "ahci", "sata-ecc";
 986                         interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
 987                         clocks = <&clockgen 4 3>;
 988                         dma-coherent;
 989                         status = "disabled";
 990                 };
 991
 992                 sata2: sata@3220000 {
 993                         compatible = "fsl,lx2160a-ahci";
 994                         reg = <0x0 0x3220000 0x0 0x10000>,
 995                               <0x7 0x100520 0x0 0x4>;
 996                         reg-names = "ahci", "sata-ecc";
 997                         interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 998                         clocks = <&clockgen 4 3>;
 999                         dma-coherent;
1000                         status = "disabled";
1001                 };
1002
1003                 sata3: sata@3230000 {
1004                         compatible = "fsl,lx2160a-ahci";
1005                         reg = <0x0 0x3230000 0x0 0x10000>,
1006                               <0x7 0x100520 0x0 0x4>;
1007                         reg-names = "ahci", "sata-ecc";
1008                         interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
1009                         clocks = <&clockgen 4 3>;
1010                         dma-coherent;
1011                         status = "disabled";
1012                 };
1013
1014                 pcie1: pcie@3400000 {
1015                         compatible = "fsl,lx2160a-pcie";
1016                         reg = <0x00 0x03400000 0x0 0x00100000   /* controller registers */
1017                                0x80 0x00000000 0x0 0x00002000>; /* configuration space */
1018                         reg-names = "csr_axi_slave", "config_axi_slave";
1019                         interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
1020                                      <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
1021                                      <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
1022                         interrupt-names = "aer", "pme", "intr";
1023                         #address-cells = <3>;
1024                         #size-cells = <2>;
1025                         device_type = "pci";
1026                         dma-coherent;
1027                         apio-wins = <8>;
1028                         ppio-wins = <8>;
1029                         bus-range = <0x0 0xff>;
1030                         ranges = <0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
1031                         msi-parent = <&its>;
1032                         #interrupt-cells = <1>;
1033                         interrupt-map-mask = <0 0 0 7>;
1034                         interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
1035                                         <0000 0 0 2 &gic 0 0 GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
1036                                         <0000 0 0 3 &gic 0 0 GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
1037                                         <0000 0 0 4 &gic 0 0 GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
1038                         iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
1039                         status = "disabled";
1040                 };
1041
1042                 pcie2: pcie@3500000 {
1043                         compatible = "fsl,lx2160a-pcie";
1044                         reg = <0x00 0x03500000 0x0 0x00100000   /* controller registers */
1045                                0x88 0x00000000 0x0 0x00002000>; /* configuration space */
1046                         reg-names = "csr_axi_slave", "config_axi_slave";
1047                         interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
1048                                      <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
1049                                      <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
1050                         interrupt-names = "aer", "pme", "intr";
1051                         #address-cells = <3>;
1052                         #size-cells = <2>;
1053                         device_type = "pci";
1054                         dma-coherent;
1055                         apio-wins = <8>;
1056                         ppio-wins = <8>;
1057                         bus-range = <0x0 0xff>;
1058                         ranges = <0x82000000 0x0 0x40000000 0x88 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
1059                         msi-parent = <&its>;
1060                         #interrupt-cells = <1>;
1061                         interrupt-map-mask = <0 0 0 7>;
1062                         interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
1063                                         <0000 0 0 2 &gic 0 0 GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
1064                                         <0000 0 0 3 &gic 0 0 GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
1065                                         <0000 0 0 4 &gic 0 0 GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
1066                         iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
1067                         status = "disabled";
1068                 };
1069
1070                 pcie3: pcie@3600000 {
1071                         compatible = "fsl,lx2160a-pcie";
1072                         reg = <0x00 0x03600000 0x0 0x00100000   /* controller registers */
1073                                0x90 0x00000000 0x0 0x00002000>; /* configuration space */
1074                         reg-names = "csr_axi_slave", "config_axi_slave";
1075                         interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
1076                                      <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
1077                                      <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
1078                         interrupt-names = "aer", "pme", "intr";
1079                         #address-cells = <3>;
1080                         #size-cells = <2>;
1081                         device_type = "pci";
1082                         dma-coherent;
1083                         apio-wins = <256>;
1084                         ppio-wins = <24>;
1085                         bus-range = <0x0 0xff>;
1086                         ranges = <0x82000000 0x0 0x40000000 0x90 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
1087                         msi-parent = <&its>;
1088                         #interrupt-cells = <1>;
1089                         interrupt-map-mask = <0 0 0 7>;
1090                         interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
1091                                         <0000 0 0 2 &gic 0 0 GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
1092                                         <0000 0 0 3 &gic 0 0 GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
1093                                         <0000 0 0 4 &gic 0 0 GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
1094                         iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
1095                         status = "disabled";
1096                 };
1097
1098                 pcie4: pcie@3700000 {
1099                         compatible = "fsl,lx2160a-pcie";
1100                         reg = <0x00 0x03700000 0x0 0x00100000   /* controller registers */
1101                                0x98 0x00000000 0x0 0x00002000>; /* configuration space */
1102                         reg-names = "csr_axi_slave", "config_axi_slave";
1103                         interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
1104                                      <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
1105                                      <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
1106                         interrupt-names = "aer", "pme", "intr";
1107                         #address-cells = <3>;
1108                         #size-cells = <2>;
1109                         device_type = "pci";
1110                         dma-coherent;
1111                         apio-wins = <8>;
1112                         ppio-wins = <8>;
1113                         bus-range = <0x0 0xff>;
1114                         ranges = <0x82000000 0x0 0x40000000 0x98 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
1115                         msi-parent = <&its>;
1116                         #interrupt-cells = <1>;
1117                         interrupt-map-mask = <0 0 0 7>;
1118                         interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
1119                                         <0000 0 0 2 &gic 0 0 GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
1120                                         <0000 0 0 3 &gic 0 0 GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
1121                                         <0000 0 0 4 &gic 0 0 GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
1122                         iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
1123                         status = "disabled";
1124                 };
1125
1126                 pcie5: pcie@3800000 {
1127                         compatible = "fsl,lx2160a-pcie";
1128                         reg = <0x00 0x03800000 0x0 0x00100000   /* controller registers */
1129                                0xa0 0x00000000 0x0 0x00002000>; /* configuration space */
1130                         reg-names = "csr_axi_slave", "config_axi_slave";
1131                         interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
1132                                      <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
1133                                      <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
1134                         interrupt-names = "aer", "pme", "intr";
1135                         #address-cells = <3>;
1136                         #size-cells = <2>;
1137                         device_type = "pci";
1138                         dma-coherent;
1139                         apio-wins = <256>;
1140                         ppio-wins = <24>;
1141                         bus-range = <0x0 0xff>;
1142                         ranges = <0x82000000 0x0 0x40000000 0xa0 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
1143                         msi-parent = <&its>;
1144                         #interrupt-cells = <1>;
1145                         interrupt-map-mask = <0 0 0 7>;
1146                         interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
1147                                         <0000 0 0 2 &gic 0 0 GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
1148                                         <0000 0 0 3 &gic 0 0 GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
1149                                         <0000 0 0 4 &gic 0 0 GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
1150                         iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
1151                         status = "disabled";
1152                 };
1153
1154                 pcie6: pcie@3900000 {
1155                         compatible = "fsl,lx2160a-pcie";
1156                         reg = <0x00 0x03900000 0x0 0x00100000   /* controller registers */
1157                                0xa8 0x00000000 0x0 0x00002000>; /* configuration space */
1158                         reg-names = "csr_axi_slave", "config_axi_slave";
1159                         interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
1160                                      <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
1161                                      <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
1162                         interrupt-names = "aer", "pme", "intr";
1163                         #address-cells = <3>;
1164                         #size-cells = <2>;
1165                         device_type = "pci";
1166                         dma-coherent;
1167                         apio-wins = <8>;
1168                         ppio-wins = <8>;
1169                         bus-range = <0x0 0xff>;
1170                         ranges = <0x82000000 0x0 0x40000000 0xa8 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
1171                         msi-parent = <&its>;
1172                         #interrupt-cells = <1>;
1173                         interrupt-map-mask = <0 0 0 7>;
1174                         interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
1175                                         <0000 0 0 2 &gic 0 0 GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
1176                                         <0000 0 0 3 &gic 0 0 GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
1177                                         <0000 0 0 4 &gic 0 0 GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
1178                         iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
1179                         status = "disabled";
1180                 };
1181
1182                 smmu: iommu@5000000 {
1183                         compatible = "arm,mmu-500";
1184                         reg = <0 0x5000000 0 0x800000>;
1185                         #iommu-cells = <1>;
1186                         #global-interrupts = <14>;
1187                                      // global secure fault
1188                         interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
1189                                      // combined secure
1190                                      <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
1191                                      // global non-secure fault
1192                                      <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
1193                                      // combined non-secure
1194                                      <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
1195                                      // performance counter interrupts 0-9
1196                                      <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
1197                                      <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
1198                                      <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
1199                                      <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
1200                                      <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
1201                                      <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
1202                                      <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
1203                                      <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
1204                                      <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
1205                                      <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
1206                                      // per context interrupt, 64 interrupts
1207                                      <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
1208                                      <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
1209                                      <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
1210                                      <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
1211                                      <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
1212                                      <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
1213                                      <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
1214                                      <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
1215                                      <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
1216                                      <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
1217                                      <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>,
1218                                      <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
1219                                      <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
1220                                      <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
1221                                      <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
1222                                      <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
1223                                      <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
1224                                      <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
1225                                      <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
1226                                      <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
1227                                      <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>,
1228                                      <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
1229                                      <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
1230                                      <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
1231                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1232                                      <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>,
1233                                      <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>,
1234                                      <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>,
1235                                      <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>,
1236                                      <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>,
1237                                      <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>,
1238                                      <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>,
1239                                      <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>,
1240                                      <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>,
1241                                      <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>,
1242                                      <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
1243                                      <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
1244                                      <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
1245                                      <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
1246                                      <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
1247                                      <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
1248                                      <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
1249                                      <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
1250                                      <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
1251                                      <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
1252                                      <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
1253                                      <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
1254                                      <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>,
1255                                      <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>,
1256                                      <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>,
1257                                      <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
1258                                      <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
1259                                      <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
1260                                      <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
1261                                      <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
1262                                      <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
1263                                      <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
1264                                      <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
1265                                      <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
1266                                      <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
1267                                      <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
1268                                      <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
1269                                      <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
1270                                      <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
1271                         dma-coherent;
1272                 };
1273
1274                 console@8340020 {
1275                         compatible = "fsl,dpaa2-console";
1276                         reg = <0x00000000 0x08340020 0 0x2>;
1277                 };
1278
1279                 ptp-timer@8b95000 {
1280                         compatible = "fsl,dpaa2-ptp";
1281                         reg = <0x0 0x8b95000 0x0 0x100>;
1282                         clocks = <&clockgen 4 1>;
1283                         little-endian;
1284                         fsl,extts-fifo;
1285                 };
1286
1287                 /* WRIOP0: 0x8b8_0000, E-MDIO1: 0x1_6000 */
1288                 emdio1: mdio@8b96000 {
1289                         compatible = "fsl,fman-memac-mdio";
1290                         reg = <0x0 0x8b96000 0x0 0x1000>;
1291                         interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
1292                         #address-cells = <1>;
1293                         #size-cells = <0>;
1294                         little-endian;
1295                         status = "disabled";
1296                 };
1297
1298                 emdio2: mdio@8b97000 {
1299                         compatible = "fsl,fman-memac-mdio";
1300                         reg = <0x0 0x8b97000 0x0 0x1000>;
1301                         interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
1302                         little-endian;
1303                         #address-cells = <1>;
1304                         #size-cells = <0>;
1305                         status = "disabled";
1306                 };
1307
1308                 fsl_mc: fsl-mc@80c000000 {
1309                         compatible = "fsl,qoriq-mc";
1310                         reg = <0x00000008 0x0c000000 0 0x40>,
1311                               <0x00000000 0x08340000 0 0x40000>;
1312                         msi-parent = <&its>;
1313                         /* iommu-map property is fixed up by u-boot */
1314                         iommu-map = <0 &smmu 0 0>;
1315                         dma-coherent;
1316                         #address-cells = <3>;
1317                         #size-cells = <1>;
1318
1319                         /*
1320                          * Region type 0x0 - MC portals
1321                          * Region type 0x1 - QBMAN portals
1322                          */
1323                         ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000
1324                                   0x1 0x0 0x0 0x8 0x18000000 0x8000000>;
1325
1326                         /*
1327                          * Define the maximum number of MACs present on the SoC.
1328                          */
1329                         dpmacs {
1330                                 #address-cells = <1>;
1331                                 #size-cells = <0>;
1332
1333                                 dpmac1: dpmac@1 {
1334                                         compatible = "fsl,qoriq-mc-dpmac";
1335                                         reg = <0x1>;
1336                                 };
1337
1338                                 dpmac2: dpmac@2 {
1339                                         compatible = "fsl,qoriq-mc-dpmac";
1340                                         reg = <0x2>;
1341                                 };
1342
1343                                 dpmac3: dpmac@3 {
1344                                         compatible = "fsl,qoriq-mc-dpmac";
1345                                         reg = <0x3>;
1346                                 };
1347
1348                                 dpmac4: dpmac@4 {
1349                                         compatible = "fsl,qoriq-mc-dpmac";
1350                                         reg = <0x4>;
1351                                 };
1352
1353                                 dpmac5: dpmac@5 {
1354                                         compatible = "fsl,qoriq-mc-dpmac";
1355                                         reg = <0x5>;
1356                                 };
1357
1358                                 dpmac6: dpmac@6 {
1359                                         compatible = "fsl,qoriq-mc-dpmac";
1360                                         reg = <0x6>;
1361                                 };
1362
1363                                 dpmac7: dpmac@7 {
1364                                         compatible = "fsl,qoriq-mc-dpmac";
1365                                         reg = <0x7>;
1366                                 };
1367
1368                                 dpmac8: dpmac@8 {
1369                                         compatible = "fsl,qoriq-mc-dpmac";
1370                                         reg = <0x8>;
1371                                 };
1372
1373                                 dpmac9: dpmac@9 {
1374                                         compatible = "fsl,qoriq-mc-dpmac";
1375                                         reg = <0x9>;
1376                                 };
1377
1378                                 dpmac10: dpmac@a {
1379                                         compatible = "fsl,qoriq-mc-dpmac";
1380                                         reg = <0xa>;
1381                                 };
1382
1383                                 dpmac11: dpmac@b {
1384                                         compatible = "fsl,qoriq-mc-dpmac";
1385                                         reg = <0xb>;
1386                                 };
1387
1388                                 dpmac12: dpmac@c {
1389                                         compatible = "fsl,qoriq-mc-dpmac";
1390                                         reg = <0xc>;
1391                                 };
1392
1393                                 dpmac13: dpmac@d {
1394                                         compatible = "fsl,qoriq-mc-dpmac";
1395                                         reg = <0xd>;
1396                                 };
1397
1398                                 dpmac14: dpmac@e {
1399                                         compatible = "fsl,qoriq-mc-dpmac";
1400                                         reg = <0xe>;
1401                                 };
1402
1403                                 dpmac15: dpmac@f {
1404                                         compatible = "fsl,qoriq-mc-dpmac";
1405                                         reg = <0xf>;
1406                                 };
1407
1408                                 dpmac16: dpmac@10 {
1409                                         compatible = "fsl,qoriq-mc-dpmac";
1410                                         reg = <0x10>;
1411                                 };
1412
1413                                 dpmac17: dpmac@11 {
1414                                         compatible = "fsl,qoriq-mc-dpmac";
1415                                         reg = <0x11>;
1416                                 };
1417
1418                                 dpmac18: dpmac@12 {
1419                                         compatible = "fsl,qoriq-mc-dpmac";
1420                                         reg = <0x12>;
1421                                 };
1422                         };
1423                 };
1424         };
1425 };