1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for NXP Layerscape-1088A family SoC.
5 * Copyright 2017-2020 NXP
7 * Harninder Rai <harninder.rai@nxp.com>
10 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/thermal/thermal.h>
15 compatible = "fsl,ls1088a";
16 interrupt-parent = <&gic>;
29 /* We have 2 clusters having 4 Cortex-A53 cores each */
32 compatible = "arm,cortex-a53";
34 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
35 cpu-idle-states = <&CPU_PH20>;
41 compatible = "arm,cortex-a53";
43 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
44 cpu-idle-states = <&CPU_PH20>;
50 compatible = "arm,cortex-a53";
52 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
53 cpu-idle-states = <&CPU_PH20>;
59 compatible = "arm,cortex-a53";
61 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
62 cpu-idle-states = <&CPU_PH20>;
68 compatible = "arm,cortex-a53";
70 clocks = <&clockgen QORIQ_CLK_CMUX 1>;
71 cpu-idle-states = <&CPU_PH20>;
77 compatible = "arm,cortex-a53";
79 clocks = <&clockgen QORIQ_CLK_CMUX 1>;
80 cpu-idle-states = <&CPU_PH20>;
86 compatible = "arm,cortex-a53";
88 clocks = <&clockgen QORIQ_CLK_CMUX 1>;
89 cpu-idle-states = <&CPU_PH20>;
95 compatible = "arm,cortex-a53";
97 clocks = <&clockgen QORIQ_CLK_CMUX 1>;
98 cpu-idle-states = <&CPU_PH20>;
103 compatible = "arm,idle-state";
104 idle-state-name = "PH20";
105 arm,psci-suspend-param = <0x0>;
106 entry-latency-us = <1000>;
107 exit-latency-us = <1000>;
108 min-residency-us = <3000>;
112 gic: interrupt-controller@6000000 {
113 compatible = "arm,gic-v3";
114 #interrupt-cells = <3>;
115 interrupt-controller;
116 reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */
117 <0x0 0x06100000 0 0x100000>, /* GICR(RD_base+SGI_base)*/
118 <0x0 0x0c0c0000 0 0x2000>, /* GICC */
119 <0x0 0x0c0d0000 0 0x1000>, /* GICH */
120 <0x0 0x0c0e0000 0 0x20000>; /* GICV */
121 interrupts = <1 9 IRQ_TYPE_LEVEL_HIGH>;
122 #address-cells = <2>;
126 its: gic-its@6020000 {
127 compatible = "arm,gic-v3-its";
129 reg = <0x0 0x6020000 0 0x20000>;
135 polling-delay-passive = <1000>;
136 polling-delay = <5000>;
137 thermal-sensors = <&tmu 0>;
140 core_cluster_alert: core-cluster-alert {
141 temperature = <85000>;
147 temperature = <95000>;
155 trip = <&core_cluster_alert>;
157 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
158 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
159 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
160 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
161 <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
162 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
163 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
164 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
170 polling-delay-passive = <1000>;
171 polling-delay = <5000>;
172 thermal-sensors = <&tmu 1>;
176 temperature = <95000>;
185 compatible = "arm,armv8-timer";
186 interrupts = <1 13 IRQ_TYPE_LEVEL_LOW>,/* Physical Secure PPI */
187 <1 14 IRQ_TYPE_LEVEL_LOW>,/* Physical Non-Secure PPI */
188 <1 11 IRQ_TYPE_LEVEL_LOW>,/* Virtual PPI */
189 <1 10 IRQ_TYPE_LEVEL_LOW>;/* Hypervisor PPI */
193 compatible = "arm,psci-0.2";
198 compatible = "fixed-clock";
200 clock-frequency = <100000000>;
201 clock-output-names = "sysclk";
205 compatible = "simple-bus";
206 #address-cells = <2>;
209 dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>;
211 clockgen: clocking@1300000 {
212 compatible = "fsl,ls1088a-clockgen";
213 reg = <0 0x1300000 0 0xa0000>;
219 compatible = "fsl,ls1088a-dcfg", "syscon";
220 reg = <0x0 0x1e00000 0x0 0x10000>;
224 isc: syscon@1f70000 {
225 compatible = "fsl,ls1088a-isc", "syscon";
226 reg = <0x0 0x1f70000 0x0 0x10000>;
228 #address-cells = <1>;
230 ranges = <0x0 0x0 0x1f70000 0x10000>;
232 extirq: interrupt-controller@14 {
233 compatible = "fsl,ls1088a-extirq";
234 #interrupt-cells = <2>;
235 #address-cells = <0>;
236 interrupt-controller;
239 <0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
240 <1 0 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
241 <2 0 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
242 <3 0 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
243 <4 0 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
244 <5 0 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
245 <6 0 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
246 <7 0 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
247 <8 0 &gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
248 <9 0 &gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
249 <10 0 &gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
250 <11 0 &gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
251 interrupt-map-mask = <0xffffffff 0x0>;
256 compatible = "fsl,qoriq-tmu";
257 reg = <0x0 0x1f80000 0x0 0x10000>;
258 interrupts = <0 23 0x4>;
259 fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x70062>;
260 fsl,tmu-calibration =
261 /* Calibration data group 1 */
262 <0x00000000 0x00000023
263 0x00000001 0x0000002a
264 0x00000002 0x00000030
265 0x00000003 0x00000037
266 0x00000004 0x0000003d
267 0x00000005 0x00000044
268 0x00000006 0x0000004a
269 0x00000007 0x00000051
270 0x00000008 0x00000057
271 0x00000009 0x0000005e
272 0x0000000a 0x00000064
273 0x0000000b 0x0000006b
274 /* Calibration data group 2 */
275 0x00010000 0x00000022
276 0x00010001 0x0000002a
277 0x00010002 0x00000032
278 0x00010003 0x0000003a
279 0x00010004 0x00000042
280 0x00010005 0x0000004a
281 0x00010006 0x00000052
282 0x00010007 0x0000005a
283 0x00010008 0x00000062
284 0x00010009 0x0000006a
285 /* Calibration data group 3 */
286 0x00020000 0x00000021
287 0x00020001 0x0000002b
288 0x00020002 0x00000035
289 0x00020003 0x00000040
290 0x00020004 0x0000004a
291 0x00020005 0x00000054
292 0x00020006 0x0000005e
293 /* Calibration data group 4 */
294 0x00030000 0x00000010
295 0x00030001 0x0000001c
296 0x00030002 0x00000027
297 0x00030003 0x00000032
298 0x00030004 0x0000003e
299 0x00030005 0x00000049
300 0x00030006 0x00000054
301 0x00030007 0x00000060>;
303 #thermal-sensor-cells = <1>;
307 compatible = "fsl,ls1088a-dspi",
308 "fsl,ls1021a-v1.0-dspi";
309 #address-cells = <1>;
311 reg = <0x0 0x2100000 0x0 0x10000>;
312 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
313 clock-names = "dspi";
314 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
315 QORIQ_CLK_PLL_DIV(2)>;
316 spi-num-chipselects = <6>;
320 duart0: serial@21c0500 {
321 compatible = "fsl,ns16550", "ns16550a";
322 reg = <0x0 0x21c0500 0x0 0x100>;
323 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
324 QORIQ_CLK_PLL_DIV(4)>;
325 interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
329 duart1: serial@21c0600 {
330 compatible = "fsl,ns16550", "ns16550a";
331 reg = <0x0 0x21c0600 0x0 0x100>;
332 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
333 QORIQ_CLK_PLL_DIV(4)>;
334 interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
338 gpio0: gpio@2300000 {
339 compatible = "fsl,ls1088a-gpio", "fsl,qoriq-gpio";
340 reg = <0x0 0x2300000 0x0 0x10000>;
341 interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>;
345 interrupt-controller;
346 #interrupt-cells = <2>;
349 gpio1: gpio@2310000 {
350 compatible = "fsl,ls1088a-gpio", "fsl,qoriq-gpio";
351 reg = <0x0 0x2310000 0x0 0x10000>;
352 interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>;
356 interrupt-controller;
357 #interrupt-cells = <2>;
360 gpio2: gpio@2320000 {
361 compatible = "fsl,ls1088a-gpio", "fsl,qoriq-gpio";
362 reg = <0x0 0x2320000 0x0 0x10000>;
363 interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>;
367 interrupt-controller;
368 #interrupt-cells = <2>;
371 gpio3: gpio@2330000 {
372 compatible = "fsl,ls1088a-gpio", "fsl,qoriq-gpio";
373 reg = <0x0 0x2330000 0x0 0x10000>;
374 interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>;
378 interrupt-controller;
379 #interrupt-cells = <2>;
383 compatible = "fsl,ifc", "simple-bus";
384 reg = <0x0 0x2240000 0x0 0x20000>;
385 interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>;
387 #address-cells = <2>;
393 compatible = "fsl,vf610-i2c";
394 #address-cells = <1>;
396 reg = <0x0 0x2000000 0x0 0x10000>;
397 interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
398 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
399 QORIQ_CLK_PLL_DIV(8)>;
404 compatible = "fsl,vf610-i2c";
405 #address-cells = <1>;
407 reg = <0x0 0x2010000 0x0 0x10000>;
408 interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
409 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
410 QORIQ_CLK_PLL_DIV(8)>;
415 compatible = "fsl,vf610-i2c";
416 #address-cells = <1>;
418 reg = <0x0 0x2020000 0x0 0x10000>;
419 interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>;
420 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
421 QORIQ_CLK_PLL_DIV(8)>;
426 compatible = "fsl,vf610-i2c";
427 #address-cells = <1>;
429 reg = <0x0 0x2030000 0x0 0x10000>;
430 interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>;
431 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
432 QORIQ_CLK_PLL_DIV(8)>;
437 compatible = "fsl,ls2080a-qspi";
438 #address-cells = <1>;
440 reg = <0x0 0x20c0000 0x0 0x10000>,
441 <0x0 0x20000000 0x0 0x10000000>;
442 reg-names = "QuadSPI", "QuadSPI-memory";
443 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
444 clock-names = "qspi_en", "qspi";
445 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
446 QORIQ_CLK_PLL_DIV(4)>,
447 <&clockgen QORIQ_CLK_PLATFORM_PLL
448 QORIQ_CLK_PLL_DIV(4)>;
452 esdhc: esdhc@2140000 {
453 compatible = "fsl,ls1088a-esdhc", "fsl,esdhc";
454 reg = <0x0 0x2140000 0x0 0x10000>;
455 interrupts = <0 28 0x4>; /* Level high type */
456 clock-frequency = <0>;
457 clocks = <&clockgen QORIQ_CLK_HWACCEL 1>;
458 voltage-ranges = <1800 1800 3300 3300>;
466 compatible = "snps,dwc3";
467 reg = <0x0 0x3100000 0x0 0x10000>;
468 interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>;
470 snps,quirk-frame-length-adjustment = <0x20>;
471 snps,dis_rxdet_inp3_quirk;
472 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
477 compatible = "snps,dwc3";
478 reg = <0x0 0x3110000 0x0 0x10000>;
479 interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>;
481 snps,quirk-frame-length-adjustment = <0x20>;
482 snps,dis_rxdet_inp3_quirk;
487 compatible = "fsl,ls1088a-ahci";
488 reg = <0x0 0x3200000 0x0 0x10000>,
489 <0x7 0x100520 0x0 0x4>;
490 reg-names = "ahci", "sata-ecc";
491 interrupts = <0 133 IRQ_TYPE_LEVEL_HIGH>;
492 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
493 QORIQ_CLK_PLL_DIV(4)>;
498 crypto: crypto@8000000 {
499 compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
501 #address-cells = <1>;
503 ranges = <0x0 0x00 0x8000000 0x100000>;
504 reg = <0x00 0x8000000 0x0 0x100000>;
505 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
509 compatible = "fsl,sec-v5.0-job-ring",
510 "fsl,sec-v4.0-job-ring";
511 reg = <0x10000 0x10000>;
512 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
516 compatible = "fsl,sec-v5.0-job-ring",
517 "fsl,sec-v4.0-job-ring";
518 reg = <0x20000 0x10000>;
519 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
523 compatible = "fsl,sec-v5.0-job-ring",
524 "fsl,sec-v4.0-job-ring";
525 reg = <0x30000 0x10000>;
526 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
530 compatible = "fsl,sec-v5.0-job-ring",
531 "fsl,sec-v4.0-job-ring";
532 reg = <0x40000 0x10000>;
533 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
537 pcie1: pcie@3400000 {
538 compatible = "fsl,ls1088a-pcie";
539 reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
540 0x20 0x00000000 0x0 0x00002000>; /* configuration space */
541 reg-names = "regs", "config";
542 interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
543 interrupt-names = "aer";
544 #address-cells = <3>;
548 num-viewport = <256>;
549 bus-range = <0x0 0xff>;
550 ranges = <0x81000000 0x0 0x00000000 0x20 0x00010000 0x0 0x00010000 /* downstream I/O */
551 0x82000000 0x0 0x40000000 0x20 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
553 #interrupt-cells = <1>;
554 interrupt-map-mask = <0 0 0 7>;
555 interrupt-map = <0000 0 0 1 &gic 0 0 0 109 IRQ_TYPE_LEVEL_HIGH>,
556 <0000 0 0 2 &gic 0 0 0 110 IRQ_TYPE_LEVEL_HIGH>,
557 <0000 0 0 3 &gic 0 0 0 111 IRQ_TYPE_LEVEL_HIGH>,
558 <0000 0 0 4 &gic 0 0 0 112 IRQ_TYPE_LEVEL_HIGH>;
559 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
563 pcie_ep1: pcie-ep@3400000 {
564 compatible = "fsl,ls1088a-pcie-ep", "fsl,ls-pcie-ep";
565 reg = <0x00 0x03400000 0x0 0x00100000
566 0x20 0x00000000 0x8 0x00000000>;
567 reg-names = "regs", "addr_space";
568 num-ib-windows = <24>;
569 num-ob-windows = <256>;
570 max-functions = /bits/ 8 <2>;
574 pcie2: pcie@3500000 {
575 compatible = "fsl,ls1088a-pcie";
576 reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */
577 0x28 0x00000000 0x0 0x00002000>; /* configuration space */
578 reg-names = "regs", "config";
579 interrupts = <0 113 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
580 interrupt-names = "aer";
581 #address-cells = <3>;
586 bus-range = <0x0 0xff>;
587 ranges = <0x81000000 0x0 0x00000000 0x28 0x00010000 0x0 0x00010000 /* downstream I/O */
588 0x82000000 0x0 0x40000000 0x28 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
590 #interrupt-cells = <1>;
591 interrupt-map-mask = <0 0 0 7>;
592 interrupt-map = <0000 0 0 1 &gic 0 0 0 114 IRQ_TYPE_LEVEL_HIGH>,
593 <0000 0 0 2 &gic 0 0 0 115 IRQ_TYPE_LEVEL_HIGH>,
594 <0000 0 0 3 &gic 0 0 0 116 IRQ_TYPE_LEVEL_HIGH>,
595 <0000 0 0 4 &gic 0 0 0 117 IRQ_TYPE_LEVEL_HIGH>;
596 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
600 pcie_ep2: pcie-ep@3500000 {
601 compatible = "fsl,ls1088a-pcie-ep", "fsl,ls-pcie-ep";
602 reg = <0x00 0x03500000 0x0 0x00100000
603 0x28 0x00000000 0x8 0x00000000>;
604 reg-names = "regs", "addr_space";
605 num-ib-windows = <6>;
606 num-ob-windows = <6>;
610 pcie3: pcie@3600000 {
611 compatible = "fsl,ls1088a-pcie";
612 reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */
613 0x30 0x00000000 0x0 0x00002000>; /* configuration space */
614 reg-names = "regs", "config";
615 interrupts = <0 118 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
616 interrupt-names = "aer";
617 #address-cells = <3>;
622 bus-range = <0x0 0xff>;
623 ranges = <0x81000000 0x0 0x00000000 0x30 0x00010000 0x0 0x00010000 /* downstream I/O */
624 0x82000000 0x0 0x40000000 0x30 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
626 #interrupt-cells = <1>;
627 interrupt-map-mask = <0 0 0 7>;
628 interrupt-map = <0000 0 0 1 &gic 0 0 0 119 IRQ_TYPE_LEVEL_HIGH>,
629 <0000 0 0 2 &gic 0 0 0 120 IRQ_TYPE_LEVEL_HIGH>,
630 <0000 0 0 3 &gic 0 0 0 121 IRQ_TYPE_LEVEL_HIGH>,
631 <0000 0 0 4 &gic 0 0 0 122 IRQ_TYPE_LEVEL_HIGH>;
632 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
636 pcie_ep3: pcie-ep@3600000 {
637 compatible = "fsl,ls1088a-pcie-ep", "fsl,ls-pcie-ep";
638 reg = <0x00 0x03600000 0x0 0x00100000
639 0x30 0x00000000 0x8 0x00000000>;
640 reg-names = "regs", "addr_space";
641 num-ib-windows = <6>;
642 num-ob-windows = <6>;
646 smmu: iommu@5000000 {
647 compatible = "arm,mmu-500";
648 reg = <0 0x5000000 0 0x800000>;
650 stream-match-mask = <0x7C00>;
651 #global-interrupts = <12>;
652 // global secure fault
653 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
655 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
656 // global non-secure fault
657 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
658 // combined non-secure
659 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
660 // performance counter interrupts 0-7
661 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
662 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
663 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
664 <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
665 <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
666 <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
667 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
668 <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
669 // per context interrupt, 64 interrupts
670 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
671 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
672 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
673 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
674 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
675 <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
676 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
677 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
678 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
679 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
680 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>,
681 <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
682 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
683 <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
684 <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
685 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
686 <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
687 <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
688 <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
689 <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
690 <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>,
691 <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
692 <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
693 <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
694 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
695 <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>,
696 <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>,
697 <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>,
698 <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>,
699 <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>,
700 <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>,
701 <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>,
702 <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>,
703 <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>,
704 <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>,
705 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
706 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
707 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
708 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
709 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
710 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
711 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
712 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
713 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
714 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
715 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
716 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
717 <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>,
718 <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>,
719 <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>,
720 <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
721 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
722 <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
723 <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
724 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
725 <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
726 <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
727 <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
728 <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
729 <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
730 <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
731 <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
732 <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
733 <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
737 compatible = "fsl,dpaa2-console";
738 reg = <0x00000000 0x08340020 0 0x2>;
742 compatible = "fsl,dpaa2-ptp";
743 reg = <0x0 0x8b95000 0x0 0x100>;
744 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
745 QORIQ_CLK_PLL_DIV(1)>;
750 emdio1: mdio@8b96000 {
751 compatible = "fsl,fman-memac-mdio";
752 reg = <0x0 0x8b96000 0x0 0x1000>;
754 #address-cells = <1>;
759 emdio2: mdio@8b97000 {
760 compatible = "fsl,fman-memac-mdio";
761 reg = <0x0 0x8b97000 0x0 0x1000>;
763 #address-cells = <1>;
768 pcs_mdio2: mdio@8c0b000 {
769 compatible = "fsl,fman-memac-mdio";
770 reg = <0x0 0x8c0b000 0x0 0x1000>;
772 #address-cells = <1>;
776 pcs2: ethernet-phy@0 {
781 pcs_mdio3: mdio@8c0f000 {
782 compatible = "fsl,fman-memac-mdio";
783 reg = <0x0 0x8c0f000 0x0 0x1000>;
785 #address-cells = <1>;
789 pcs3_0: ethernet-phy@0 {
793 pcs3_1: ethernet-phy@1 {
797 pcs3_2: ethernet-phy@2 {
801 pcs3_3: ethernet-phy@3 {
806 pcs_mdio7: mdio@8c1f000 {
807 compatible = "fsl,fman-memac-mdio";
808 reg = <0x0 0x8c1f000 0x0 0x1000>;
810 #address-cells = <1>;
814 pcs7_0: ethernet-phy@0 {
818 pcs7_1: ethernet-phy@1 {
822 pcs7_2: ethernet-phy@2 {
826 pcs7_3: ethernet-phy@3 {
831 cluster1_core0_watchdog: wdt@c000000 {
832 compatible = "arm,sp805-wdt", "arm,primecell";
833 reg = <0x0 0xc000000 0x0 0x1000>;
834 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
835 QORIQ_CLK_PLL_DIV(16)>,
836 <&clockgen QORIQ_CLK_PLATFORM_PLL
837 QORIQ_CLK_PLL_DIV(16)>;
838 clock-names = "wdog_clk", "apb_pclk";
841 cluster1_core1_watchdog: wdt@c010000 {
842 compatible = "arm,sp805-wdt", "arm,primecell";
843 reg = <0x0 0xc010000 0x0 0x1000>;
844 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
845 QORIQ_CLK_PLL_DIV(16)>,
846 <&clockgen QORIQ_CLK_PLATFORM_PLL
847 QORIQ_CLK_PLL_DIV(16)>;
848 clock-names = "wdog_clk", "apb_pclk";
851 cluster1_core2_watchdog: wdt@c020000 {
852 compatible = "arm,sp805-wdt", "arm,primecell";
853 reg = <0x0 0xc020000 0x0 0x1000>;
854 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
855 QORIQ_CLK_PLL_DIV(16)>,
856 <&clockgen QORIQ_CLK_PLATFORM_PLL
857 QORIQ_CLK_PLL_DIV(16)>;
858 clock-names = "wdog_clk", "apb_pclk";
861 cluster1_core3_watchdog: wdt@c030000 {
862 compatible = "arm,sp805-wdt", "arm,primecell";
863 reg = <0x0 0xc030000 0x0 0x1000>;
864 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
865 QORIQ_CLK_PLL_DIV(16)>,
866 <&clockgen QORIQ_CLK_PLATFORM_PLL
867 QORIQ_CLK_PLL_DIV(16)>;
868 clock-names = "wdog_clk", "apb_pclk";
871 cluster2_core0_watchdog: wdt@c100000 {
872 compatible = "arm,sp805-wdt", "arm,primecell";
873 reg = <0x0 0xc100000 0x0 0x1000>;
874 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
875 QORIQ_CLK_PLL_DIV(16)>,
876 <&clockgen QORIQ_CLK_PLATFORM_PLL
877 QORIQ_CLK_PLL_DIV(16)>;
878 clock-names = "wdog_clk", "apb_pclk";
881 cluster2_core1_watchdog: wdt@c110000 {
882 compatible = "arm,sp805-wdt", "arm,primecell";
883 reg = <0x0 0xc110000 0x0 0x1000>;
884 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
885 QORIQ_CLK_PLL_DIV(16)>,
886 <&clockgen QORIQ_CLK_PLATFORM_PLL
887 QORIQ_CLK_PLL_DIV(16)>;
888 clock-names = "wdog_clk", "apb_pclk";
891 cluster2_core2_watchdog: wdt@c120000 {
892 compatible = "arm,sp805-wdt", "arm,primecell";
893 reg = <0x0 0xc120000 0x0 0x1000>;
894 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
895 QORIQ_CLK_PLL_DIV(16)>,
896 <&clockgen QORIQ_CLK_PLATFORM_PLL
897 QORIQ_CLK_PLL_DIV(16)>;
898 clock-names = "wdog_clk", "apb_pclk";
901 cluster2_core3_watchdog: wdt@c130000 {
902 compatible = "arm,sp805-wdt", "arm,primecell";
903 reg = <0x0 0xc130000 0x0 0x1000>;
904 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
905 QORIQ_CLK_PLL_DIV(16)>,
906 <&clockgen QORIQ_CLK_PLATFORM_PLL
907 QORIQ_CLK_PLL_DIV(16)>;
908 clock-names = "wdog_clk", "apb_pclk";
911 fsl_mc: fsl-mc@80c000000 {
912 compatible = "fsl,qoriq-mc";
913 reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */
914 <0x00000000 0x08340000 0 0x40000>; /* MC control reg */
916 iommu-map = <0 &smmu 0 0>; /* This is fixed-up by u-boot */
918 #address-cells = <3>;
922 * Region type 0x0 - MC portals
923 * Region type 0x1 - QBMAN portals
925 ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000
926 0x1 0x0 0x0 0x8 0x18000000 0x8000000>;
929 #address-cells = <1>;
933 compatible = "fsl,qoriq-mc-dpmac";
938 compatible = "fsl,qoriq-mc-dpmac";
943 compatible = "fsl,qoriq-mc-dpmac";
948 compatible = "fsl,qoriq-mc-dpmac";
953 compatible = "fsl,qoriq-mc-dpmac";
958 compatible = "fsl,qoriq-mc-dpmac";
963 compatible = "fsl,qoriq-mc-dpmac";
968 compatible = "fsl,qoriq-mc-dpmac";
973 compatible = "fsl,qoriq-mc-dpmac";
977 dpmac10: ethernet@a {
978 compatible = "fsl,qoriq-mc-dpmac";
984 rcpm: power-controller@1e34040 {
985 compatible = "fsl,ls1088a-rcpm", "fsl,qoriq-rcpm-2.1+";
986 reg = <0x0 0x1e34040 0x0 0x18>;
987 #fsl,rcpm-wakeup-cells = <6>;
991 ftm_alarm0: timer@2800000 {
992 compatible = "fsl,ls1088a-ftm-alarm";
993 reg = <0x0 0x2800000 0x0 0x10000>;
994 fsl,rcpm-wakeup = <&rcpm 0x0 0x0 0x0 0x0 0x4000 0x0>;
995 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
1001 compatible = "linaro,optee-tz";