arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Device Tree Include file for NXP Layerscape-1088A family SoC.
   4  *
   5  * Copyright 2017-2020 NXP
   6  *
   7  * Harninder Rai <harninder.rai@nxp.com>
   8  *
   9  */
  10 #include <dt-bindings/interrupt-controller/arm-gic.h>
  11 #include <dt-bindings/thermal/thermal.h>
  12
  13 / {
  14         compatible = "fsl,ls1088a";
  15         interrupt-parent = <&gic>;
  16         #address-cells = <2>;
  17         #size-cells = <2>;
  18
  19         aliases {
  20                 crypto = &crypto;
  21                 rtc1 = &ftm_alarm0;
  22         };
  23
  24         cpus {
  25                 #address-cells = <1>;
  26                 #size-cells = <0>;
  27
  28                 /* We have 2 clusters having 4 Cortex-A53 cores each */
  29                 cpu0: cpu@0 {
  30                         device_type = "cpu";
  31                         compatible = "arm,cortex-a53";
  32                         reg = <0x0>;
  33                         clocks = <&clockgen 1 0>;
  34                         cpu-idle-states = <&CPU_PH20>;
  35                         #cooling-cells = <2>;
  36                 };
  37
  38                 cpu1: cpu@1 {
  39                         device_type = "cpu";
  40                         compatible = "arm,cortex-a53";
  41                         reg = <0x1>;
  42                         clocks = <&clockgen 1 0>;
  43                         cpu-idle-states = <&CPU_PH20>;
  44                         #cooling-cells = <2>;
  45                 };
  46
  47                 cpu2: cpu@2 {
  48                         device_type = "cpu";
  49                         compatible = "arm,cortex-a53";
  50                         reg = <0x2>;
  51                         clocks = <&clockgen 1 0>;
  52                         cpu-idle-states = <&CPU_PH20>;
  53                         #cooling-cells = <2>;
  54                 };
  55
  56                 cpu3: cpu@3 {
  57                         device_type = "cpu";
  58                         compatible = "arm,cortex-a53";
  59                         reg = <0x3>;
  60                         clocks = <&clockgen 1 0>;
  61                         cpu-idle-states = <&CPU_PH20>;
  62                         #cooling-cells = <2>;
  63                 };
  64
  65                 cpu4: cpu@100 {
  66                         device_type = "cpu";
  67                         compatible = "arm,cortex-a53";
  68                         reg = <0x100>;
  69                         clocks = <&clockgen 1 1>;
  70                         cpu-idle-states = <&CPU_PH20>;
  71                         #cooling-cells = <2>;
  72                 };
  73
  74                 cpu5: cpu@101 {
  75                         device_type = "cpu";
  76                         compatible = "arm,cortex-a53";
  77                         reg = <0x101>;
  78                         clocks = <&clockgen 1 1>;
  79                         cpu-idle-states = <&CPU_PH20>;
  80                         #cooling-cells = <2>;
  81                 };
  82
  83                 cpu6: cpu@102 {
  84                         device_type = "cpu";
  85                         compatible = "arm,cortex-a53";
  86                         reg = <0x102>;
  87                         clocks = <&clockgen 1 1>;
  88                         cpu-idle-states = <&CPU_PH20>;
  89                         #cooling-cells = <2>;
  90                 };
  91
  92                 cpu7: cpu@103 {
  93                         device_type = "cpu";
  94                         compatible = "arm,cortex-a53";
  95                         reg = <0x103>;
  96                         clocks = <&clockgen 1 1>;
  97                         cpu-idle-states = <&CPU_PH20>;
  98                         #cooling-cells = <2>;
  99                 };
 100
 101                 CPU_PH20: cpu-ph20 {
 102                         compatible = "arm,idle-state";
 103                         idle-state-name = "PH20";
 104                         arm,psci-suspend-param = <0x0>;
 105                         entry-latency-us = <1000>;
 106                         exit-latency-us = <1000>;
 107                         min-residency-us = <3000>;
 108                 };
 109         };
 110
 111         gic: interrupt-controller@6000000 {
 112                 compatible = "arm,gic-v3";
 113                 #interrupt-cells = <3>;
 114                 interrupt-controller;
 115                 reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */
 116                       <0x0 0x06100000 0 0x100000>, /* GICR(RD_base+SGI_base)*/
 117                       <0x0 0x0c0c0000 0 0x2000>, /* GICC */
 118                       <0x0 0x0c0d0000 0 0x1000>, /* GICH */
 119                       <0x0 0x0c0e0000 0 0x20000>; /* GICV */
 120                 interrupts = <1 9 IRQ_TYPE_LEVEL_HIGH>;
 121                 #address-cells = <2>;
 122                 #size-cells = <2>;
 123                 ranges;
 124
 125                 its: gic-its@6020000 {
 126                         compatible = "arm,gic-v3-its";
 127                         msi-controller;
 128                         reg = <0x0 0x6020000 0 0x20000>;
 129                 };
 130         };
 131
 132         thermal-zones {
 133                 core-cluster {
 134                         polling-delay-passive = <1000>;
 135                         polling-delay = <5000>;
 136                         thermal-sensors = <&tmu 0>;
 137
 138                         trips {
 139                                 core_cluster_alert: core-cluster-alert {
 140                                         temperature = <85000>;
 141                                         hysteresis = <2000>;
 142                                         type = "passive";
 143                                 };
 144
 145                                 core-cluster-crit {
 146                                         temperature = <95000>;
 147                                         hysteresis = <2000>;
 148                                         type = "critical";
 149                                 };
 150                         };
 151
 152                         cooling-maps {
 153                                 map0 {
 154                                         trip = <&core_cluster_alert>;
 155                                         cooling-device =
 156                                                 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 157                                                 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 158                                                 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 159                                                 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 160                                                 <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 161                                                 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 162                                                 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 163                                                 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 164                                 };
 165                         };
 166                 };
 167
 168                 soc {
 169                         polling-delay-passive = <1000>;
 170                         polling-delay = <5000>;
 171                         thermal-sensors = <&tmu 1>;
 172
 173                         trips {
 174                                 soc-crit {
 175                                         temperature = <95000>;
 176                                         hysteresis = <2000>;
 177                                         type = "critical";
 178                                 };
 179                         };
 180                 };
 181         };
 182
 183         timer {
 184                 compatible = "arm,armv8-timer";
 185                 interrupts = <1 13 IRQ_TYPE_LEVEL_LOW>,/* Physical Secure PPI */
 186                              <1 14 IRQ_TYPE_LEVEL_LOW>,/* Physical Non-Secure PPI */
 187                              <1 11 IRQ_TYPE_LEVEL_LOW>,/* Virtual PPI */
 188                              <1 10 IRQ_TYPE_LEVEL_LOW>;/* Hypervisor PPI */
 189         };
 190
 191         psci {
 192                 compatible = "arm,psci-0.2";
 193                 method = "smc";
 194         };
 195
 196         sysclk: sysclk {
 197                 compatible = "fixed-clock";
 198                 #clock-cells = <0>;
 199                 clock-frequency = <100000000>;
 200                 clock-output-names = "sysclk";
 201         };
 202
 203         soc {
 204                 compatible = "simple-bus";
 205                 #address-cells = <2>;
 206                 #size-cells = <2>;
 207                 ranges;
 208                 dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>;
 209
 210                 clockgen: clocking@1300000 {
 211                         compatible = "fsl,ls1088a-clockgen";
 212                         reg = <0 0x1300000 0 0xa0000>;
 213                         #clock-cells = <2>;
 214                         clocks = <&sysclk>;
 215                 };
 216
 217                 dcfg: dcfg@1e00000 {
 218                         compatible = "fsl,ls1088a-dcfg", "syscon";
 219                         reg = <0x0 0x1e00000 0x0 0x10000>;
 220                         little-endian;
 221                 };
 222
 223                 tmu: tmu@1f80000 {
 224                         compatible = "fsl,qoriq-tmu";
 225                         reg = <0x0 0x1f80000 0x0 0x10000>;
 226                         interrupts = <0 23 0x4>;
 227                         fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x70062>;
 228                         fsl,tmu-calibration =
 229                                 /* Calibration data group 1 */
 230                                 <0x00000000 0x00000023
 231                                 0x00000001 0x0000002a
 232                                 0x00000002 0x00000030
 233                                 0x00000003 0x00000037
 234                                 0x00000004 0x0000003d
 235                                 0x00000005 0x00000044
 236                                 0x00000006 0x0000004a
 237                                 0x00000007 0x00000051
 238                                 0x00000008 0x00000057
 239                                 0x00000009 0x0000005e
 240                                 0x0000000a 0x00000064
 241                                 0x0000000b 0x0000006b
 242                                 /* Calibration data group 2 */
 243                                 0x00010000 0x00000022
 244                                 0x00010001 0x0000002a
 245                                 0x00010002 0x00000032
 246                                 0x00010003 0x0000003a
 247                                 0x00010004 0x00000042
 248                                 0x00010005 0x0000004a
 249                                 0x00010006 0x00000052
 250                                 0x00010007 0x0000005a
 251                                 0x00010008 0x00000062
 252                                 0x00010009 0x0000006a
 253                                 /* Calibration data group 3 */
 254                                 0x00020000 0x00000021
 255                                 0x00020001 0x0000002b
 256                                 0x00020002 0x00000035
 257                                 0x00020003 0x00000040
 258                                 0x00020004 0x0000004a
 259                                 0x00020005 0x00000054
 260                                 0x00020006 0x0000005e
 261                                 /* Calibration data group 4 */
 262                                 0x00030000 0x00000010
 263                                 0x00030001 0x0000001c
 264                                 0x00030002 0x00000027
 265                                 0x00030003 0x00000032
 266                                 0x00030004 0x0000003e
 267                                 0x00030005 0x00000049
 268                                 0x00030006 0x00000054
 269                                 0x00030007 0x00000060>;
 270                         little-endian;
 271                         #thermal-sensor-cells = <1>;
 272                 };
 273
 274                 dspi: spi@2100000 {
 275                         compatible = "fsl,ls1088a-dspi",
 276                                      "fsl,ls1021a-v1.0-dspi";
 277                         #address-cells = <1>;
 278                         #size-cells = <0>;
 279                         reg = <0x0 0x2100000 0x0 0x10000>;
 280                         interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 281                         clock-names = "dspi";
 282                         clocks = <&clockgen 4 1>;
 283                         spi-num-chipselects = <6>;
 284                         status = "disabled";
 285                 };
 286
 287                 duart0: serial@21c0500 {
 288                         compatible = "fsl,ns16550", "ns16550a";
 289                         reg = <0x0 0x21c0500 0x0 0x100>;
 290                         clocks = <&clockgen 4 3>;
 291                         interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
 292                         status = "disabled";
 293                 };
 294
 295                 duart1: serial@21c0600 {
 296                         compatible = "fsl,ns16550", "ns16550a";
 297                         reg = <0x0 0x21c0600 0x0 0x100>;
 298                         clocks = <&clockgen 4 3>;
 299                         interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
 300                         status = "disabled";
 301                 };
 302
 303                 gpio0: gpio@2300000 {
 304                         compatible = "fsl,ls1088a-gpio", "fsl,qoriq-gpio";
 305                         reg = <0x0 0x2300000 0x0 0x10000>;
 306                         interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>;
 307                         little-endian;
 308                         gpio-controller;
 309                         #gpio-cells = <2>;
 310                         interrupt-controller;
 311                         #interrupt-cells = <2>;
 312                 };
 313
 314                 gpio1: gpio@2310000 {
 315                         compatible = "fsl,ls1088a-gpio", "fsl,qoriq-gpio";
 316                         reg = <0x0 0x2310000 0x0 0x10000>;
 317                         interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>;
 318                         little-endian;
 319                         gpio-controller;
 320                         #gpio-cells = <2>;
 321                         interrupt-controller;
 322                         #interrupt-cells = <2>;
 323                 };
 324
 325                 gpio2: gpio@2320000 {
 326                         compatible = "fsl,ls1088a-gpio", "fsl,qoriq-gpio";
 327                         reg = <0x0 0x2320000 0x0 0x10000>;
 328                         interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>;
 329                         little-endian;
 330                         gpio-controller;
 331                         #gpio-cells = <2>;
 332                         interrupt-controller;
 333                         #interrupt-cells = <2>;
 334                 };
 335
 336                 gpio3: gpio@2330000 {
 337                         compatible = "fsl,ls1088a-gpio", "fsl,qoriq-gpio";
 338                         reg = <0x0 0x2330000 0x0 0x10000>;
 339                         interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>;
 340                         little-endian;
 341                         gpio-controller;
 342                         #gpio-cells = <2>;
 343                         interrupt-controller;
 344                         #interrupt-cells = <2>;
 345                 };
 346
 347                 ifc: ifc@2240000 {
 348                         compatible = "fsl,ifc", "simple-bus";
 349                         reg = <0x0 0x2240000 0x0 0x20000>;
 350                         interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>;
 351                         little-endian;
 352                         #address-cells = <2>;
 353                         #size-cells = <1>;
 354                         status = "disabled";
 355                 };
 356
 357                 i2c0: i2c@2000000 {
 358                         compatible = "fsl,vf610-i2c";
 359                         #address-cells = <1>;
 360                         #size-cells = <0>;
 361                         reg = <0x0 0x2000000 0x0 0x10000>;
 362                         interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
 363                         clocks = <&clockgen 4 7>;
 364                         status = "disabled";
 365                 };
 366
 367                 i2c1: i2c@2010000 {
 368                         compatible = "fsl,vf610-i2c";
 369                         #address-cells = <1>;
 370                         #size-cells = <0>;
 371                         reg = <0x0 0x2010000 0x0 0x10000>;
 372                         interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
 373                         clocks = <&clockgen 4 7>;
 374                         status = "disabled";
 375                 };
 376
 377                 i2c2: i2c@2020000 {
 378                         compatible = "fsl,vf610-i2c";
 379                         #address-cells = <1>;
 380                         #size-cells = <0>;
 381                         reg = <0x0 0x2020000 0x0 0x10000>;
 382                         interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>;
 383                         clocks = <&clockgen 4 7>;
 384                         status = "disabled";
 385                 };
 386
 387                 i2c3: i2c@2030000 {
 388                         compatible = "fsl,vf610-i2c";
 389                         #address-cells = <1>;
 390                         #size-cells = <0>;
 391                         reg = <0x0 0x2030000 0x0 0x10000>;
 392                         interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>;
 393                         clocks = <&clockgen 4 7>;
 394                         status = "disabled";
 395                 };
 396
 397                 qspi: spi@20c0000 {
 398                         compatible = "fsl,ls2080a-qspi";
 399                         #address-cells = <1>;
 400                         #size-cells = <0>;
 401                         reg = <0x0 0x20c0000 0x0 0x10000>,
 402                               <0x0 0x20000000 0x0 0x10000000>;
 403                         reg-names = "QuadSPI", "QuadSPI-memory";
 404                         interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 405                         clock-names = "qspi_en", "qspi";
 406                         clocks = <&clockgen 4 3>, <&clockgen 4 3>;
 407                         status = "disabled";
 408                 };
 409
 410                 esdhc: esdhc@2140000 {
 411                         compatible = "fsl,ls1088a-esdhc", "fsl,esdhc";
 412                         reg = <0x0 0x2140000 0x0 0x10000>;
 413                         interrupts = <0 28 0x4>; /* Level high type */
 414                         clock-frequency = <0>;
 415                         clocks = <&clockgen 2 1>;
 416                         voltage-ranges = <1800 1800 3300 3300>;
 417                         sdhci,auto-cmd12;
 418                         little-endian;
 419                         bus-width = <4>;
 420                         status = "disabled";
 421                 };
 422
 423                 usb0: usb3@3100000 {
 424                         compatible = "snps,dwc3";
 425                         reg = <0x0 0x3100000 0x0 0x10000>;
 426                         interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>;
 427                         dr_mode = "host";
 428                         snps,quirk-frame-length-adjustment = <0x20>;
 429                         snps,dis_rxdet_inp3_quirk;
 430                         snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
 431                         status = "disabled";
 432                 };
 433
 434                 usb1: usb3@3110000 {
 435                         compatible = "snps,dwc3";
 436                         reg = <0x0 0x3110000 0x0 0x10000>;
 437                         interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>;
 438                         dr_mode = "host";
 439                         snps,quirk-frame-length-adjustment = <0x20>;
 440                         snps,dis_rxdet_inp3_quirk;
 441                         status = "disabled";
 442                 };
 443
 444                 sata: sata@3200000 {
 445                         compatible = "fsl,ls1088a-ahci";
 446                         reg = <0x0 0x3200000 0x0 0x10000>,
 447                                 <0x7 0x100520 0x0 0x4>;
 448                         reg-names = "ahci", "sata-ecc";
 449                         interrupts = <0 133 IRQ_TYPE_LEVEL_HIGH>;
 450                         clocks = <&clockgen 4 3>;
 451                         dma-coherent;
 452                         status = "disabled";
 453                 };
 454
 455                 crypto: crypto@8000000 {
 456                         compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
 457                         fsl,sec-era = <8>;
 458                         #address-cells = <1>;
 459                         #size-cells = <1>;
 460                         ranges = <0x0 0x00 0x8000000 0x100000>;
 461                         reg = <0x00 0x8000000 0x0 0x100000>;
 462                         interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
 463                         dma-coherent;
 464
 465                         sec_jr0: jr@10000 {
 466                                 compatible = "fsl,sec-v5.0-job-ring",
 467                                              "fsl,sec-v4.0-job-ring";
 468                                 reg        = <0x10000 0x10000>;
 469                                 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
 470                         };
 471
 472                         sec_jr1: jr@20000 {
 473                                 compatible = "fsl,sec-v5.0-job-ring",
 474                                              "fsl,sec-v4.0-job-ring";
 475                                 reg        = <0x20000 0x10000>;
 476                                 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
 477                         };
 478
 479                         sec_jr2: jr@30000 {
 480                                 compatible = "fsl,sec-v5.0-job-ring",
 481                                              "fsl,sec-v4.0-job-ring";
 482                                 reg        = <0x30000 0x10000>;
 483                                 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
 484                         };
 485
 486                         sec_jr3: jr@40000 {
 487                                 compatible = "fsl,sec-v5.0-job-ring",
 488                                              "fsl,sec-v4.0-job-ring";
 489                                 reg        = <0x40000 0x10000>;
 490                                 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
 491                         };
 492                 };
 493
 494                 pcie1: pcie@3400000 {
 495                         compatible = "fsl,ls1088a-pcie";
 496                         reg = <0x00 0x03400000 0x0 0x00100000   /* controller registers */
 497                                0x20 0x00000000 0x0 0x00002000>; /* configuration space */
 498                         reg-names = "regs", "config";
 499                         interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
 500                         interrupt-names = "aer";
 501                         #address-cells = <3>;
 502                         #size-cells = <2>;
 503                         device_type = "pci";
 504                         dma-coherent;
 505                         num-viewport = <256>;
 506                         bus-range = <0x0 0xff>;
 507                         ranges = <0x81000000 0x0 0x00000000 0x20 0x00010000 0x0 0x00010000   /* downstream I/O */
 508                                   0x82000000 0x0 0x40000000 0x20 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
 509                         msi-parent = <&its>;
 510                         #interrupt-cells = <1>;
 511                         interrupt-map-mask = <0 0 0 7>;
 512                         interrupt-map = <0000 0 0 1 &gic 0 0 0 109 IRQ_TYPE_LEVEL_HIGH>,
 513                                         <0000 0 0 2 &gic 0 0 0 110 IRQ_TYPE_LEVEL_HIGH>,
 514                                         <0000 0 0 3 &gic 0 0 0 111 IRQ_TYPE_LEVEL_HIGH>,
 515                                         <0000 0 0 4 &gic 0 0 0 112 IRQ_TYPE_LEVEL_HIGH>;
 516                         iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
 517                         status = "disabled";
 518                 };
 519
 520                 pcie2: pcie@3500000 {
 521                         compatible = "fsl,ls1088a-pcie";
 522                         reg = <0x00 0x03500000 0x0 0x00100000   /* controller registers */
 523                                0x28 0x00000000 0x0 0x00002000>; /* configuration space */
 524                         reg-names = "regs", "config";
 525                         interrupts = <0 113 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
 526                         interrupt-names = "aer";
 527                         #address-cells = <3>;
 528                         #size-cells = <2>;
 529                         device_type = "pci";
 530                         dma-coherent;
 531                         num-viewport = <6>;
 532                         bus-range = <0x0 0xff>;
 533                         ranges = <0x81000000 0x0 0x00000000 0x28 0x00010000 0x0 0x00010000   /* downstream I/O */
 534                                   0x82000000 0x0 0x40000000 0x28 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
 535                         msi-parent = <&its>;
 536                         #interrupt-cells = <1>;
 537                         interrupt-map-mask = <0 0 0 7>;
 538                         interrupt-map = <0000 0 0 1 &gic 0 0 0 114 IRQ_TYPE_LEVEL_HIGH>,
 539                                         <0000 0 0 2 &gic 0 0 0 115 IRQ_TYPE_LEVEL_HIGH>,
 540                                         <0000 0 0 3 &gic 0 0 0 116 IRQ_TYPE_LEVEL_HIGH>,
 541                                         <0000 0 0 4 &gic 0 0 0 117 IRQ_TYPE_LEVEL_HIGH>;
 542                         iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
 543                         status = "disabled";
 544                 };
 545
 546                 pcie3: pcie@3600000 {
 547                         compatible = "fsl,ls1088a-pcie";
 548                         reg = <0x00 0x03600000 0x0 0x00100000   /* controller registers */
 549                                0x30 0x00000000 0x0 0x00002000>; /* configuration space */
 550                         reg-names = "regs", "config";
 551                         interrupts = <0 118 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
 552                         interrupt-names = "aer";
 553                         #address-cells = <3>;
 554                         #size-cells = <2>;
 555                         device_type = "pci";
 556                         dma-coherent;
 557                         num-viewport = <6>;
 558                         bus-range = <0x0 0xff>;
 559                         ranges = <0x81000000 0x0 0x00000000 0x30 0x00010000 0x0 0x00010000   /* downstream I/O */
 560                                   0x82000000 0x0 0x40000000 0x30 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
 561                         msi-parent = <&its>;
 562                         #interrupt-cells = <1>;
 563                         interrupt-map-mask = <0 0 0 7>;
 564                         interrupt-map = <0000 0 0 1 &gic 0 0 0 119 IRQ_TYPE_LEVEL_HIGH>,
 565                                         <0000 0 0 2 &gic 0 0 0 120 IRQ_TYPE_LEVEL_HIGH>,
 566                                         <0000 0 0 3 &gic 0 0 0 121 IRQ_TYPE_LEVEL_HIGH>,
 567                                         <0000 0 0 4 &gic 0 0 0 122 IRQ_TYPE_LEVEL_HIGH>;
 568                         iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
 569                         status = "disabled";
 570                 };
 571
 572                 smmu: iommu@5000000 {
 573                         compatible = "arm,mmu-500";
 574                         reg = <0 0x5000000 0 0x800000>;
 575                         #iommu-cells = <1>;
 576                         stream-match-mask = <0x7C00>;
 577                         #global-interrupts = <12>;
 578                                      // global secure fault
 579                         interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
 580                                      // combined secure
 581                                      <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
 582                                      // global non-secure fault
 583                                      <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
 584                                      // combined non-secure
 585                                      <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
 586                                      // performance counter interrupts 0-7
 587                                      <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
 588                                      <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
 589                                      <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
 590                                      <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
 591                                      <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
 592                                      <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
 593                                      <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
 594                                      <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
 595                                      // per context interrupt, 64 interrupts
 596                                      <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
 597                                      <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
 598                                      <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
 599                                      <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
 600                                      <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
 601                                      <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
 602                                      <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
 603                                      <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
 604                                      <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
 605                                      <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
 606                                      <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>,
 607                                      <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
 608                                      <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
 609                                      <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
 610                                      <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
 611                                      <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
 612                                      <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
 613                                      <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
 614                                      <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
 615                                      <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
 616                                      <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>,
 617                                      <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
 618                                      <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
 619                                      <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
 620                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 621                                      <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>,
 622                                      <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>,
 623                                      <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>,
 624                                      <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>,
 625                                      <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>,
 626                                      <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>,
 627                                      <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>,
 628                                      <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>,
 629                                      <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>,
 630                                      <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>,
 631                                      <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
 632                                      <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
 633                                      <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
 634                                      <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
 635                                      <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
 636                                      <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
 637                                      <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
 638                                      <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
 639                                      <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
 640                                      <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
 641                                      <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
 642                                      <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
 643                                      <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>,
 644                                      <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>,
 645                                      <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>,
 646                                      <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
 647                                      <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
 648                                      <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
 649                                      <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
 650                                      <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
 651                                      <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
 652                                      <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
 653                                      <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
 654                                      <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
 655                                      <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
 656                                      <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
 657                                      <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
 658                                      <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
 659                                      <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
 660                 };
 661
 662                 console@8340020 {
 663                         compatible = "fsl,dpaa2-console";
 664                         reg = <0x00000000 0x08340020 0 0x2>;
 665                 };
 666
 667                 ptp-timer@8b95000 {
 668                         compatible = "fsl,dpaa2-ptp";
 669                         reg = <0x0 0x8b95000 0x0 0x100>;
 670                         clocks = <&clockgen 4 0>;
 671                         little-endian;
 672                         fsl,extts-fifo;
 673                 };
 674
 675                 cluster1_core0_watchdog: wdt@c000000 {
 676                         compatible = "arm,sp805-wdt", "arm,primecell";
 677                         reg = <0x0 0xc000000 0x0 0x1000>;
 678                         clocks = <&clockgen 4 15>, <&clockgen 4 15>;
 679                         clock-names = "wdog_clk", "apb_pclk";
 680                 };
 681
 682                 cluster1_core1_watchdog: wdt@c010000 {
 683                         compatible = "arm,sp805-wdt", "arm,primecell";
 684                         reg = <0x0 0xc010000 0x0 0x1000>;
 685                         clocks = <&clockgen 4 15>, <&clockgen 4 15>;
 686                         clock-names = "wdog_clk", "apb_pclk";
 687                 };
 688
 689                 cluster1_core2_watchdog: wdt@c020000 {
 690                         compatible = "arm,sp805-wdt", "arm,primecell";
 691                         reg = <0x0 0xc020000 0x0 0x1000>;
 692                         clocks = <&clockgen 4 15>, <&clockgen 4 15>;
 693                         clock-names = "wdog_clk", "apb_pclk";
 694                 };
 695
 696                 cluster1_core3_watchdog: wdt@c030000 {
 697                         compatible = "arm,sp805-wdt", "arm,primecell";
 698                         reg = <0x0 0xc030000 0x0 0x1000>;
 699                         clocks = <&clockgen 4 15>, <&clockgen 4 15>;
 700                         clock-names = "wdog_clk", "apb_pclk";
 701                 };
 702
 703                 cluster2_core0_watchdog: wdt@c100000 {
 704                         compatible = "arm,sp805-wdt", "arm,primecell";
 705                         reg = <0x0 0xc100000 0x0 0x1000>;
 706                         clocks = <&clockgen 4 15>, <&clockgen 4 15>;
 707                         clock-names = "wdog_clk", "apb_pclk";
 708                 };
 709
 710                 cluster2_core1_watchdog: wdt@c110000 {
 711                         compatible = "arm,sp805-wdt", "arm,primecell";
 712                         reg = <0x0 0xc110000 0x0 0x1000>;
 713                         clocks = <&clockgen 4 15>, <&clockgen 4 15>;
 714                         clock-names = "wdog_clk", "apb_pclk";
 715                 };
 716
 717                 cluster2_core2_watchdog: wdt@c120000 {
 718                         compatible = "arm,sp805-wdt", "arm,primecell";
 719                         reg = <0x0 0xc120000 0x0 0x1000>;
 720                         clocks = <&clockgen 4 15>, <&clockgen 4 15>;
 721                         clock-names = "wdog_clk", "apb_pclk";
 722                 };
 723
 724                 cluster2_core3_watchdog: wdt@c130000 {
 725                         compatible = "arm,sp805-wdt", "arm,primecell";
 726                         reg = <0x0 0xc130000 0x0 0x1000>;
 727                         clocks = <&clockgen 4 15>, <&clockgen 4 15>;
 728                         clock-names = "wdog_clk", "apb_pclk";
 729                 };
 730
 731                 fsl_mc: fsl-mc@80c000000 {
 732                         compatible = "fsl,qoriq-mc";
 733                         reg = <0x00000008 0x0c000000 0 0x40>,    /* MC portal base */
 734                               <0x00000000 0x08340000 0 0x40000>; /* MC control reg */
 735                         msi-parent = <&its>;
 736                         iommu-map = <0 &smmu 0 0>;      /* This is fixed-up by u-boot */
 737                         dma-coherent;
 738                         #address-cells = <3>;
 739                         #size-cells = <1>;
 740
 741                         /*
 742                          * Region type 0x0 - MC portals
 743                          * Region type 0x1 - QBMAN portals
 744                          */
 745                         ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000
 746                                   0x1 0x0 0x0 0x8 0x18000000 0x8000000>;
 747
 748                         dpmacs {
 749                                 #address-cells = <1>;
 750                                 #size-cells = <0>;
 751
 752                                 dpmac1: dpmac@1 {
 753                                         compatible = "fsl,qoriq-mc-dpmac";
 754                                         reg = <1>;
 755                                 };
 756
 757                                 dpmac2: dpmac@2 {
 758                                         compatible = "fsl,qoriq-mc-dpmac";
 759                                         reg = <2>;
 760                                 };
 761
 762                                 dpmac3: dpmac@3 {
 763                                         compatible = "fsl,qoriq-mc-dpmac";
 764                                         reg = <3>;
 765                                 };
 766
 767                                 dpmac4: dpmac@4 {
 768                                         compatible = "fsl,qoriq-mc-dpmac";
 769                                         reg = <4>;
 770                                 };
 771
 772                                 dpmac5: dpmac@5 {
 773                                         compatible = "fsl,qoriq-mc-dpmac";
 774                                         reg = <5>;
 775                                 };
 776
 777                                 dpmac6: dpmac@6 {
 778                                         compatible = "fsl,qoriq-mc-dpmac";
 779                                         reg = <6>;
 780                                 };
 781
 782                                 dpmac7: dpmac@7 {
 783                                         compatible = "fsl,qoriq-mc-dpmac";
 784                                         reg = <7>;
 785                                 };
 786
 787                                 dpmac8: dpmac@8 {
 788                                         compatible = "fsl,qoriq-mc-dpmac";
 789                                         reg = <8>;
 790                                 };
 791
 792                                 dpmac9: dpmac@9 {
 793                                         compatible = "fsl,qoriq-mc-dpmac";
 794                                         reg = <9>;
 795                                 };
 796
 797                                 dpmac10: dpmac@a {
 798                                         compatible = "fsl,qoriq-mc-dpmac";
 799                                         reg = <0xa>;
 800                                 };
 801                         };
 802                 };
 803
 804                 rcpm: power-controller@1e34040 {
 805                         compatible = "fsl,ls1088a-rcpm", "fsl,qoriq-rcpm-2.1+";
 806                         reg = <0x0 0x1e34040 0x0 0x18>;
 807                         #fsl,rcpm-wakeup-cells = <6>;
 808                         little-endian;
 809                 };
 810
 811                 ftm_alarm0: timer@2800000 {
 812                         compatible = "fsl,ls1088a-ftm-alarm";
 813                         reg = <0x0 0x2800000 0x0 0x10000>;
 814                         fsl,rcpm-wakeup = <&rcpm 0x0 0x0 0x0 0x0 0x4000 0x0>;
 815                         interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 816                 };
 817         };
 818
 819         firmware {
 820                 optee {
 821                         compatible = "linaro,optee-tz";
 822                         method = "smc";
 823                 };
 824         };
 825 };