arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Device Tree Include file for NXP Layerscape-1046A family SoC.
   4  *
   5  * Copyright 2016 Freescale Semiconductor, Inc.
   6  * Copyright 2018, 2020 NXP
   7  *
   8  * Mingkai Hu <mingkai.hu@nxp.com>
   9  */
  10
  11 #include <dt-bindings/interrupt-controller/arm-gic.h>
  12 #include <dt-bindings/thermal/thermal.h>
  13
  14 / {
  15         compatible = "fsl,ls1046a";
  16         interrupt-parent = <&gic>;
  17         #address-cells = <2>;
  18         #size-cells = <2>;
  19
  20         aliases {
  21                 crypto = &crypto;
  22                 fman0 = &fman0;
  23                 ethernet0 = &enet0;
  24                 ethernet1 = &enet1;
  25                 ethernet2 = &enet2;
  26                 ethernet3 = &enet3;
  27                 ethernet4 = &enet4;
  28                 ethernet5 = &enet5;
  29                 ethernet6 = &enet6;
  30                 ethernet7 = &enet7;
  31                 rtc1 = &ftm_alarm0;
  32         };
  33
  34         cpus {
  35                 #address-cells = <1>;
  36                 #size-cells = <0>;
  37
  38                 cpu0: cpu@0 {
  39                         device_type = "cpu";
  40                         compatible = "arm,cortex-a72";
  41                         reg = <0x0>;
  42                         clocks = <&clockgen 1 0>;
  43                         next-level-cache = <&l2>;
  44                         cpu-idle-states = <&CPU_PH20>;
  45                         #cooling-cells = <2>;
  46                 };
  47
  48                 cpu1: cpu@1 {
  49                         device_type = "cpu";
  50                         compatible = "arm,cortex-a72";
  51                         reg = <0x1>;
  52                         clocks = <&clockgen 1 0>;
  53                         next-level-cache = <&l2>;
  54                         cpu-idle-states = <&CPU_PH20>;
  55                         #cooling-cells = <2>;
  56                 };
  57
  58                 cpu2: cpu@2 {
  59                         device_type = "cpu";
  60                         compatible = "arm,cortex-a72";
  61                         reg = <0x2>;
  62                         clocks = <&clockgen 1 0>;
  63                         next-level-cache = <&l2>;
  64                         cpu-idle-states = <&CPU_PH20>;
  65                         #cooling-cells = <2>;
  66                 };
  67
  68                 cpu3: cpu@3 {
  69                         device_type = "cpu";
  70                         compatible = "arm,cortex-a72";
  71                         reg = <0x3>;
  72                         clocks = <&clockgen 1 0>;
  73                         next-level-cache = <&l2>;
  74                         cpu-idle-states = <&CPU_PH20>;
  75                         #cooling-cells = <2>;
  76                 };
  77
  78                 l2: l2-cache {
  79                         compatible = "cache";
  80                 };
  81         };
  82
  83         idle-states {
  84                 /*
  85                  * PSCI node is not added default, U-boot will add missing
  86                  * parts if it determines to use PSCI.
  87                  */
  88                 entry-method = "psci";
  89
  90                 CPU_PH20: cpu-ph20 {
  91                         compatible = "arm,idle-state";
  92                         idle-state-name = "PH20";
  93                         arm,psci-suspend-param = <0x0>;
  94                         entry-latency-us = <1000>;
  95                         exit-latency-us = <1000>;
  96                         min-residency-us = <3000>;
  97                 };
  98         };
  99
 100         memory@80000000 {
 101                 device_type = "memory";
 102                 /* Real size will be filled by bootloader */
 103                 reg = <0x0 0x80000000 0x0 0x0>;
 104         };
 105
 106         sysclk: sysclk {
 107                 compatible = "fixed-clock";
 108                 #clock-cells = <0>;
 109                 clock-frequency = <100000000>;
 110                 clock-output-names = "sysclk";
 111         };
 112
 113         reboot {
 114                 compatible ="syscon-reboot";
 115                 regmap = <&dcfg>;
 116                 offset = <0xb0>;
 117                 mask = <0x02>;
 118         };
 119
 120         thermal-zones {
 121                 ddr-controller {
 122                         polling-delay-passive = <1000>;
 123                         polling-delay = <5000>;
 124                         thermal-sensors = <&tmu 0>;
 125
 126                         trips {
 127                                 ddr-ctrler-alert {
 128                                         temperature = <85000>;
 129                                         hysteresis = <2000>;
 130                                         type = "passive";
 131                                 };
 132
 133                                 ddr-ctrler-crit {
 134                                         temperature = <95000>;
 135                                         hysteresis = <2000>;
 136                                         type = "critical";
 137                                 };
 138                         };
 139                 };
 140
 141                 serdes {
 142                         polling-delay-passive = <1000>;
 143                         polling-delay = <5000>;
 144                         thermal-sensors = <&tmu 1>;
 145
 146                         trips {
 147                                 serdes-alert {
 148                                         temperature = <85000>;
 149                                         hysteresis = <2000>;
 150                                         type = "passive";
 151                                 };
 152
 153                                 serdes-crit {
 154                                         temperature = <95000>;
 155                                         hysteresis = <2000>;
 156                                         type = "critical";
 157                                 };
 158                         };
 159                 };
 160
 161                 fman {
 162                         polling-delay-passive = <1000>;
 163                         polling-delay = <5000>;
 164                         thermal-sensors = <&tmu 2>;
 165
 166                         trips {
 167                                 fman-alert {
 168                                         temperature = <85000>;
 169                                         hysteresis = <2000>;
 170                                         type = "passive";
 171                                 };
 172
 173                                 fman-crit {
 174                                         temperature = <95000>;
 175                                         hysteresis = <2000>;
 176                                         type = "critical";
 177                                 };
 178                         };
 179                 };
 180
 181                 core-cluster {
 182                         polling-delay-passive = <1000>;
 183                         polling-delay = <5000>;
 184                         thermal-sensors = <&tmu 3>;
 185
 186                         trips {
 187                                 core_cluster_alert: core-cluster-alert {
 188                                         temperature = <85000>;
 189                                         hysteresis = <2000>;
 190                                         type = "passive";
 191                                 };
 192
 193                                 core_cluster_crit: core-cluster-crit {
 194                                         temperature = <95000>;
 195                                         hysteresis = <2000>;
 196                                         type = "critical";
 197                                 };
 198                         };
 199
 200                         cooling-maps {
 201                                 map0 {
 202                                         trip = <&core_cluster_alert>;
 203                                         cooling-device =
 204                                                 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 205                                                 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 206                                                 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 207                                                 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 208                                 };
 209                         };
 210                 };
 211
 212                 sec {
 213                         polling-delay-passive = <1000>;
 214                         polling-delay = <5000>;
 215                         thermal-sensors = <&tmu 4>;
 216
 217                         trips {
 218                                 sec-alert {
 219                                         temperature = <85000>;
 220                                         hysteresis = <2000>;
 221                                         type = "passive";
 222                                 };
 223
 224                                 sec-crit {
 225                                         temperature = <95000>;
 226                                         hysteresis = <2000>;
 227                                         type = "critical";
 228                                 };
 229                         };
 230                 };
 231         };
 232
 233         timer {
 234                 compatible = "arm,armv8-timer";
 235                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(0xf) |
 236                                           IRQ_TYPE_LEVEL_LOW)>,
 237                              <GIC_PPI 14 (GIC_CPU_MASK_RAW(0xf) |
 238                                           IRQ_TYPE_LEVEL_LOW)>,
 239                              <GIC_PPI 11 (GIC_CPU_MASK_RAW(0xf) |
 240                                           IRQ_TYPE_LEVEL_LOW)>,
 241                              <GIC_PPI 10 (GIC_CPU_MASK_RAW(0xf) |
 242                                           IRQ_TYPE_LEVEL_LOW)>;
 243         };
 244
 245         pmu {
 246                 compatible = "arm,cortex-a72-pmu";
 247                 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
 248                              <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
 249                              <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
 250                              <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 251                 interrupt-affinity = <&cpu0>,
 252                                      <&cpu1>,
 253                                      <&cpu2>,
 254                                      <&cpu3>;
 255         };
 256
 257         gic: interrupt-controller@1400000 {
 258                 compatible = "arm,gic-400";
 259                 #interrupt-cells = <3>;
 260                 interrupt-controller;
 261                 reg = <0x0 0x1410000 0 0x10000>, /* GICD */
 262                       <0x0 0x1420000 0 0x20000>, /* GICC */
 263                       <0x0 0x1440000 0 0x20000>, /* GICH */
 264                       <0x0 0x1460000 0 0x20000>; /* GICV */
 265                 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_RAW(0xf) |
 266                                          IRQ_TYPE_LEVEL_LOW)>;
 267         };
 268
 269         soc: soc {
 270                 compatible = "simple-bus";
 271                 #address-cells = <2>;
 272                 #size-cells = <2>;
 273                 ranges;
 274
 275                 ddr: memory-controller@1080000 {
 276                         compatible = "fsl,qoriq-memory-controller";
 277                         reg = <0x0 0x1080000 0x0 0x1000>;
 278                         interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
 279                         big-endian;
 280                 };
 281
 282                 ifc: ifc@1530000 {
 283                         compatible = "fsl,ifc", "simple-bus";
 284                         reg = <0x0 0x1530000 0x0 0x10000>;
 285                         interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
 286                         status = "disabled";
 287                 };
 288
 289                 qspi: spi@1550000 {
 290                         compatible = "fsl,ls1021a-qspi";
 291                         #address-cells = <1>;
 292                         #size-cells = <0>;
 293                         reg = <0x0 0x1550000 0x0 0x10000>,
 294                                 <0x0 0x40000000 0x0 0x10000000>;
 295                         reg-names = "QuadSPI", "QuadSPI-memory";
 296                         interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
 297                         clock-names = "qspi_en", "qspi";
 298                         clocks = <&clockgen 4 1>, <&clockgen 4 1>;
 299                         status = "disabled";
 300                 };
 301
 302                 esdhc: esdhc@1560000 {
 303                         compatible = "fsl,ls1046a-esdhc", "fsl,esdhc";
 304                         reg = <0x0 0x1560000 0x0 0x10000>;
 305                         interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 306                         clocks = <&clockgen 2 1>;
 307                         voltage-ranges = <1800 1800 3300 3300>;
 308                         sdhci,auto-cmd12;
 309                         big-endian;
 310                         bus-width = <4>;
 311                 };
 312
 313                 scfg: scfg@1570000 {
 314                         compatible = "fsl,ls1046a-scfg", "syscon";
 315                         reg = <0x0 0x1570000 0x0 0x10000>;
 316                         big-endian;
 317                 };
 318
 319                 crypto: crypto@1700000 {
 320                         compatible = "fsl,sec-v5.4", "fsl,sec-v5.0",
 321                                      "fsl,sec-v4.0";
 322                         fsl,sec-era = <8>;
 323                         #address-cells = <1>;
 324                         #size-cells = <1>;
 325                         ranges = <0x0 0x00 0x1700000 0x100000>;
 326                         reg = <0x00 0x1700000 0x0 0x100000>;
 327                         interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 328
 329                         sec_jr0: jr@10000 {
 330                                 compatible = "fsl,sec-v5.4-job-ring",
 331                                              "fsl,sec-v5.0-job-ring",
 332                                              "fsl,sec-v4.0-job-ring";
 333                                 reg        = <0x10000 0x10000>;
 334                                 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 335                         };
 336
 337                         sec_jr1: jr@20000 {
 338                                 compatible = "fsl,sec-v5.4-job-ring",
 339                                              "fsl,sec-v5.0-job-ring",
 340                                              "fsl,sec-v4.0-job-ring";
 341                                 reg        = <0x20000 0x10000>;
 342                                 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 343                         };
 344
 345                         sec_jr2: jr@30000 {
 346                                 compatible = "fsl,sec-v5.4-job-ring",
 347                                              "fsl,sec-v5.0-job-ring",
 348                                              "fsl,sec-v4.0-job-ring";
 349                                 reg        = <0x30000 0x10000>;
 350                                 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 351                         };
 352
 353                         sec_jr3: jr@40000 {
 354                                 compatible = "fsl,sec-v5.4-job-ring",
 355                                              "fsl,sec-v5.0-job-ring",
 356                                              "fsl,sec-v4.0-job-ring";
 357                                 reg        = <0x40000 0x10000>;
 358                                 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 359                         };
 360                 };
 361
 362                 qman: qman@1880000 {
 363                         compatible = "fsl,qman";
 364                         reg = <0x0 0x1880000 0x0 0x10000>;
 365                         interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 366                         memory-region = <&qman_fqd &qman_pfdr>;
 367
 368                 };
 369
 370                 bman: bman@1890000 {
 371                         compatible = "fsl,bman";
 372                         reg = <0x0 0x1890000 0x0 0x10000>;
 373                         interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 374                         memory-region = <&bman_fbpr>;
 375
 376                 };
 377
 378                 qportals: qman-portals@500000000 {
 379                         ranges = <0x0 0x5 0x00000000 0x8000000>;
 380                 };
 381
 382                 bportals: bman-portals@508000000 {
 383                         ranges = <0x0 0x5 0x08000000 0x8000000>;
 384                 };
 385
 386                 dcfg: dcfg@1ee0000 {
 387                         compatible = "fsl,ls1046a-dcfg", "syscon";
 388                         reg = <0x0 0x1ee0000 0x0 0x10000>;
 389                         big-endian;
 390                 };
 391
 392                 clockgen: clocking@1ee1000 {
 393                         compatible = "fsl,ls1046a-clockgen";
 394                         reg = <0x0 0x1ee1000 0x0 0x1000>;
 395                         #clock-cells = <2>;
 396                         clocks = <&sysclk>;
 397                 };
 398
 399                 tmu: tmu@1f00000 {
 400                         compatible = "fsl,qoriq-tmu";
 401                         reg = <0x0 0x1f00000 0x0 0x10000>;
 402                         interrupts = <0 33 0x4>;
 403                         fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x70062>;
 404                         fsl,tmu-calibration =
 405                                 /* Calibration data group 1 */
 406                                 <0x00000000 0x00000023
 407                                 0x00000001 0x00000029
 408                                 0x00000002 0x0000002f
 409                                 0x00000003 0x00000036
 410                                 0x00000004 0x0000003c
 411                                 0x00000005 0x00000042
 412                                 0x00000006 0x00000049
 413                                 0x00000007 0x0000004f
 414                                 0x00000008 0x00000055
 415                                 0x00000009 0x0000005c
 416                                 0x0000000a 0x00000062
 417                                 0x0000000b 0x00000068
 418                                 /* Calibration data group 2 */
 419                                 0x00010000 0x00000022
 420                                 0x00010001 0x0000002a
 421                                 0x00010002 0x00000032
 422                                 0x00010003 0x0000003a
 423                                 0x00010004 0x00000042
 424                                 0x00010005 0x0000004a
 425                                 0x00010006 0x00000052
 426                                 0x00010007 0x0000005a
 427                                 0x00010008 0x00000062
 428                                 0x00010009 0x0000006a
 429                                 /* Calibration data group 3 */
 430                                 0x00020000 0x00000021
 431                                 0x00020001 0x0000002b
 432                                 0x00020002 0x00000035
 433                                 0x00020003 0x0000003e
 434                                 0x00020004 0x00000048
 435                                 0x00020005 0x00000052
 436                                 0x00020006 0x0000005c
 437                                 /* Calibration data group 4 */
 438                                 0x00030000 0x00000011
 439                                 0x00030001 0x0000001a
 440                                 0x00030002 0x00000024
 441                                 0x00030003 0x0000002e
 442                                 0x00030004 0x00000038
 443                                 0x00030005 0x00000042
 444                                 0x00030006 0x0000004c
 445                                 0x00030007 0x00000056>;
 446                         big-endian;
 447                         #thermal-sensor-cells = <1>;
 448                 };
 449
 450                 dspi: spi@2100000 {
 451                         compatible = "fsl,ls1021a-v1.0-dspi";
 452                         #address-cells = <1>;
 453                         #size-cells = <0>;
 454                         reg = <0x0 0x2100000 0x0 0x10000>;
 455                         interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 456                         clock-names = "dspi";
 457                         clocks = <&clockgen 4 1>;
 458                         spi-num-chipselects = <5>;
 459                         big-endian;
 460                         status = "disabled";
 461                 };
 462
 463                 i2c0: i2c@2180000 {
 464                         compatible = "fsl,vf610-i2c";
 465                         #address-cells = <1>;
 466                         #size-cells = <0>;
 467                         reg = <0x0 0x2180000 0x0 0x10000>;
 468                         interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 469                         clocks = <&clockgen 4 1>;
 470                         dmas = <&edma0 1 39>,
 471                                <&edma0 1 38>;
 472                         dma-names = "tx", "rx";
 473                         status = "disabled";
 474                 };
 475
 476                 i2c1: i2c@2190000 {
 477                         compatible = "fsl,vf610-i2c";
 478                         #address-cells = <1>;
 479                         #size-cells = <0>;
 480                         reg = <0x0 0x2190000 0x0 0x10000>;
 481                         interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 482                         clocks = <&clockgen 4 1>;
 483                         status = "disabled";
 484                 };
 485
 486                 i2c2: i2c@21a0000 {
 487                         compatible = "fsl,vf610-i2c";
 488                         #address-cells = <1>;
 489                         #size-cells = <0>;
 490                         reg = <0x0 0x21a0000 0x0 0x10000>;
 491                         interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 492                         clocks = <&clockgen 4 1>;
 493                         status = "disabled";
 494                 };
 495
 496                 i2c3: i2c@21b0000 {
 497                         compatible = "fsl,vf610-i2c";
 498                         #address-cells = <1>;
 499                         #size-cells = <0>;
 500                         reg = <0x0 0x21b0000 0x0 0x10000>;
 501                         interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 502                         clocks = <&clockgen 4 1>;
 503                         status = "disabled";
 504                 };
 505
 506                 duart0: serial@21c0500 {
 507                         compatible = "fsl,ns16550", "ns16550a";
 508                         reg = <0x00 0x21c0500 0x0 0x100>;
 509                         interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
 510                         clocks = <&clockgen 4 1>;
 511                         status = "disabled";
 512                 };
 513
 514                 duart1: serial@21c0600 {
 515                         compatible = "fsl,ns16550", "ns16550a";
 516                         reg = <0x00 0x21c0600 0x0 0x100>;
 517                         interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
 518                         clocks = <&clockgen 4 1>;
 519                         status = "disabled";
 520                 };
 521
 522                 duart2: serial@21d0500 {
 523                         compatible = "fsl,ns16550", "ns16550a";
 524                         reg = <0x0 0x21d0500 0x0 0x100>;
 525                         interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 526                         clocks = <&clockgen 4 1>;
 527                         status = "disabled";
 528                 };
 529
 530                 duart3: serial@21d0600 {
 531                         compatible = "fsl,ns16550", "ns16550a";
 532                         reg = <0x0 0x21d0600 0x0 0x100>;
 533                         interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 534                         clocks = <&clockgen 4 1>;
 535                         status = "disabled";
 536                 };
 537
 538                 gpio0: gpio@2300000 {
 539                         compatible = "fsl,qoriq-gpio";
 540                         reg = <0x0 0x2300000 0x0 0x10000>;
 541                         interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
 542                         gpio-controller;
 543                         #gpio-cells = <2>;
 544                         interrupt-controller;
 545                         #interrupt-cells = <2>;
 546                 };
 547
 548                 gpio1: gpio@2310000 {
 549                         compatible = "fsl,qoriq-gpio";
 550                         reg = <0x0 0x2310000 0x0 0x10000>;
 551                         interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
 552                         gpio-controller;
 553                         #gpio-cells = <2>;
 554                         interrupt-controller;
 555                         #interrupt-cells = <2>;
 556                 };
 557
 558                 gpio2: gpio@2320000 {
 559                         compatible = "fsl,qoriq-gpio";
 560                         reg = <0x0 0x2320000 0x0 0x10000>;
 561                         interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
 562                         gpio-controller;
 563                         #gpio-cells = <2>;
 564                         interrupt-controller;
 565                         #interrupt-cells = <2>;
 566                 };
 567
 568                 gpio3: gpio@2330000 {
 569                         compatible = "fsl,qoriq-gpio";
 570                         reg = <0x0 0x2330000 0x0 0x10000>;
 571                         interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
 572                         gpio-controller;
 573                         #gpio-cells = <2>;
 574                         interrupt-controller;
 575                         #interrupt-cells = <2>;
 576                 };
 577
 578                 lpuart0: serial@2950000 {
 579                         compatible = "fsl,ls1021a-lpuart";
 580                         reg = <0x0 0x2950000 0x0 0x1000>;
 581                         interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
 582                         clocks = <&clockgen 4 0>;
 583                         clock-names = "ipg";
 584                         status = "disabled";
 585                 };
 586
 587                 lpuart1: serial@2960000 {
 588                         compatible = "fsl,ls1021a-lpuart";
 589                         reg = <0x0 0x2960000 0x0 0x1000>;
 590                         interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
 591                         clocks = <&clockgen 4 1>;
 592                         clock-names = "ipg";
 593                         status = "disabled";
 594                 };
 595
 596                 lpuart2: serial@2970000 {
 597                         compatible = "fsl,ls1021a-lpuart";
 598                         reg = <0x0 0x2970000 0x0 0x1000>;
 599                         interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
 600                         clocks = <&clockgen 4 1>;
 601                         clock-names = "ipg";
 602                         status = "disabled";
 603                 };
 604
 605                 lpuart3: serial@2980000 {
 606                         compatible = "fsl,ls1021a-lpuart";
 607                         reg = <0x0 0x2980000 0x0 0x1000>;
 608                         interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
 609                         clocks = <&clockgen 4 1>;
 610                         clock-names = "ipg";
 611                         status = "disabled";
 612                 };
 613
 614                 lpuart4: serial@2990000 {
 615                         compatible = "fsl,ls1021a-lpuart";
 616                         reg = <0x0 0x2990000 0x0 0x1000>;
 617                         interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 618                         clocks = <&clockgen 4 1>;
 619                         clock-names = "ipg";
 620                         status = "disabled";
 621                 };
 622
 623                 lpuart5: serial@29a0000 {
 624                         compatible = "fsl,ls1021a-lpuart";
 625                         reg = <0x0 0x29a0000 0x0 0x1000>;
 626                         interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 627                         clocks = <&clockgen 4 1>;
 628                         clock-names = "ipg";
 629                         status = "disabled";
 630                 };
 631
 632                 wdog0: watchdog@2ad0000 {
 633                         compatible = "fsl,imx21-wdt";
 634                         reg = <0x0 0x2ad0000 0x0 0x10000>;
 635                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 636                         clocks = <&clockgen 4 1>;
 637                         big-endian;
 638                 };
 639
 640                 edma0: edma@2c00000 {
 641                         #dma-cells = <2>;
 642                         compatible = "fsl,vf610-edma";
 643                         reg = <0x0 0x2c00000 0x0 0x10000>,
 644                               <0x0 0x2c10000 0x0 0x10000>,
 645                               <0x0 0x2c20000 0x0 0x10000>;
 646                         interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
 647                                      <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 648                         interrupt-names = "edma-tx", "edma-err";
 649                         dma-channels = <32>;
 650                         big-endian;
 651                         clock-names = "dmamux0", "dmamux1";
 652                         clocks = <&clockgen 4 1>,
 653                                  <&clockgen 4 1>;
 654                 };
 655
 656                 usb0: usb@2f00000 {
 657                         compatible = "snps,dwc3";
 658                         reg = <0x0 0x2f00000 0x0 0x10000>;
 659                         interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 660                         dr_mode = "host";
 661                         snps,quirk-frame-length-adjustment = <0x20>;
 662                         snps,dis_rxdet_inp3_quirk;
 663                         snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
 664                 };
 665
 666                 usb1: usb@3000000 {
 667                         compatible = "snps,dwc3";
 668                         reg = <0x0 0x3000000 0x0 0x10000>;
 669                         interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 670                         dr_mode = "host";
 671                         snps,quirk-frame-length-adjustment = <0x20>;
 672                         snps,dis_rxdet_inp3_quirk;
 673                         snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
 674                 };
 675
 676                 usb2: usb@3100000 {
 677                         compatible = "snps,dwc3";
 678                         reg = <0x0 0x3100000 0x0 0x10000>;
 679                         interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 680                         dr_mode = "host";
 681                         snps,quirk-frame-length-adjustment = <0x20>;
 682                         snps,dis_rxdet_inp3_quirk;
 683                         snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
 684                 };
 685
 686                 sata: sata@3200000 {
 687                         compatible = "fsl,ls1046a-ahci";
 688                         reg = <0x0 0x3200000 0x0 0x10000>,
 689                                 <0x0 0x20140520 0x0 0x4>;
 690                         reg-names = "ahci", "sata-ecc";
 691                         interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
 692                         clocks = <&clockgen 4 1>;
 693                 };
 694
 695                 msi1: msi-controller@1580000 {
 696                         compatible = "fsl,ls1046a-msi";
 697                         msi-controller;
 698                         reg = <0x0 0x1580000 0x0 0x10000>;
 699                         interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
 700                                      <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
 701                                      <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
 702                                      <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
 703                 };
 704
 705                 msi2: msi-controller@1590000 {
 706                         compatible = "fsl,ls1046a-msi";
 707                         msi-controller;
 708                         reg = <0x0 0x1590000 0x0 0x10000>;
 709                         interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
 710                                      <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
 711                                      <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
 712                                      <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
 713                 };
 714
 715                 msi3: msi-controller@15a0000 {
 716                         compatible = "fsl,ls1046a-msi";
 717                         msi-controller;
 718                         reg = <0x0 0x15a0000 0x0 0x10000>;
 719                         interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
 720                                      <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
 721                                      <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>,
 722                                      <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
 723                 };
 724
 725                 pcie1: pcie@3400000 {
 726                         compatible = "fsl,ls1046a-pcie";
 727                         reg = <0x00 0x03400000 0x0 0x00100000   /* controller registers */
 728                                0x40 0x00000000 0x0 0x00002000>; /* configuration space */
 729                         reg-names = "regs", "config";
 730                         interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
 731                                      <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; /* PME interrupt */
 732                         interrupt-names = "aer", "pme";
 733                         #address-cells = <3>;
 734                         #size-cells = <2>;
 735                         device_type = "pci";
 736                         dma-coherent;
 737                         num-viewport = <8>;
 738                         bus-range = <0x0 0xff>;
 739                         ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000   /* downstream I/O */
 740                                   0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
 741                         msi-parent = <&msi1>, <&msi2>, <&msi3>;
 742                         #interrupt-cells = <1>;
 743                         interrupt-map-mask = <0 0 0 7>;
 744                         interrupt-map = <0000 0 0 1 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
 745                                         <0000 0 0 2 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
 746                                         <0000 0 0 3 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
 747                                         <0000 0 0 4 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
 748                         status = "disabled";
 749                 };
 750
 751                 pcie_ep1: pcie_ep@3400000 {
 752                         compatible = "fsl,ls1046a-pcie-ep","fsl,ls-pcie-ep";
 753                         reg = <0x00 0x03400000 0x0 0x00100000
 754                                 0x40 0x00000000 0x8 0x00000000>;
 755                         reg-names = "regs", "addr_space";
 756                         num-ib-windows = <6>;
 757                         num-ob-windows = <8>;
 758                         status = "disabled";
 759                 };
 760
 761                 pcie2: pcie@3500000 {
 762                         compatible = "fsl,ls1046a-pcie";
 763                         reg = <0x00 0x03500000 0x0 0x00100000   /* controller registers */
 764                                0x48 0x00000000 0x0 0x00002000>; /* configuration space */
 765                         reg-names = "regs", "config";
 766                         interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
 767                                      <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; /* PME interrupt */
 768                         interrupt-names = "aer", "pme";
 769                         #address-cells = <3>;
 770                         #size-cells = <2>;
 771                         device_type = "pci";
 772                         dma-coherent;
 773                         num-viewport = <8>;
 774                         bus-range = <0x0 0xff>;
 775                         ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000   /* downstream I/O */
 776                                   0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
 777                         msi-parent = <&msi2>, <&msi3>, <&msi1>;
 778                         #interrupt-cells = <1>;
 779                         interrupt-map-mask = <0 0 0 7>;
 780                         interrupt-map = <0000 0 0 1 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
 781                                         <0000 0 0 2 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
 782                                         <0000 0 0 3 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
 783                                         <0000 0 0 4 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
 784                         status = "disabled";
 785                 };
 786
 787                 pcie_ep2: pcie_ep@3500000 {
 788                         compatible = "fsl,ls1046a-pcie-ep","fsl,ls-pcie-ep";
 789                         reg = <0x00 0x03500000 0x0 0x00100000
 790                                 0x48 0x00000000 0x8 0x00000000>;
 791                         reg-names = "regs", "addr_space";
 792                         num-ib-windows = <6>;
 793                         num-ob-windows = <8>;
 794                         status = "disabled";
 795                 };
 796
 797                 pcie3: pcie@3600000 {
 798                         compatible = "fsl,ls1046a-pcie";
 799                         reg = <0x00 0x03600000 0x0 0x00100000   /* controller registers */
 800                                0x50 0x00000000 0x0 0x00002000>; /* configuration space */
 801                         reg-names = "regs", "config";
 802                         interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
 803                                      <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; /* PME interrupt */
 804                         interrupt-names = "aer", "pme";
 805                         #address-cells = <3>;
 806                         #size-cells = <2>;
 807                         device_type = "pci";
 808                         dma-coherent;
 809                         num-viewport = <8>;
 810                         bus-range = <0x0 0xff>;
 811                         ranges = <0x81000000 0x0 0x00000000 0x50 0x00010000 0x0 0x00010000   /* downstream I/O */
 812                                   0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
 813                         msi-parent = <&msi3>, <&msi1>, <&msi2>;
 814                         #interrupt-cells = <1>;
 815                         interrupt-map-mask = <0 0 0 7>;
 816                         interrupt-map = <0000 0 0 1 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
 817                                         <0000 0 0 2 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
 818                                         <0000 0 0 3 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
 819                                         <0000 0 0 4 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
 820                         status = "disabled";
 821                 };
 822
 823                 pcie_ep3: pcie_ep@3600000 {
 824                         compatible = "fsl,ls1046a-pcie-ep", "fsl,ls-pcie-ep";
 825                         reg = <0x00 0x03600000 0x0 0x00100000
 826                                 0x50 0x00000000 0x8 0x00000000>;
 827                         reg-names = "regs", "addr_space";
 828                         num-ib-windows = <6>;
 829                         num-ob-windows = <8>;
 830                         status = "disabled";
 831                 };
 832
 833                 qdma: dma-controller@8380000 {
 834                         compatible = "fsl,ls1046a-qdma", "fsl,ls1021a-qdma";
 835                         reg = <0x0 0x8380000 0x0 0x1000>, /* Controller regs */
 836                               <0x0 0x8390000 0x0 0x10000>, /* Status regs */
 837                               <0x0 0x83a0000 0x0 0x40000>; /* Block regs */
 838                         interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
 839                                      <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
 840                                      <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
 841                                      <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
 842                                      <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
 843                         interrupt-names = "qdma-error", "qdma-queue0",
 844                                 "qdma-queue1", "qdma-queue2", "qdma-queue3";
 845                         dma-channels = <8>;
 846                         block-number = <1>;
 847                         block-offset = <0x10000>;
 848                         fsl,dma-queues = <2>;
 849                         status-sizes = <64>;
 850                         queue-sizes = <64 64>;
 851                         big-endian;
 852                 };
 853
 854                 rcpm: power-controller@1ee2140 {
 855                         compatible = "fsl,ls1046a-rcpm", "fsl,qoriq-rcpm-2.1+";
 856                         reg = <0x0 0x1ee2140 0x0 0x4>;
 857                         #fsl,rcpm-wakeup-cells = <1>;
 858                 };
 859
 860                 ftm_alarm0: timer@29d0000 {
 861                         compatible = "fsl,ls1046a-ftm-alarm";
 862                         reg = <0x0 0x29d0000 0x0 0x10000>;
 863                         fsl,rcpm-wakeup = <&rcpm 0x20000>;
 864                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 865                         big-endian;
 866                 };
 867         };
 868
 869         reserved-memory {
 870                 #address-cells = <2>;
 871                 #size-cells = <2>;
 872                 ranges;
 873
 874                 bman_fbpr: bman-fbpr {
 875                         compatible = "shared-dma-pool";
 876                         size = <0 0x1000000>;
 877                         alignment = <0 0x1000000>;
 878                         no-map;
 879                 };
 880
 881                 qman_fqd: qman-fqd {
 882                         compatible = "shared-dma-pool";
 883                         size = <0 0x800000>;
 884                         alignment = <0 0x800000>;
 885                         no-map;
 886                 };
 887
 888                 qman_pfdr: qman-pfdr {
 889                         compatible = "shared-dma-pool";
 890                         size = <0 0x2000000>;
 891                         alignment = <0 0x2000000>;
 892                         no-map;
 893                 };
 894         };
 895
 896         firmware {
 897                 optee {
 898                         compatible = "linaro,optee-tz";
 899                         method = "smc";
 900                 };
 901         };
 902 };
 903
 904 #include "qoriq-qman-portals.dtsi"
 905 #include "qoriq-bman-portals.dtsi"