arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Device Tree Include file for Freescale Layerscape-1046A family SoC.
   4  *
   5  * Copyright 2016 Freescale Semiconductor, Inc.
   6  * Copyright 2019-2020 NXP
   7  *
   8  * Mingkai Hu <mingkai.hu@nxp.com>
   9  */
  10
  11 /dts-v1/;
  12
  13 #include "fsl-ls1046a.dtsi"
  14
  15 / {
  16         model = "LS1046A RDB Board";
  17         compatible = "fsl,ls1046a-rdb", "fsl,ls1046a";
  18
  19         aliases {
  20                 serial0 = &duart0;
  21                 serial1 = &duart1;
  22                 serial2 = &duart2;
  23                 serial3 = &duart3;
  24         };
  25
  26         chosen {
  27                 stdout-path = "serial0:115200n8";
  28         };
  29 };
  30
  31 &duart0 {
  32         status = "okay";
  33 };
  34
  35 &duart1 {
  36         status = "okay";
  37 };
  38
  39 &esdhc {
  40         mmc-hs200-1_8v;
  41         sd-uhs-sdr104;
  42         sd-uhs-sdr50;
  43         sd-uhs-sdr25;
  44         sd-uhs-sdr12;
  45 };
  46
  47 &i2c0 {
  48         status = "okay";
  49
  50         ina220@40 {
  51                 compatible = "ti,ina220";
  52                 reg = <0x40>;
  53                 shunt-resistor = <1000>;
  54         };
  55
  56         temp-sensor@4c {
  57                 compatible = "adi,adt7461";
  58                 reg = <0x4c>;
  59         };
  60
  61         eeprom@52 {
  62                 compatible = "atmel,24c512";
  63                 reg = <0x52>;
  64         };
  65
  66         eeprom@53 {
  67                 compatible = "atmel,24c512";
  68                 reg = <0x53>;
  69         };
  70 };
  71
  72 &i2c3 {
  73         status = "okay";
  74
  75         rtc@51 {
  76                 compatible = "nxp,pcf2129";
  77                 reg = <0x51>;
  78                 /* IRQ_RTC_B -> IRQ05, active low */
  79                 interrupts-extended = <&extirq 5 IRQ_TYPE_LEVEL_LOW>;
  80         };
  81 };
  82
  83 &ifc {
  84         #address-cells = <2>;
  85         #size-cells = <1>;
  86         /* NAND Flashe and CPLD on board */
  87         ranges = <0x0 0x0 0x0 0x7e800000 0x00010000
  88                   0x2 0x0 0x0 0x7fb00000 0x00000100>;
  89         status = "okay";
  90
  91         nand@0,0 {
  92                 compatible = "fsl,ifc-nand";
  93                 #address-cells = <1>;
  94                 #size-cells = <1>;
  95                 reg = <0x0 0x0 0x10000>;
  96         };
  97
  98         cpld: board-control@2,0 {
  99                 compatible = "fsl,ls1046ardb-cpld";
 100                 reg = <0x2 0x0 0x0000100>;
 101         };
 102 };
 103
 104 &qspi {
 105         status = "okay";
 106
 107         s25fs512s0: flash@0 {
 108                 compatible = "jedec,spi-nor";
 109                 #address-cells = <1>;
 110                 #size-cells = <1>;
 111                 spi-max-frequency = <50000000>;
 112                 spi-rx-bus-width = <4>;
 113                 spi-tx-bus-width = <1>;
 114                 reg = <0>;
 115         };
 116
 117         s25fs512s1: flash@1 {
 118                 compatible = "jedec,spi-nor";
 119                 #address-cells = <1>;
 120                 #size-cells = <1>;
 121                 spi-max-frequency = <50000000>;
 122                 spi-rx-bus-width = <4>;
 123                 spi-tx-bus-width = <1>;
 124                 reg = <1>;
 125         };
 126 };
 127
 128 &usb1 {
 129         dr_mode = "otg";
 130 };
 131
 132 #include "fsl-ls1046-post.dtsi"
 133
 134 &fman0 {
 135         ethernet@e4000 {
 136                 phy-handle = <&rgmii_phy1>;
 137                 phy-connection-type = "rgmii-id";
 138         };
 139
 140         ethernet@e6000 {
 141                 phy-handle = <&rgmii_phy2>;
 142                 phy-connection-type = "rgmii-id";
 143         };
 144
 145         ethernet@e8000 {
 146                 phy-handle = <&sgmii_phy1>;
 147                 phy-connection-type = "sgmii";
 148         };
 149
 150         ethernet@ea000 {
 151                 phy-handle = <&sgmii_phy2>;
 152                 phy-connection-type = "sgmii";
 153         };
 154
 155         ethernet@f0000 { /* 10GEC1 */
 156                 phy-handle = <&aqr106_phy>;
 157                 phy-connection-type = "xgmii";
 158         };
 159
 160         ethernet@f2000 { /* 10GEC2 */
 161                 fixed-link = <0 1 1000 0 0>;
 162                 phy-connection-type = "xgmii";
 163         };
 164
 165         mdio@fc000 {
 166                 rgmii_phy1: ethernet-phy@1 {
 167                         reg = <0x1>;
 168                 };
 169
 170                 rgmii_phy2: ethernet-phy@2 {
 171                         reg = <0x2>;
 172                 };
 173
 174                 sgmii_phy1: ethernet-phy@3 {
 175                         reg = <0x3>;
 176                 };
 177
 178                 sgmii_phy2: ethernet-phy@4 {
 179                         reg = <0x4>;
 180                 };
 181         };
 182
 183         mdio@fd000 {
 184                 aqr106_phy: ethernet-phy@0 {
 185                         compatible = "ethernet-phy-ieee802.3-c45";
 186                         interrupts = <0 131 4>;
 187                         reg = <0x0>;
 188                 };
 189         };
 190 };