arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Device Tree file for NXP LS1028A QDS Board.
   4  *
   5  * Copyright 2018 NXP
   6  *
   7  * Harninder Rai <harninder.rai@nxp.com>
   8  *
   9  */
  10
  11 /dts-v1/;
  12
  13 #include "fsl-ls1028a.dtsi"
  14
  15 / {
  16         model = "LS1028A QDS Board";
  17         compatible = "fsl,ls1028a-qds", "fsl,ls1028a";
  18
  19         aliases {
  20                 crypto = &crypto;
  21                 gpio0 = &gpio1;
  22                 gpio1 = &gpio2;
  23                 gpio2 = &gpio3;
  24                 serial0 = &duart0;
  25                 serial1 = &duart1;
  26         };
  27
  28         chosen {
  29                 stdout-path = "serial0:115200n8";
  30         };
  31
  32         memory@80000000 {
  33                 device_type = "memory";
  34                 reg = <0x0 0x80000000 0x1 0x00000000>;
  35         };
  36
  37         sys_mclk: clock-mclk {
  38                 compatible = "fixed-clock";
  39                 #clock-cells = <0>;
  40                 clock-frequency = <25000000>;
  41         };
  42
  43         reg_1p8v: regulator-1p8v {
  44                 compatible = "regulator-fixed";
  45                 regulator-name = "1P8V";
  46                 regulator-min-microvolt = <1800000>;
  47                 regulator-max-microvolt = <1800000>;
  48                 regulator-always-on;
  49         };
  50
  51         sb_3v3: regulator-sb3v3 {
  52                 compatible = "regulator-fixed";
  53                 regulator-name = "3v3_vbus";
  54                 regulator-min-microvolt = <3300000>;
  55                 regulator-max-microvolt = <3300000>;
  56                 regulator-boot-on;
  57                 regulator-always-on;
  58         };
  59
  60         sound {
  61                 compatible = "simple-audio-card";
  62                 simple-audio-card,format = "i2s";
  63                 simple-audio-card,widgets =
  64                         "Microphone", "Microphone Jack",
  65                         "Headphone", "Headphone Jack",
  66                         "Speaker", "Speaker Ext",
  67                         "Line", "Line In Jack";
  68                 simple-audio-card,routing =
  69                         "MIC_IN", "Microphone Jack",
  70                         "Microphone Jack", "Mic Bias",
  71                         "LINE_IN", "Line In Jack",
  72                         "Headphone Jack", "HP_OUT",
  73                         "Speaker Ext", "LINE_OUT";
  74
  75                 simple-audio-card,cpu {
  76                         sound-dai = <&sai1>;
  77                         frame-master;
  78                         bitclock-master;
  79                 };
  80
  81                 simple-audio-card,codec {
  82                         sound-dai = <&sgtl5000>;
  83                         frame-master;
  84                         bitclock-master;
  85                         system-clock-frequency = <25000000>;
  86                 };
  87         };
  88
  89         mdio-mux {
  90                 compatible = "mdio-mux-multiplexer";
  91                 mux-controls = <&mux 0>;
  92                 mdio-parent-bus = <&enetc_mdio_pf3>;
  93                 #address-cells=<1>;
  94                 #size-cells = <0>;
  95
  96                 /* on-board RGMII PHY */
  97                 mdio@0 {
  98                         #address-cells = <1>;
  99                         #size-cells = <0>;
 100                         reg = <0>;
 101
 102                         qds_phy1: ethernet-phy@5 {
 103                                 /* Atheros 8035 */
 104                                 reg = <5>;
 105                         };
 106                 };
 107         };
 108 };
 109
 110 &dspi0 {
 111         bus-num = <0>;
 112         status = "okay";
 113
 114         flash@0 {
 115                 #address-cells = <1>;
 116                 #size-cells = <1>;
 117                 compatible = "jedec,spi-nor";
 118                 spi-cpol;
 119                 spi-cpha;
 120                 reg = <0>;
 121                 spi-max-frequency = <10000000>;
 122         };
 123
 124         flash@1 {
 125                 #address-cells = <1>;
 126                 #size-cells = <1>;
 127                 compatible = "jedec,spi-nor";
 128                 spi-cpol;
 129                 spi-cpha;
 130                 reg = <1>;
 131                 spi-max-frequency = <10000000>;
 132         };
 133
 134         flash@2 {
 135                 #address-cells = <1>;
 136                 #size-cells = <1>;
 137                 compatible = "jedec,spi-nor";
 138                 spi-cpol;
 139                 spi-cpha;
 140                 reg = <2>;
 141                 spi-max-frequency = <10000000>;
 142         };
 143 };
 144
 145 &dspi1 {
 146         bus-num = <1>;
 147         status = "okay";
 148
 149         flash@0 {
 150                 #address-cells = <1>;
 151                 #size-cells = <1>;
 152                 compatible = "jedec,spi-nor";
 153                 spi-cpol;
 154                 spi-cpha;
 155                 reg = <0>;
 156                 spi-max-frequency = <10000000>;
 157         };
 158
 159         flash@1 {
 160                 #address-cells = <1>;
 161                 #size-cells = <1>;
 162                 compatible = "jedec,spi-nor";
 163                 spi-cpol;
 164                 spi-cpha;
 165                 reg = <1>;
 166                 spi-max-frequency = <10000000>;
 167         };
 168
 169         flash@2 {
 170                 #address-cells = <1>;
 171                 #size-cells = <1>;
 172                 compatible = "jedec,spi-nor";
 173                 spi-cpol;
 174                 spi-cpha;
 175                 reg = <2>;
 176                 spi-max-frequency = <10000000>;
 177         };
 178 };
 179
 180 &dspi2 {
 181         bus-num = <2>;
 182         status = "okay";
 183
 184         flash@0 {
 185                 #address-cells = <1>;
 186                 #size-cells = <1>;
 187                 compatible = "jedec,spi-nor";
 188                 spi-cpol;
 189                 spi-cpha;
 190                 reg = <0>;
 191                 spi-max-frequency = <10000000>;
 192         };
 193 };
 194
 195 &duart0 {
 196         status = "okay";
 197 };
 198
 199 &duart1 {
 200         status = "okay";
 201 };
 202
 203 &esdhc {
 204         status = "okay";
 205 };
 206
 207 &esdhc1 {
 208         status = "okay";
 209 };
 210
 211 &fspi {
 212         status = "okay";
 213
 214         mt35xu02g0: flash@0 {
 215                 compatible = "jedec,spi-nor";
 216                 #address-cells = <1>;
 217                 #size-cells = <1>;
 218                 spi-max-frequency = <50000000>;
 219                 /* The following setting enables 1-1-8 (CMD-ADDR-DATA) mode */
 220                 spi-rx-bus-width = <8>; /* 8 SPI Rx lines */
 221                 spi-tx-bus-width = <1>; /* 1 SPI Tx line */
 222                 reg = <0>;
 223         };
 224 };
 225
 226 &i2c0 {
 227         status = "okay";
 228
 229         i2c-mux@77 {
 230                 compatible = "nxp,pca9547";
 231                 reg = <0x77>;
 232                 #address-cells = <1>;
 233                 #size-cells = <0>;
 234
 235                 i2c@2 {
 236                         #address-cells = <1>;
 237                         #size-cells = <0>;
 238                         reg = <0x2>;
 239
 240                         current-monitor@40 {
 241                                 compatible = "ti,ina220";
 242                                 reg = <0x40>;
 243                                 shunt-resistor = <1000>;
 244                         };
 245
 246                         current-monitor@41 {
 247                                 compatible = "ti,ina220";
 248                                 reg = <0x41>;
 249                                 shunt-resistor = <1000>;
 250                         };
 251                 };
 252
 253                 i2c@3 {
 254                         #address-cells = <1>;
 255                         #size-cells = <0>;
 256                         reg = <0x3>;
 257
 258                         temperature-sensor@4c {
 259                                 compatible = "nxp,sa56004";
 260                                 reg = <0x4c>;
 261                                 vcc-supply = <&sb_3v3>;
 262                         };
 263
 264                         rtc@51 {
 265                                 compatible = "nxp,pcf2129";
 266                                 reg = <0x51>;
 267                         };
 268
 269                         eeprom@56 {
 270                                 compatible = "atmel,24c512";
 271                                 reg = <0x56>;
 272                         };
 273
 274                         eeprom@57 {
 275                                 compatible = "atmel,24c512";
 276                                 reg = <0x57>;
 277                         };
 278                 };
 279
 280                 i2c@5 {
 281                         #address-cells = <1>;
 282                         #size-cells = <0>;
 283                         reg = <0x5>;
 284
 285                         sgtl5000: audio-codec@a {
 286                                 #sound-dai-cells = <0>;
 287                                 compatible = "fsl,sgtl5000";
 288                                 reg = <0xa>;
 289                                 VDDA-supply = <&reg_1p8v>;
 290                                 VDDIO-supply = <&reg_1p8v>;
 291                                 clocks = <&sys_mclk>;
 292                         };
 293                 };
 294         };
 295
 296         fpga@66 {
 297                 compatible = "fsl,ls1028aqds-fpga", "fsl,fpga-qixis-i2c",
 298                              "simple-mfd";
 299                 reg = <0x66>;
 300
 301                 mux: mux-controller {
 302                         compatible = "reg-mux";
 303                         #mux-control-cells = <1>;
 304                         mux-reg-masks = <0x54 0xf0>; /* 0: reg 0x54, bits 7:4 */
 305                 };
 306         };
 307
 308 };
 309
 310 &enetc_port1 {
 311         phy-handle = <&qds_phy1>;
 312         phy-connection-type = "rgmii-id";
 313         status = "okay";
 314 };
 315
 316 &lpuart0 {
 317         status = "okay";
 318 };
 319
 320 &sai1 {
 321         status = "okay";
 322 };
 323
 324 &sata {
 325         status = "okay";
 326 };