arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 // Copyright (C) 2016 ARM Ltd.
   3 // based on the Allwinner H3 dtsi:
   4 //    Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com>
   5
   6 #include <dt-bindings/clock/sun50i-a64-ccu.h>
   7 #include <dt-bindings/clock/sun8i-de2.h>
   8 #include <dt-bindings/clock/sun8i-r-ccu.h>
   9 #include <dt-bindings/interrupt-controller/arm-gic.h>
  10 #include <dt-bindings/reset/sun50i-a64-ccu.h>
  11 #include <dt-bindings/reset/sun8i-de2.h>
  12 #include <dt-bindings/reset/sun8i-r-ccu.h>
  13 #include <dt-bindings/thermal/thermal.h>
  14
  15 / {
  16         interrupt-parent = <&gic>;
  17         #address-cells = <1>;
  18         #size-cells = <1>;
  19
  20         chosen {
  21                 #address-cells = <1>;
  22                 #size-cells = <1>;
  23                 ranges;
  24
  25                 simplefb_lcd: framebuffer-lcd {
  26                         compatible = "allwinner,simple-framebuffer",
  27                                      "simple-framebuffer";
  28                         allwinner,pipeline = "mixer0-lcd0";
  29                         clocks = <&ccu CLK_TCON0>,
  30                                  <&display_clocks CLK_MIXER0>;
  31                         status = "disabled";
  32                 };
  33
  34                 simplefb_hdmi: framebuffer-hdmi {
  35                         compatible = "allwinner,simple-framebuffer",
  36                                      "simple-framebuffer";
  37                         allwinner,pipeline = "mixer1-lcd1-hdmi";
  38                         clocks = <&display_clocks CLK_MIXER1>,
  39                                  <&ccu CLK_TCON1>, <&ccu CLK_HDMI>;
  40                         status = "disabled";
  41                 };
  42         };
  43
  44         cpus {
  45                 #address-cells = <1>;
  46                 #size-cells = <0>;
  47
  48                 cpu0: cpu@0 {
  49                         compatible = "arm,cortex-a53";
  50                         device_type = "cpu";
  51                         reg = <0>;
  52                         enable-method = "psci";
  53                         next-level-cache = <&L2>;
  54                         clocks = <&ccu CLK_CPUX>;
  55                         clock-names = "cpu";
  56                         #cooling-cells = <2>;
  57                 };
  58
  59                 cpu1: cpu@1 {
  60                         compatible = "arm,cortex-a53";
  61                         device_type = "cpu";
  62                         reg = <1>;
  63                         enable-method = "psci";
  64                         next-level-cache = <&L2>;
  65                         clocks = <&ccu CLK_CPUX>;
  66                         clock-names = "cpu";
  67                         #cooling-cells = <2>;
  68                 };
  69
  70                 cpu2: cpu@2 {
  71                         compatible = "arm,cortex-a53";
  72                         device_type = "cpu";
  73                         reg = <2>;
  74                         enable-method = "psci";
  75                         next-level-cache = <&L2>;
  76                         clocks = <&ccu CLK_CPUX>;
  77                         clock-names = "cpu";
  78                         #cooling-cells = <2>;
  79                 };
  80
  81                 cpu3: cpu@3 {
  82                         compatible = "arm,cortex-a53";
  83                         device_type = "cpu";
  84                         reg = <3>;
  85                         enable-method = "psci";
  86                         next-level-cache = <&L2>;
  87                         clocks = <&ccu CLK_CPUX>;
  88                         clock-names = "cpu";
  89                         #cooling-cells = <2>;
  90                 };
  91
  92                 L2: l2-cache {
  93                         compatible = "cache";
  94                         cache-level = <2>;
  95                 };
  96         };
  97
  98         de: display-engine {
  99                 compatible = "allwinner,sun50i-a64-display-engine";
 100                 allwinner,pipelines = <&mixer0>,
 101                                       <&mixer1>;
 102                 status = "disabled";
 103         };
 104
 105         osc24M: osc24M_clk {
 106                 #clock-cells = <0>;
 107                 compatible = "fixed-clock";
 108                 clock-frequency = <24000000>;
 109                 clock-output-names = "osc24M";
 110         };
 111
 112         osc32k: osc32k_clk {
 113                 #clock-cells = <0>;
 114                 compatible = "fixed-clock";
 115                 clock-frequency = <32768>;
 116                 clock-output-names = "ext-osc32k";
 117         };
 118
 119         pmu {
 120                 compatible = "arm,cortex-a53-pmu";
 121                 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
 122                              <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
 123                              <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
 124                              <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
 125                 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
 126         };
 127
 128         psci {
 129                 compatible = "arm,psci-0.2";
 130                 method = "smc";
 131         };
 132
 133         sound: sound {
 134                 #address-cells = <1>;
 135                 #size-cells = <0>;
 136                 compatible = "simple-audio-card";
 137                 simple-audio-card,name = "sun50i-a64-audio";
 138                 simple-audio-card,aux-devs = <&codec_analog>;
 139                 simple-audio-card,routing =
 140                                 "Left DAC", "DACL",
 141                                 "Right DAC", "DACR",
 142                                 "ADCL", "Left ADC",
 143                                 "ADCR", "Right ADC";
 144                 status = "disabled";
 145
 146                 simple-audio-card,dai-link@0 {
 147                         format = "i2s";
 148                         frame-master = <&link0_cpu>;
 149                         bitclock-master = <&link0_cpu>;
 150                         mclk-fs = <128>;
 151
 152                         link0_cpu: cpu {
 153                                 sound-dai = <&dai>;
 154                         };
 155
 156                         link0_codec: codec {
 157                                 sound-dai = <&codec 0>;
 158                         };
 159                 };
 160         };
 161
 162         timer {
 163                 compatible = "arm,armv8-timer";
 164                 allwinner,erratum-unknown1;
 165                 arm,no-tick-in-suspend;
 166                 interrupts = <GIC_PPI 13
 167                         (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 168                              <GIC_PPI 14
 169                         (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 170                              <GIC_PPI 11
 171                         (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 172                              <GIC_PPI 10
 173                         (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 174         };
 175
 176         thermal-zones {
 177                 cpu_thermal: cpu0-thermal {
 178                         /* milliseconds */
 179                         polling-delay-passive = <0>;
 180                         polling-delay = <0>;
 181                         thermal-sensors = <&ths 0>;
 182
 183                         cooling-maps {
 184                                 map0 {
 185                                         trip = <&cpu_alert0>;
 186                                         cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 187                                                          <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 188                                                          <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 189                                                          <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 190                                 };
 191                                 map1 {
 192                                         trip = <&cpu_alert1>;
 193                                         cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 194                                                          <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 195                                                          <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 196                                                          <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 197                                 };
 198                         };
 199
 200                         trips {
 201                                 cpu_alert0: cpu_alert0 {
 202                                         /* milliCelsius */
 203                                         temperature = <75000>;
 204                                         hysteresis = <2000>;
 205                                         type = "passive";
 206                                 };
 207
 208                                 cpu_alert1: cpu_alert1 {
 209                                         /* milliCelsius */
 210                                         temperature = <90000>;
 211                                         hysteresis = <2000>;
 212                                         type = "hot";
 213                                 };
 214
 215                                 cpu_crit: cpu_crit {
 216                                         /* milliCelsius */
 217                                         temperature = <110000>;
 218                                         hysteresis = <2000>;
 219                                         type = "critical";
 220                                 };
 221                         };
 222                 };
 223
 224                 gpu0_thermal: gpu0-thermal {
 225                         /* milliseconds */
 226                         polling-delay-passive = <0>;
 227                         polling-delay = <0>;
 228                         thermal-sensors = <&ths 1>;
 229                 };
 230
 231                 gpu1_thermal: gpu1-thermal {
 232                         /* milliseconds */
 233                         polling-delay-passive = <0>;
 234                         polling-delay = <0>;
 235                         thermal-sensors = <&ths 2>;
 236                 };
 237         };
 238
 239         soc {
 240                 compatible = "simple-bus";
 241                 #address-cells = <1>;
 242                 #size-cells = <1>;
 243                 ranges;
 244
 245                 bus@1000000 {
 246                         compatible = "allwinner,sun50i-a64-de2";
 247                         reg = <0x1000000 0x400000>;
 248                         allwinner,sram = <&de2_sram 1>;
 249                         #address-cells = <1>;
 250                         #size-cells = <1>;
 251                         ranges = <0 0x1000000 0x400000>;
 252
 253                         display_clocks: clock@0 {
 254                                 compatible = "allwinner,sun50i-a64-de2-clk";
 255                                 reg = <0x0 0x10000>;
 256                                 clocks = <&ccu CLK_BUS_DE>,
 257                                          <&ccu CLK_DE>;
 258                                 clock-names = "bus",
 259                                               "mod";
 260                                 resets = <&ccu RST_BUS_DE>;
 261                                 #clock-cells = <1>;
 262                                 #reset-cells = <1>;
 263                         };
 264
 265                         rotate: rotate@20000 {
 266                                 compatible = "allwinner,sun50i-a64-de2-rotate",
 267                                              "allwinner,sun8i-a83t-de2-rotate";
 268                                 reg = <0x20000 0x10000>;
 269                                 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 270                                 clocks = <&display_clocks CLK_BUS_ROT>,
 271                                          <&display_clocks CLK_ROT>;
 272                                 clock-names = "bus",
 273                                               "mod";
 274                                 resets = <&display_clocks RST_ROT>;
 275                         };
 276
 277                         mixer0: mixer@100000 {
 278                                 compatible = "allwinner,sun50i-a64-de2-mixer-0";
 279                                 reg = <0x100000 0x100000>;
 280                                 clocks = <&display_clocks CLK_BUS_MIXER0>,
 281                                          <&display_clocks CLK_MIXER0>;
 282                                 clock-names = "bus",
 283                                               "mod";
 284                                 resets = <&display_clocks RST_MIXER0>;
 285
 286                                 ports {
 287                                         #address-cells = <1>;
 288                                         #size-cells = <0>;
 289
 290                                         mixer0_out: port@1 {
 291                                                 #address-cells = <1>;
 292                                                 #size-cells = <0>;
 293                                                 reg = <1>;
 294
 295                                                 mixer0_out_tcon0: endpoint@0 {
 296                                                         reg = <0>;
 297                                                         remote-endpoint = <&tcon0_in_mixer0>;
 298                                                 };
 299
 300                                                 mixer0_out_tcon1: endpoint@1 {
 301                                                         reg = <1>;
 302                                                         remote-endpoint = <&tcon1_in_mixer0>;
 303                                                 };
 304                                         };
 305                                 };
 306                         };
 307
 308                         mixer1: mixer@200000 {
 309                                 compatible = "allwinner,sun50i-a64-de2-mixer-1";
 310                                 reg = <0x200000 0x100000>;
 311                                 clocks = <&display_clocks CLK_BUS_MIXER1>,
 312                                          <&display_clocks CLK_MIXER1>;
 313                                 clock-names = "bus",
 314                                               "mod";
 315                                 resets = <&display_clocks RST_MIXER1>;
 316
 317                                 ports {
 318                                         #address-cells = <1>;
 319                                         #size-cells = <0>;
 320
 321                                         mixer1_out: port@1 {
 322                                                 #address-cells = <1>;
 323                                                 #size-cells = <0>;
 324                                                 reg = <1>;
 325
 326                                                 mixer1_out_tcon0: endpoint@0 {
 327                                                         reg = <0>;
 328                                                         remote-endpoint = <&tcon0_in_mixer1>;
 329                                                 };
 330
 331                                                 mixer1_out_tcon1: endpoint@1 {
 332                                                         reg = <1>;
 333                                                         remote-endpoint = <&tcon1_in_mixer1>;
 334                                                 };
 335                                         };
 336                                 };
 337                         };
 338                 };
 339
 340                 syscon: syscon@1c00000 {
 341                         compatible = "allwinner,sun50i-a64-system-control";
 342                         reg = <0x01c00000 0x1000>;
 343                         #address-cells = <1>;
 344                         #size-cells = <1>;
 345                         ranges;
 346
 347                         sram_c: sram@18000 {
 348                                 compatible = "mmio-sram";
 349                                 reg = <0x00018000 0x28000>;
 350                                 #address-cells = <1>;
 351                                 #size-cells = <1>;
 352                                 ranges = <0 0x00018000 0x28000>;
 353
 354                                 de2_sram: sram-section@0 {
 355                                         compatible = "allwinner,sun50i-a64-sram-c";
 356                                         reg = <0x0000 0x28000>;
 357                                 };
 358                         };
 359
 360                         sram_c1: sram@1d00000 {
 361                                 compatible = "mmio-sram";
 362                                 reg = <0x01d00000 0x40000>;
 363                                 #address-cells = <1>;
 364                                 #size-cells = <1>;
 365                                 ranges = <0 0x01d00000 0x40000>;
 366
 367                                 ve_sram: sram-section@0 {
 368                                         compatible = "allwinner,sun50i-a64-sram-c1",
 369                                                      "allwinner,sun4i-a10-sram-c1";
 370                                         reg = <0x000000 0x40000>;
 371                                 };
 372                         };
 373                 };
 374
 375                 dma: dma-controller@1c02000 {
 376                         compatible = "allwinner,sun50i-a64-dma";
 377                         reg = <0x01c02000 0x1000>;
 378                         interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
 379                         clocks = <&ccu CLK_BUS_DMA>;
 380                         dma-channels = <8>;
 381                         dma-requests = <27>;
 382                         resets = <&ccu RST_BUS_DMA>;
 383                         #dma-cells = <1>;
 384                 };
 385
 386                 tcon0: lcd-controller@1c0c000 {
 387                         compatible = "allwinner,sun50i-a64-tcon-lcd",
 388                                      "allwinner,sun8i-a83t-tcon-lcd";
 389                         reg = <0x01c0c000 0x1000>;
 390                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 391                         clocks = <&ccu CLK_BUS_TCON0>, <&ccu CLK_TCON0>;
 392                         clock-names = "ahb", "tcon-ch0";
 393                         clock-output-names = "tcon-pixel-clock";
 394                         #clock-cells = <0>;
 395                         resets = <&ccu RST_BUS_TCON0>, <&ccu RST_BUS_LVDS>;
 396                         reset-names = "lcd", "lvds";
 397
 398                         ports {
 399                                 #address-cells = <1>;
 400                                 #size-cells = <0>;
 401
 402                                 tcon0_in: port@0 {
 403                                         #address-cells = <1>;
 404                                         #size-cells = <0>;
 405                                         reg = <0>;
 406
 407                                         tcon0_in_mixer0: endpoint@0 {
 408                                                 reg = <0>;
 409                                                 remote-endpoint = <&mixer0_out_tcon0>;
 410                                         };
 411
 412                                         tcon0_in_mixer1: endpoint@1 {
 413                                                 reg = <1>;
 414                                                 remote-endpoint = <&mixer1_out_tcon0>;
 415                                         };
 416                                 };
 417
 418                                 tcon0_out: port@1 {
 419                                         #address-cells = <1>;
 420                                         #size-cells = <0>;
 421                                         reg = <1>;
 422
 423                                         tcon0_out_dsi: endpoint@1 {
 424                                                 reg = <1>;
 425                                                 remote-endpoint = <&dsi_in_tcon0>;
 426                                                 allwinner,tcon-channel = <1>;
 427                                         };
 428                                 };
 429                         };
 430                 };
 431
 432                 tcon1: lcd-controller@1c0d000 {
 433                         compatible = "allwinner,sun50i-a64-tcon-tv",
 434                                      "allwinner,sun8i-a83t-tcon-tv";
 435                         reg = <0x01c0d000 0x1000>;
 436                         interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
 437                         clocks = <&ccu CLK_BUS_TCON1>, <&ccu CLK_TCON1>;
 438                         clock-names = "ahb", "tcon-ch1";
 439                         resets = <&ccu RST_BUS_TCON1>;
 440                         reset-names = "lcd";
 441
 442                         ports {
 443                                 #address-cells = <1>;
 444                                 #size-cells = <0>;
 445
 446                                 tcon1_in: port@0 {
 447                                         #address-cells = <1>;
 448                                         #size-cells = <0>;
 449                                         reg = <0>;
 450
 451                                         tcon1_in_mixer0: endpoint@0 {
 452                                                 reg = <0>;
 453                                                 remote-endpoint = <&mixer0_out_tcon1>;
 454                                         };
 455
 456                                         tcon1_in_mixer1: endpoint@1 {
 457                                                 reg = <1>;
 458                                                 remote-endpoint = <&mixer1_out_tcon1>;
 459                                         };
 460                                 };
 461
 462                                 tcon1_out: port@1 {
 463                                         #address-cells = <1>;
 464                                         #size-cells = <0>;
 465                                         reg = <1>;
 466
 467                                         tcon1_out_hdmi: endpoint@1 {
 468                                                 reg = <1>;
 469                                                 remote-endpoint = <&hdmi_in_tcon1>;
 470                                         };
 471                                 };
 472                         };
 473                 };
 474
 475                 video-codec@1c0e000 {
 476                         compatible = "allwinner,sun50i-a64-video-engine";
 477                         reg = <0x01c0e000 0x1000>;
 478                         clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>,
 479                                  <&ccu CLK_DRAM_VE>;
 480                         clock-names = "ahb", "mod", "ram";
 481                         resets = <&ccu RST_BUS_VE>;
 482                         interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 483                         allwinner,sram = <&ve_sram 1>;
 484                 };
 485
 486                 mmc0: mmc@1c0f000 {
 487                         compatible = "allwinner,sun50i-a64-mmc";
 488                         reg = <0x01c0f000 0x1000>;
 489                         clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
 490                         clock-names = "ahb", "mmc";
 491                         resets = <&ccu RST_BUS_MMC0>;
 492                         reset-names = "ahb";
 493                         interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 494                         max-frequency = <150000000>;
 495                         status = "disabled";
 496                         #address-cells = <1>;
 497                         #size-cells = <0>;
 498                 };
 499
 500                 mmc1: mmc@1c10000 {
 501                         compatible = "allwinner,sun50i-a64-mmc";
 502                         reg = <0x01c10000 0x1000>;
 503                         clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>;
 504                         clock-names = "ahb", "mmc";
 505                         resets = <&ccu RST_BUS_MMC1>;
 506                         reset-names = "ahb";
 507                         interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 508                         max-frequency = <150000000>;
 509                         status = "disabled";
 510                         #address-cells = <1>;
 511                         #size-cells = <0>;
 512                 };
 513
 514                 mmc2: mmc@1c11000 {
 515                         compatible = "allwinner,sun50i-a64-emmc";
 516                         reg = <0x01c11000 0x1000>;
 517                         clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>;
 518                         clock-names = "ahb", "mmc";
 519                         resets = <&ccu RST_BUS_MMC2>;
 520                         reset-names = "ahb";
 521                         interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 522                         max-frequency = <150000000>;
 523                         status = "disabled";
 524                         #address-cells = <1>;
 525                         #size-cells = <0>;
 526                 };
 527
 528                 sid: eeprom@1c14000 {
 529                         compatible = "allwinner,sun50i-a64-sid";
 530                         reg = <0x1c14000 0x400>;
 531                         #address-cells = <1>;
 532                         #size-cells = <1>;
 533
 534                         ths_calibration: thermal-sensor-calibration@34 {
 535                                 reg = <0x34 0x8>;
 536                         };
 537                 };
 538
 539                 crypto: crypto@1c15000 {
 540                         compatible = "allwinner,sun50i-a64-crypto";
 541                         reg = <0x01c15000 0x1000>;
 542                         interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
 543                         clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>;
 544                         clock-names = "bus", "mod";
 545                         resets = <&ccu RST_BUS_CE>;
 546                 };
 547
 548                 msgbox: mailbox@1c17000 {
 549                         compatible = "allwinner,sun50i-a64-msgbox",
 550                                      "allwinner,sun6i-a31-msgbox";
 551                         reg = <0x01c17000 0x1000>;
 552                         clocks = <&ccu CLK_BUS_MSGBOX>;
 553                         resets = <&ccu RST_BUS_MSGBOX>;
 554                         interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
 555                         #mbox-cells = <1>;
 556                 };
 557
 558                 usb_otg: usb@1c19000 {
 559                         compatible = "allwinner,sun8i-a33-musb";
 560                         reg = <0x01c19000 0x0400>;
 561                         clocks = <&ccu CLK_BUS_OTG>;
 562                         resets = <&ccu RST_BUS_OTG>;
 563                         interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 564                         interrupt-names = "mc";
 565                         phys = <&usbphy 0>;
 566                         phy-names = "usb";
 567                         extcon = <&usbphy 0>;
 568                         dr_mode = "otg";
 569                         status = "disabled";
 570                 };
 571
 572                 usbphy: phy@1c19400 {
 573                         compatible = "allwinner,sun50i-a64-usb-phy";
 574                         reg = <0x01c19400 0x14>,
 575                               <0x01c1a800 0x4>,
 576                               <0x01c1b800 0x4>;
 577                         reg-names = "phy_ctrl",
 578                                     "pmu0",
 579                                     "pmu1";
 580                         clocks = <&ccu CLK_USB_PHY0>,
 581                                  <&ccu CLK_USB_PHY1>;
 582                         clock-names = "usb0_phy",
 583                                       "usb1_phy";
 584                         resets = <&ccu RST_USB_PHY0>,
 585                                  <&ccu RST_USB_PHY1>;
 586                         reset-names = "usb0_reset",
 587                                       "usb1_reset";
 588                         status = "disabled";
 589                         #phy-cells = <1>;
 590                 };
 591
 592                 ehci0: usb@1c1a000 {
 593                         compatible = "allwinner,sun50i-a64-ehci", "generic-ehci";
 594                         reg = <0x01c1a000 0x100>;
 595                         interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 596                         clocks = <&ccu CLK_BUS_OHCI0>,
 597                                  <&ccu CLK_BUS_EHCI0>,
 598                                  <&ccu CLK_USB_OHCI0>;
 599                         resets = <&ccu RST_BUS_OHCI0>,
 600                                  <&ccu RST_BUS_EHCI0>;
 601                         phys = <&usbphy 0>;
 602                         phy-names = "usb";
 603                         status = "disabled";
 604                 };
 605
 606                 ohci0: usb@1c1a400 {
 607                         compatible = "allwinner,sun50i-a64-ohci", "generic-ohci";
 608                         reg = <0x01c1a400 0x100>;
 609                         interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 610                         clocks = <&ccu CLK_BUS_OHCI0>,
 611                                  <&ccu CLK_USB_OHCI0>;
 612                         resets = <&ccu RST_BUS_OHCI0>;
 613                         phys = <&usbphy 0>;
 614                         phy-names = "usb";
 615                         status = "disabled";
 616                 };
 617
 618                 ehci1: usb@1c1b000 {
 619                         compatible = "allwinner,sun50i-a64-ehci", "generic-ehci";
 620                         reg = <0x01c1b000 0x100>;
 621                         interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 622                         clocks = <&ccu CLK_BUS_OHCI1>,
 623                                  <&ccu CLK_BUS_EHCI1>,
 624                                  <&ccu CLK_USB_OHCI1>;
 625                         resets = <&ccu RST_BUS_OHCI1>,
 626                                  <&ccu RST_BUS_EHCI1>;
 627                         phys = <&usbphy 1>;
 628                         phy-names = "usb";
 629                         status = "disabled";
 630                 };
 631
 632                 ohci1: usb@1c1b400 {
 633                         compatible = "allwinner,sun50i-a64-ohci", "generic-ohci";
 634                         reg = <0x01c1b400 0x100>;
 635                         interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 636                         clocks = <&ccu CLK_BUS_OHCI1>,
 637                                  <&ccu CLK_USB_OHCI1>;
 638                         resets = <&ccu RST_BUS_OHCI1>;
 639                         phys = <&usbphy 1>;
 640                         phy-names = "usb";
 641                         status = "disabled";
 642                 };
 643
 644                 ccu: clock@1c20000 {
 645                         compatible = "allwinner,sun50i-a64-ccu";
 646                         reg = <0x01c20000 0x400>;
 647                         clocks = <&osc24M>, <&rtc 0>;
 648                         clock-names = "hosc", "losc";
 649                         #clock-cells = <1>;
 650                         #reset-cells = <1>;
 651                 };
 652
 653                 pio: pinctrl@1c20800 {
 654                         compatible = "allwinner,sun50i-a64-pinctrl";
 655                         reg = <0x01c20800 0x400>;
 656                         interrupt-parent = <&r_intc>;
 657                         interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
 658                                      <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
 659                                      <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
 660                         clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&rtc 0>;
 661                         clock-names = "apb", "hosc", "losc";
 662                         gpio-controller;
 663                         #gpio-cells = <3>;
 664                         interrupt-controller;
 665                         #interrupt-cells = <3>;
 666
 667                         /omit-if-no-ref/
 668                         aif2_pins: aif2-pins {
 669                                 pins = "PB4", "PB5", "PB6", "PB7";
 670                                 function = "aif2";
 671                         };
 672
 673                         /omit-if-no-ref/
 674                         aif3_pins: aif3-pins {
 675                                 pins = "PG10", "PG11", "PG12", "PG13";
 676                                 function = "aif3";
 677                         };
 678
 679                         csi_pins: csi-pins {
 680                                 pins = "PE0", "PE2", "PE3", "PE4", "PE5", "PE6",
 681                                        "PE7", "PE8", "PE9", "PE10", "PE11";
 682                                 function = "csi";
 683                         };
 684
 685                         /omit-if-no-ref/
 686                         csi_mclk_pin: csi-mclk-pin {
 687                                 pins = "PE1";
 688                                 function = "csi";
 689                         };
 690
 691                         i2c0_pins: i2c0-pins {
 692                                 pins = "PH0", "PH1";
 693                                 function = "i2c0";
 694                         };
 695
 696                         i2c1_pins: i2c1-pins {
 697                                 pins = "PH2", "PH3";
 698                                 function = "i2c1";
 699                         };
 700
 701                         i2c2_pins: i2c2-pins {
 702                                 pins = "PE14", "PE15";
 703                                 function = "i2c2";
 704                         };
 705
 706                         /omit-if-no-ref/
 707                         lcd_rgb666_pins: lcd-rgb666-pins {
 708                                 pins = "PD0", "PD1", "PD2", "PD3", "PD4",
 709                                        "PD5", "PD6", "PD7", "PD8", "PD9",
 710                                        "PD10", "PD11", "PD12", "PD13",
 711                                        "PD14", "PD15", "PD16", "PD17",
 712                                        "PD18", "PD19", "PD20", "PD21";
 713                                 function = "lcd0";
 714                         };
 715
 716                         mmc0_pins: mmc0-pins {
 717                                 pins = "PF0", "PF1", "PF2", "PF3",
 718                                        "PF4", "PF5";
 719                                 function = "mmc0";
 720                                 drive-strength = <30>;
 721                                 bias-pull-up;
 722                         };
 723
 724                         mmc1_pins: mmc1-pins {
 725                                 pins = "PG0", "PG1", "PG2", "PG3",
 726                                        "PG4", "PG5";
 727                                 function = "mmc1";
 728                                 drive-strength = <30>;
 729                                 bias-pull-up;
 730                         };
 731
 732                         mmc2_pins: mmc2-pins {
 733                                 pins = "PC5", "PC6", "PC8", "PC9",
 734                                        "PC10","PC11", "PC12", "PC13",
 735                                        "PC14", "PC15", "PC16";
 736                                 function = "mmc2";
 737                                 drive-strength = <30>;
 738                                 bias-pull-up;
 739                         };
 740
 741                         mmc2_ds_pin: mmc2-ds-pin {
 742                                 pins = "PC1";
 743                                 function = "mmc2";
 744                                 drive-strength = <30>;
 745                                 bias-pull-up;
 746                         };
 747
 748                         pwm_pin: pwm-pin {
 749                                 pins = "PD22";
 750                                 function = "pwm";
 751                         };
 752
 753                         rmii_pins: rmii-pins {
 754                                 pins = "PD10", "PD11", "PD13", "PD14", "PD17",
 755                                        "PD18", "PD19", "PD20", "PD22", "PD23";
 756                                 function = "emac";
 757                                 drive-strength = <40>;
 758                         };
 759
 760                         rgmii_pins: rgmii-pins {
 761                                 pins = "PD8", "PD9", "PD10", "PD11", "PD12",
 762                                        "PD13", "PD15", "PD16", "PD17", "PD18",
 763                                        "PD19", "PD20", "PD21", "PD22", "PD23";
 764                                 function = "emac";
 765                                 drive-strength = <40>;
 766                         };
 767
 768                         spdif_tx_pin: spdif-tx-pin {
 769                                 pins = "PH8";
 770                                 function = "spdif";
 771                         };
 772
 773                         spi0_pins: spi0-pins {
 774                                 pins = "PC0", "PC1", "PC2", "PC3";
 775                                 function = "spi0";
 776                         };
 777
 778                         spi1_pins: spi1-pins {
 779                                 pins = "PD0", "PD1", "PD2", "PD3";
 780                                 function = "spi1";
 781                         };
 782
 783                         uart0_pb_pins: uart0-pb-pins {
 784                                 pins = "PB8", "PB9";
 785                                 function = "uart0";
 786                         };
 787
 788                         uart1_pins: uart1-pins {
 789                                 pins = "PG6", "PG7";
 790                                 function = "uart1";
 791                         };
 792
 793                         uart1_rts_cts_pins: uart1-rts-cts-pins {
 794                                 pins = "PG8", "PG9";
 795                                 function = "uart1";
 796                         };
 797
 798                         uart2_pins: uart2-pins {
 799                                 pins = "PB0", "PB1";
 800                                 function = "uart2";
 801                         };
 802
 803                         uart3_pins: uart3-pins {
 804                                 pins = "PD0", "PD1";
 805                                 function = "uart3";
 806                         };
 807
 808                         uart4_pins: uart4-pins {
 809                                 pins = "PD2", "PD3";
 810                                 function = "uart4";
 811                         };
 812
 813                         uart4_rts_cts_pins: uart4-rts-cts-pins {
 814                                 pins = "PD4", "PD5";
 815                                 function = "uart4";
 816                         };
 817                 };
 818
 819                 timer@1c20c00 {
 820                         compatible = "allwinner,sun50i-a64-timer",
 821                                      "allwinner,sun8i-a23-timer";
 822                         reg = <0x01c20c00 0xa0>;
 823                         interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
 824                                      <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 825                         clocks = <&osc24M>;
 826                 };
 827
 828                 wdt0: watchdog@1c20ca0 {
 829                         compatible = "allwinner,sun50i-a64-wdt",
 830                                      "allwinner,sun6i-a31-wdt";
 831                         reg = <0x01c20ca0 0x20>;
 832                         interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 833                         clocks = <&osc24M>;
 834                 };
 835
 836                 spdif: spdif@1c21000 {
 837                         #sound-dai-cells = <0>;
 838                         compatible = "allwinner,sun50i-a64-spdif",
 839                                      "allwinner,sun8i-h3-spdif";
 840                         reg = <0x01c21000 0x400>;
 841                         interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 842                         clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>;
 843                         resets = <&ccu RST_BUS_SPDIF>;
 844                         clock-names = "apb", "spdif";
 845                         dmas = <&dma 2>;
 846                         dma-names = "tx";
 847                         pinctrl-names = "default";
 848                         pinctrl-0 = <&spdif_tx_pin>;
 849                         status = "disabled";
 850                 };
 851
 852                 lradc: lradc@1c21800 {
 853                         compatible = "allwinner,sun50i-a64-lradc",
 854                                      "allwinner,sun8i-a83t-r-lradc";
 855                         reg = <0x01c21800 0x400>;
 856                         interrupt-parent = <&r_intc>;
 857                         interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 858                         status = "disabled";
 859                 };
 860
 861                 i2s0: i2s@1c22000 {
 862                         #sound-dai-cells = <0>;
 863                         compatible = "allwinner,sun50i-a64-i2s",
 864                                      "allwinner,sun8i-h3-i2s";
 865                         reg = <0x01c22000 0x400>;
 866                         interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 867                         clocks = <&ccu CLK_BUS_I2S0>, <&ccu CLK_I2S0>;
 868                         clock-names = "apb", "mod";
 869                         resets = <&ccu RST_BUS_I2S0>;
 870                         dma-names = "rx", "tx";
 871                         dmas = <&dma 3>, <&dma 3>;
 872                         status = "disabled";
 873                 };
 874
 875                 i2s1: i2s@1c22400 {
 876                         #sound-dai-cells = <0>;
 877                         compatible = "allwinner,sun50i-a64-i2s",
 878                                      "allwinner,sun8i-h3-i2s";
 879                         reg = <0x01c22400 0x400>;
 880                         interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 881                         clocks = <&ccu CLK_BUS_I2S1>, <&ccu CLK_I2S1>;
 882                         clock-names = "apb", "mod";
 883                         resets = <&ccu RST_BUS_I2S1>;
 884                         dma-names = "rx", "tx";
 885                         dmas = <&dma 4>, <&dma 4>;
 886                         status = "disabled";
 887                 };
 888
 889                 i2s2: i2s@1c22800 {
 890                         #sound-dai-cells = <0>;
 891                         compatible = "allwinner,sun50i-a64-i2s",
 892                                      "allwinner,sun8i-h3-i2s";
 893                         reg = <0x01c22800 0x400>;
 894                         interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 895                         clocks = <&ccu CLK_BUS_I2S2>, <&ccu CLK_I2S2>;
 896                         clock-names = "apb", "mod";
 897                         resets = <&ccu RST_BUS_I2S2>;
 898                         dma-names = "rx", "tx";
 899                         dmas = <&dma 27>, <&dma 27>;
 900                         status = "disabled";
 901                 };
 902
 903                 dai: dai@1c22c00 {
 904                         #sound-dai-cells = <0>;
 905                         compatible = "allwinner,sun50i-a64-codec-i2s";
 906                         reg = <0x01c22c00 0x200>;
 907                         interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 908                         clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>;
 909                         clock-names = "apb", "mod";
 910                         resets = <&ccu RST_BUS_CODEC>;
 911                         dmas = <&dma 15>, <&dma 15>;
 912                         dma-names = "rx", "tx";
 913                         status = "disabled";
 914                 };
 915
 916                 codec: codec@1c22e00 {
 917                         #sound-dai-cells = <1>;
 918                         compatible = "allwinner,sun50i-a64-codec",
 919                                      "allwinner,sun8i-a33-codec";
 920                         reg = <0x01c22e00 0x600>;
 921                         interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 922                         clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>;
 923                         clock-names = "bus", "mod";
 924                         status = "disabled";
 925                 };
 926
 927                 ths: thermal-sensor@1c25000 {
 928                         compatible = "allwinner,sun50i-a64-ths";
 929                         reg = <0x01c25000 0x100>;
 930                         clocks = <&ccu CLK_BUS_THS>, <&ccu CLK_THS>;
 931                         clock-names = "bus", "mod";
 932                         interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 933                         resets = <&ccu RST_BUS_THS>;
 934                         nvmem-cells = <&ths_calibration>;
 935                         nvmem-cell-names = "calibration";
 936                         #thermal-sensor-cells = <1>;
 937                 };
 938
 939                 uart0: serial@1c28000 {
 940                         compatible = "snps,dw-apb-uart";
 941                         reg = <0x01c28000 0x400>;
 942                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
 943                         reg-shift = <2>;
 944                         reg-io-width = <4>;
 945                         clocks = <&ccu CLK_BUS_UART0>;
 946                         resets = <&ccu RST_BUS_UART0>;
 947                         status = "disabled";
 948                 };
 949
 950                 uart1: serial@1c28400 {
 951                         compatible = "snps,dw-apb-uart";
 952                         reg = <0x01c28400 0x400>;
 953                         interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 954                         reg-shift = <2>;
 955                         reg-io-width = <4>;
 956                         clocks = <&ccu CLK_BUS_UART1>;
 957                         resets = <&ccu RST_BUS_UART1>;
 958                         status = "disabled";
 959                 };
 960
 961                 uart2: serial@1c28800 {
 962                         compatible = "snps,dw-apb-uart";
 963                         reg = <0x01c28800 0x400>;
 964                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
 965                         reg-shift = <2>;
 966                         reg-io-width = <4>;
 967                         clocks = <&ccu CLK_BUS_UART2>;
 968                         resets = <&ccu RST_BUS_UART2>;
 969                         status = "disabled";
 970                 };
 971
 972                 uart3: serial@1c28c00 {
 973                         compatible = "snps,dw-apb-uart";
 974                         reg = <0x01c28c00 0x400>;
 975                         interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 976                         reg-shift = <2>;
 977                         reg-io-width = <4>;
 978                         clocks = <&ccu CLK_BUS_UART3>;
 979                         resets = <&ccu RST_BUS_UART3>;
 980                         status = "disabled";
 981                 };
 982
 983                 uart4: serial@1c29000 {
 984                         compatible = "snps,dw-apb-uart";
 985                         reg = <0x01c29000 0x400>;
 986                         interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 987                         reg-shift = <2>;
 988                         reg-io-width = <4>;
 989                         clocks = <&ccu CLK_BUS_UART4>;
 990                         resets = <&ccu RST_BUS_UART4>;
 991                         status = "disabled";
 992                 };
 993
 994                 i2c0: i2c@1c2ac00 {
 995                         compatible = "allwinner,sun6i-a31-i2c";
 996                         reg = <0x01c2ac00 0x400>;
 997                         interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
 998                         clocks = <&ccu CLK_BUS_I2C0>;
 999                         resets = <&ccu RST_BUS_I2C0>;
1000                         pinctrl-names = "default";
1001                         pinctrl-0 = <&i2c0_pins>;
1002                         status = "disabled";
1003                         #address-cells = <1>;
1004                         #size-cells = <0>;
1005                 };
1006
1007                 i2c1: i2c@1c2b000 {
1008                         compatible = "allwinner,sun6i-a31-i2c";
1009                         reg = <0x01c2b000 0x400>;
1010                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
1011                         clocks = <&ccu CLK_BUS_I2C1>;
1012                         resets = <&ccu RST_BUS_I2C1>;
1013                         pinctrl-names = "default";
1014                         pinctrl-0 = <&i2c1_pins>;
1015                         status = "disabled";
1016                         #address-cells = <1>;
1017                         #size-cells = <0>;
1018                 };
1019
1020                 i2c2: i2c@1c2b400 {
1021                         compatible = "allwinner,sun6i-a31-i2c";
1022                         reg = <0x01c2b400 0x400>;
1023                         interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1024                         clocks = <&ccu CLK_BUS_I2C2>;
1025                         resets = <&ccu RST_BUS_I2C2>;
1026                         pinctrl-names = "default";
1027                         pinctrl-0 = <&i2c2_pins>;
1028                         status = "disabled";
1029                         #address-cells = <1>;
1030                         #size-cells = <0>;
1031                 };
1032
1033                 spi0: spi@1c68000 {
1034                         compatible = "allwinner,sun8i-h3-spi";
1035                         reg = <0x01c68000 0x1000>;
1036                         interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
1037                         clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
1038                         clock-names = "ahb", "mod";
1039                         dmas = <&dma 23>, <&dma 23>;
1040                         dma-names = "rx", "tx";
1041                         pinctrl-names = "default";
1042                         pinctrl-0 = <&spi0_pins>;
1043                         resets = <&ccu RST_BUS_SPI0>;
1044                         status = "disabled";
1045                         num-cs = <1>;
1046                         #address-cells = <1>;
1047                         #size-cells = <0>;
1048                 };
1049
1050                 spi1: spi@1c69000 {
1051                         compatible = "allwinner,sun8i-h3-spi";
1052                         reg = <0x01c69000 0x1000>;
1053                         interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
1054                         clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>;
1055                         clock-names = "ahb", "mod";
1056                         dmas = <&dma 24>, <&dma 24>;
1057                         dma-names = "rx", "tx";
1058                         pinctrl-names = "default";
1059                         pinctrl-0 = <&spi1_pins>;
1060                         resets = <&ccu RST_BUS_SPI1>;
1061                         status = "disabled";
1062                         num-cs = <1>;
1063                         #address-cells = <1>;
1064                         #size-cells = <0>;
1065                 };
1066
1067                 emac: ethernet@1c30000 {
1068                         compatible = "allwinner,sun50i-a64-emac";
1069                         syscon = <&syscon>;
1070                         reg = <0x01c30000 0x10000>;
1071                         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
1072                         interrupt-names = "macirq";
1073                         resets = <&ccu RST_BUS_EMAC>;
1074                         reset-names = "stmmaceth";
1075                         clocks = <&ccu CLK_BUS_EMAC>;
1076                         clock-names = "stmmaceth";
1077                         status = "disabled";
1078
1079                         mdio: mdio {
1080                                 compatible = "snps,dwmac-mdio";
1081                                 #address-cells = <1>;
1082                                 #size-cells = <0>;
1083                         };
1084                 };
1085
1086                 mali: gpu@1c40000 {
1087                         compatible = "allwinner,sun50i-a64-mali", "arm,mali-400";
1088                         reg = <0x01c40000 0x10000>;
1089                         interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
1090                                      <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
1091                                      <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
1092                                      <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
1093                                      <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
1094                                      <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
1095                                      <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
1096                         interrupt-names = "gp",
1097                                           "gpmmu",
1098                                           "pp0",
1099                                           "ppmmu0",
1100                                           "pp1",
1101                                           "ppmmu1",
1102                                           "pmu";
1103                         clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>;
1104                         clock-names = "bus", "core";
1105                         resets = <&ccu RST_BUS_GPU>;
1106                 };
1107
1108                 gic: interrupt-controller@1c81000 {
1109                         compatible = "arm,gic-400";
1110                         reg = <0x01c81000 0x1000>,
1111                               <0x01c82000 0x2000>,
1112                               <0x01c84000 0x2000>,
1113                               <0x01c86000 0x2000>;
1114                         interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
1115                         interrupt-controller;
1116                         #interrupt-cells = <3>;
1117                 };
1118
1119                 pwm: pwm@1c21400 {
1120                         compatible = "allwinner,sun50i-a64-pwm",
1121                                      "allwinner,sun5i-a13-pwm";
1122                         reg = <0x01c21400 0x400>;
1123                         clocks = <&osc24M>;
1124                         pinctrl-names = "default";
1125                         pinctrl-0 = <&pwm_pin>;
1126                         #pwm-cells = <3>;
1127                         status = "disabled";
1128                 };
1129
1130                 mbus: dram-controller@1c62000 {
1131                         compatible = "allwinner,sun50i-a64-mbus";
1132                         reg = <0x01c62000 0x1000>;
1133                         clocks = <&ccu 112>;
1134                         #address-cells = <1>;
1135                         #size-cells = <1>;
1136                         dma-ranges = <0x00000000 0x40000000 0xc0000000>;
1137                         #interconnect-cells = <1>;
1138                 };
1139
1140                 csi: csi@1cb0000 {
1141                         compatible = "allwinner,sun50i-a64-csi";
1142                         reg = <0x01cb0000 0x1000>;
1143                         interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1144                         clocks = <&ccu CLK_BUS_CSI>,
1145                                  <&ccu CLK_CSI_SCLK>,
1146                                  <&ccu CLK_DRAM_CSI>;
1147                         clock-names = "bus", "mod", "ram";
1148                         resets = <&ccu RST_BUS_CSI>;
1149                         pinctrl-names = "default";
1150                         pinctrl-0 = <&csi_pins>;
1151                         status = "disabled";
1152                 };
1153
1154                 dsi: dsi@1ca0000 {
1155                         compatible = "allwinner,sun50i-a64-mipi-dsi";
1156                         reg = <0x01ca0000 0x1000>;
1157                         interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
1158                         clocks = <&ccu CLK_BUS_MIPI_DSI>;
1159                         resets = <&ccu RST_BUS_MIPI_DSI>;
1160                         phys = <&dphy>;
1161                         phy-names = "dphy";
1162                         status = "disabled";
1163                         #address-cells = <1>;
1164                         #size-cells = <0>;
1165
1166                         port {
1167                                 dsi_in_tcon0: endpoint {
1168                                         remote-endpoint = <&tcon0_out_dsi>;
1169                                 };
1170                         };
1171                 };
1172
1173                 dphy: d-phy@1ca1000 {
1174                         compatible = "allwinner,sun50i-a64-mipi-dphy",
1175                                      "allwinner,sun6i-a31-mipi-dphy";
1176                         reg = <0x01ca1000 0x1000>;
1177                         clocks = <&ccu CLK_BUS_MIPI_DSI>,
1178                                  <&ccu CLK_DSI_DPHY>;
1179                         clock-names = "bus", "mod";
1180                         resets = <&ccu RST_BUS_MIPI_DSI>;
1181                         status = "disabled";
1182                         #phy-cells = <0>;
1183                 };
1184
1185                 deinterlace: deinterlace@1e00000 {
1186                         compatible = "allwinner,sun50i-a64-deinterlace",
1187                                      "allwinner,sun8i-h3-deinterlace";
1188                         reg = <0x01e00000 0x20000>;
1189                         clocks = <&ccu CLK_BUS_DEINTERLACE>,
1190                                  <&ccu CLK_DEINTERLACE>,
1191                                  <&ccu CLK_DRAM_DEINTERLACE>;
1192                         clock-names = "bus", "mod", "ram";
1193                         resets = <&ccu RST_BUS_DEINTERLACE>;
1194                         interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
1195                         interconnects = <&mbus 9>;
1196                         interconnect-names = "dma-mem";
1197                 };
1198
1199                 hdmi: hdmi@1ee0000 {
1200                         compatible = "allwinner,sun50i-a64-dw-hdmi",
1201                                      "allwinner,sun8i-a83t-dw-hdmi";
1202                         reg = <0x01ee0000 0x10000>;
1203                         reg-io-width = <1>;
1204                         interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
1205                         clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>,
1206                                  <&ccu CLK_HDMI>;
1207                         clock-names = "iahb", "isfr", "tmds";
1208                         resets = <&ccu RST_BUS_HDMI1>;
1209                         reset-names = "ctrl";
1210                         phys = <&hdmi_phy>;
1211                         phy-names = "phy";
1212                         status = "disabled";
1213
1214                         ports {
1215                                 #address-cells = <1>;
1216                                 #size-cells = <0>;
1217
1218                                 hdmi_in: port@0 {
1219                                         reg = <0>;
1220
1221                                         hdmi_in_tcon1: endpoint {
1222                                                 remote-endpoint = <&tcon1_out_hdmi>;
1223                                         };
1224                                 };
1225
1226                                 hdmi_out: port@1 {
1227                                         reg = <1>;
1228                                 };
1229                         };
1230                 };
1231
1232                 hdmi_phy: hdmi-phy@1ef0000 {
1233                         compatible = "allwinner,sun50i-a64-hdmi-phy";
1234                         reg = <0x01ef0000 0x10000>;
1235                         clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>,
1236                                  <&ccu CLK_PLL_VIDEO0>;
1237                         clock-names = "bus", "mod", "pll-0";
1238                         resets = <&ccu RST_BUS_HDMI0>;
1239                         reset-names = "phy";
1240                         #phy-cells = <0>;
1241                 };
1242
1243                 rtc: rtc@1f00000 {
1244                         compatible = "allwinner,sun50i-a64-rtc",
1245                                      "allwinner,sun8i-h3-rtc";
1246                         reg = <0x01f00000 0x400>;
1247                         interrupt-parent = <&r_intc>;
1248                         interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
1249                                      <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
1250                         clock-output-names = "osc32k", "osc32k-out", "iosc";
1251                         clocks = <&osc32k>;
1252                         #clock-cells = <1>;
1253                 };
1254
1255                 r_intc: interrupt-controller@1f00c00 {
1256                         compatible = "allwinner,sun50i-a64-r-intc",
1257                                      "allwinner,sun6i-a31-r-intc";
1258                         interrupt-controller;
1259                         #interrupt-cells = <3>;
1260                         reg = <0x01f00c00 0x400>;
1261                         interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
1262                 };
1263
1264                 r_ccu: clock@1f01400 {
1265                         compatible = "allwinner,sun50i-a64-r-ccu";
1266                         reg = <0x01f01400 0x100>;
1267                         clocks = <&osc24M>, <&rtc 0>, <&rtc 2>,
1268                                  <&ccu CLK_PLL_PERIPH0>;
1269                         clock-names = "hosc", "losc", "iosc", "pll-periph";
1270                         #clock-cells = <1>;
1271                         #reset-cells = <1>;
1272                 };
1273
1274                 codec_analog: codec-analog@1f015c0 {
1275                         compatible = "allwinner,sun50i-a64-codec-analog";
1276                         reg = <0x01f015c0 0x4>;
1277                         status = "disabled";
1278                 };
1279
1280                 r_i2c: i2c@1f02400 {
1281                         compatible = "allwinner,sun50i-a64-i2c",
1282                                      "allwinner,sun6i-a31-i2c";
1283                         reg = <0x01f02400 0x400>;
1284                         interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
1285                         clocks = <&r_ccu CLK_APB0_I2C>;
1286                         resets = <&r_ccu RST_APB0_I2C>;
1287                         status = "disabled";
1288                         #address-cells = <1>;
1289                         #size-cells = <0>;
1290                 };
1291
1292                 r_ir: ir@1f02000 {
1293                         compatible = "allwinner,sun50i-a64-ir",
1294                                      "allwinner,sun6i-a31-ir";
1295                         reg = <0x01f02000 0x400>;
1296                         clocks = <&r_ccu CLK_APB0_IR>, <&r_ccu CLK_IR>;
1297                         clock-names = "apb", "ir";
1298                         resets = <&r_ccu RST_APB0_IR>;
1299                         interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
1300                         pinctrl-names = "default";
1301                         pinctrl-0 = <&r_ir_rx_pin>;
1302                         status = "disabled";
1303                 };
1304
1305                 r_pwm: pwm@1f03800 {
1306                         compatible = "allwinner,sun50i-a64-pwm",
1307                                      "allwinner,sun5i-a13-pwm";
1308                         reg = <0x01f03800 0x400>;
1309                         clocks = <&osc24M>;
1310                         pinctrl-names = "default";
1311                         pinctrl-0 = <&r_pwm_pin>;
1312                         #pwm-cells = <3>;
1313                         status = "disabled";
1314                 };
1315
1316                 r_pio: pinctrl@1f02c00 {
1317                         compatible = "allwinner,sun50i-a64-r-pinctrl";
1318                         reg = <0x01f02c00 0x400>;
1319                         interrupt-parent = <&r_intc>;
1320                         interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
1321                         clocks = <&r_ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>;
1322                         clock-names = "apb", "hosc", "losc";
1323                         gpio-controller;
1324                         #gpio-cells = <3>;
1325                         interrupt-controller;
1326                         #interrupt-cells = <3>;
1327
1328                         r_i2c_pl89_pins: r-i2c-pl89-pins {
1329                                 pins = "PL8", "PL9";
1330                                 function = "s_i2c";
1331                         };
1332
1333                         r_ir_rx_pin: r-ir-rx-pin {
1334                                 pins = "PL11";
1335                                 function = "s_cir_rx";
1336                         };
1337
1338                         r_pwm_pin: r-pwm-pin {
1339                                 pins = "PL10";
1340                                 function = "s_pwm";
1341                         };
1342
1343                         r_rsb_pins: r-rsb-pins {
1344                                 pins = "PL0", "PL1";
1345                                 function = "s_rsb";
1346                         };
1347                 };
1348
1349                 r_rsb: rsb@1f03400 {
1350                         compatible = "allwinner,sun8i-a23-rsb";
1351                         reg = <0x01f03400 0x400>;
1352                         interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
1353                         clocks = <&r_ccu 6>;
1354                         clock-frequency = <3000000>;
1355                         resets = <&r_ccu 2>;
1356                         pinctrl-names = "default";
1357                         pinctrl-0 = <&r_rsb_pins>;
1358                         status = "disabled";
1359                         #address-cells = <1>;
1360                         #size-cells = <0>;
1361                 };
1362         };
1363 };