arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ or MIT)
   2 /*
   3  * Copyright (c) 2020 Yangtao Li <frank@allwinnertech.com>
   4  */
   5
   6 #include <dt-bindings/interrupt-controller/arm-gic.h>
   7 #include <dt-bindings/clock/sun50i-a100-ccu.h>
   8 #include <dt-bindings/clock/sun50i-a100-r-ccu.h>
   9 #include <dt-bindings/reset/sun50i-a100-ccu.h>
  10 #include <dt-bindings/reset/sun50i-a100-r-ccu.h>
  11
  12 / {
  13         interrupt-parent = <&gic>;
  14         #address-cells = <2>;
  15         #size-cells = <2>;
  16
  17         cpus {
  18                 #address-cells = <1>;
  19                 #size-cells = <0>;
  20
  21                 cpu0: cpu@0 {
  22                         compatible = "arm,cortex-a53";
  23                         device_type = "cpu";
  24                         reg = <0x0>;
  25                         enable-method = "psci";
  26                 };
  27
  28                 cpu@1 {
  29                         compatible = "arm,cortex-a53";
  30                         device_type = "cpu";
  31                         reg = <0x1>;
  32                         enable-method = "psci";
  33                 };
  34
  35                 cpu@2 {
  36                         compatible = "arm,cortex-a53";
  37                         device_type = "cpu";
  38                         reg = <0x2>;
  39                         enable-method = "psci";
  40                 };
  41
  42                 cpu@3 {
  43                         compatible = "arm,cortex-a53";
  44                         device_type = "cpu";
  45                         reg = <0x3>;
  46                         enable-method = "psci";
  47                 };
  48         };
  49
  50         psci {
  51                 compatible = "arm,psci-1.0";
  52                 method = "smc";
  53         };
  54
  55         dcxo24M: dcxo24M-clk {
  56                 compatible = "fixed-clock";
  57                 clock-frequency = <24000000>;
  58                 clock-output-names = "dcxo24M";
  59                 #clock-cells = <0>;
  60         };
  61
  62         iosc: internal-osc-clk {
  63                 compatible = "fixed-clock";
  64                 clock-frequency = <16000000>;
  65                 clock-accuracy = <300000000>;
  66                 clock-output-names = "iosc";
  67                 #clock-cells = <0>;
  68         };
  69
  70         osc32k: osc32k-clk {
  71                 compatible = "fixed-clock";
  72                 clock-frequency = <32768>;
  73                 clock-output-names = "osc32k";
  74                 #clock-cells = <0>;
  75         };
  76
  77         timer {
  78                 compatible = "arm,armv8-timer";
  79                 interrupts = <GIC_PPI 13
  80                         (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
  81                              <GIC_PPI 14
  82                         (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
  83                              <GIC_PPI 11
  84                         (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
  85                              <GIC_PPI 10
  86                         (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
  87         };
  88
  89         soc {
  90                 compatible = "simple-bus";
  91                 #address-cells = <1>;
  92                 #size-cells = <1>;
  93                 ranges = <0 0 0 0x3fffffff>;
  94
  95                 ccu: clock@3001000 {
  96                         compatible = "allwinner,sun50i-a100-ccu";
  97                         reg = <0x03001000 0x1000>;
  98                         clocks = <&dcxo24M>, <&osc32k>, <&iosc>;
  99                         clock-names = "hosc", "losc", "iosc";
 100                         #clock-cells = <1>;
 101                         #reset-cells = <1>;
 102                 };
 103
 104                 gic: interrupt-controller@3021000 {
 105                         compatible = "arm,gic-400";
 106                         reg = <0x03021000 0x1000>, <0x03022000 0x2000>,
 107                               <0x03024000 0x2000>, <0x03026000 0x2000>;
 108                         interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) |
 109                                                  IRQ_TYPE_LEVEL_HIGH)>;
 110                         interrupt-controller;
 111                         #interrupt-cells = <3>;
 112                 };
 113
 114                 efuse@3006000 {
 115                         compatible = "allwinner,sun50i-a100-sid",
 116                                      "allwinner,sun50i-a64-sid";
 117                         reg = <0x03006000 0x1000>;
 118                         #address-cells = <1>;
 119                         #size-cells = <1>;
 120
 121                         ths_calibration: calib@14 {
 122                                 reg = <0x14 8>;
 123                         };
 124                 };
 125
 126                 pio: pinctrl@300b000 {
 127                         compatible = "allwinner,sun50i-a100-pinctrl";
 128                         reg = <0x0300b000 0x400>;
 129                         interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
 130                                      <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
 131                                      <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
 132                                      <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
 133                                      <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
 134                                      <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
 135                                      <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 136                         clocks = <&ccu CLK_APB1>, <&dcxo24M>, <&osc32k>;
 137                         clock-names = "apb", "hosc", "losc";
 138                         gpio-controller;
 139                         #gpio-cells = <3>;
 140                         interrupt-controller;
 141                         #interrupt-cells = <3>;
 142
 143                         uart0_pb_pins: uart0-pb-pins {
 144                                 pins = "PB9", "PB10";
 145                                 function = "uart0";
 146                         };
 147                 };
 148
 149                 uart0: serial@5000000 {
 150                         compatible = "snps,dw-apb-uart";
 151                         reg = <0x05000000 0x400>;
 152                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
 153                         reg-shift = <2>;
 154                         reg-io-width = <4>;
 155                         clocks = <&ccu CLK_BUS_UART0>;
 156                         resets = <&ccu RST_BUS_UART0>;
 157                         status = "disabled";
 158                 };
 159
 160                 uart1: serial@5000400 {
 161                         compatible = "snps,dw-apb-uart";
 162                         reg = <0x05000400 0x400>;
 163                         interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 164                         reg-shift = <2>;
 165                         reg-io-width = <4>;
 166                         clocks = <&ccu CLK_BUS_UART1>;
 167                         resets = <&ccu RST_BUS_UART1>;
 168                         status = "disabled";
 169                 };
 170
 171                 uart2: serial@5000800 {
 172                         compatible = "snps,dw-apb-uart";
 173                         reg = <0x05000800 0x400>;
 174                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
 175                         reg-shift = <2>;
 176                         reg-io-width = <4>;
 177                         clocks = <&ccu CLK_BUS_UART2>;
 178                         resets = <&ccu RST_BUS_UART2>;
 179                         status = "disabled";
 180                 };
 181
 182                 uart3: serial@5000c00 {
 183                         compatible = "snps,dw-apb-uart";
 184                         reg = <0x05000c00 0x400>;
 185                         interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 186                         reg-shift = <2>;
 187                         reg-io-width = <4>;
 188                         clocks = <&ccu CLK_BUS_UART3>;
 189                         resets = <&ccu RST_BUS_UART3>;
 190                         status = "disabled";
 191                 };
 192
 193                 uart4: serial@5001000 {
 194                         compatible = "snps,dw-apb-uart";
 195                         reg = <0x05001000 0x400>;
 196                         interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 197                         reg-shift = <2>;
 198                         reg-io-width = <4>;
 199                         clocks = <&ccu CLK_BUS_UART4>;
 200                         resets = <&ccu RST_BUS_UART4>;
 201                         status = "disabled";
 202                 };
 203
 204                 i2c0: i2c@5002000 {
 205                         compatible = "allwinner,sun50i-a100-i2c",
 206                                      "allwinner,sun6i-a31-i2c";
 207                         reg = <0x05002000 0x400>;
 208                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 209                         clocks = <&ccu CLK_BUS_I2C0>;
 210                         resets = <&ccu RST_BUS_I2C0>;
 211                         status = "disabled";
 212                         #address-cells = <1>;
 213                         #size-cells = <0>;
 214                 };
 215
 216                 i2c1: i2c@5002400 {
 217                         compatible = "allwinner,sun50i-a100-i2c",
 218                                      "allwinner,sun6i-a31-i2c";
 219                         reg = <0x05002400 0x400>;
 220                         interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 221                         clocks = <&ccu CLK_BUS_I2C1>;
 222                         resets = <&ccu RST_BUS_I2C1>;
 223                         status = "disabled";
 224                         #address-cells = <1>;
 225                         #size-cells = <0>;
 226                 };
 227
 228                 i2c2: i2c@5002800 {
 229                         compatible = "allwinner,sun50i-a100-i2c",
 230                                      "allwinner,sun6i-a31-i2c";
 231                         reg = <0x05002800 0x400>;
 232                         interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
 233                         clocks = <&ccu CLK_BUS_I2C2>;
 234                         resets = <&ccu RST_BUS_I2C2>;
 235                         status = "disabled";
 236                         #address-cells = <1>;
 237                         #size-cells = <0>;
 238                 };
 239
 240                 i2c3: i2c@5002c00 {
 241                         compatible = "allwinner,sun50i-a100-i2c",
 242                                      "allwinner,sun6i-a31-i2c";
 243                         reg = <0x05002c00 0x400>;
 244                         interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 245                         clocks = <&ccu CLK_BUS_I2C3>;
 246                         resets = <&ccu RST_BUS_I2C3>;
 247                         status = "disabled";
 248                         #address-cells = <1>;
 249                         #size-cells = <0>;
 250                 };
 251
 252                 ths: thermal-sensor@5070400 {
 253                         compatible = "allwinner,sun50i-a100-ths";
 254                         reg = <0x05070400 0x100>;
 255                         interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
 256                         clocks = <&ccu CLK_BUS_THS>;
 257                         clock-names = "bus";
 258                         resets = <&ccu RST_BUS_THS>;
 259                         nvmem-cells = <&ths_calibration>;
 260                         nvmem-cell-names = "calibration";
 261                         #thermal-sensor-cells = <1>;
 262                 };
 263
 264                 r_ccu: clock@7010000 {
 265                         compatible = "allwinner,sun50i-a100-r-ccu";
 266                         reg = <0x07010000 0x300>;
 267                         clocks = <&dcxo24M>, <&osc32k>, <&iosc>,
 268                                  <&ccu CLK_PLL_PERIPH0>;
 269                         clock-names = "hosc", "losc", "iosc", "pll-periph";
 270                         #clock-cells = <1>;
 271                         #reset-cells = <1>;
 272                 };
 273
 274                 r_intc: interrupt-controller@7010320 {
 275                         compatible = "allwinner,sun50i-a100-nmi",
 276                                      "allwinner,sun9i-a80-nmi";
 277                         interrupt-controller;
 278                         #interrupt-cells = <2>;
 279                         reg = <0x07010320 0xc>;
 280                         interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 281                 };
 282
 283                 r_pio: pinctrl@7022000 {
 284                         compatible = "allwinner,sun50i-a100-r-pinctrl";
 285                         reg = <0x07022000 0x400>;
 286                         interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
 287                         clocks = <&r_ccu CLK_R_APB1>, <&dcxo24M>, <&osc32k>;
 288                         clock-names = "apb", "hosc", "losc";
 289                         gpio-controller;
 290                         #gpio-cells = <3>;
 291                         interrupt-controller;
 292                         #interrupt-cells = <3>;
 293
 294                         r_i2c0_pins: r-i2c0-pins {
 295                                 pins = "PL0", "PL1";
 296                                 function = "s_i2c0";
 297                         };
 298
 299                         r_i2c1_pins: r-i2c1-pins {
 300                                 pins = "PL8", "PL9";
 301                                 function = "s_i2c1";
 302                         };
 303                 };
 304
 305                 r_uart: serial@7080000 {
 306                         compatible = "snps,dw-apb-uart";
 307                         reg = <0x07080000 0x400>;
 308                         interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
 309                         reg-shift = <2>;
 310                         reg-io-width = <4>;
 311                         clocks = <&r_ccu CLK_R_APB2_UART>;
 312                         resets = <&r_ccu RST_R_APB2_UART>;
 313                         status = "disabled";
 314                 };
 315
 316                 r_i2c0: i2c@7081400 {
 317                         compatible = "allwinner,sun50i-a100-i2c",
 318                                      "allwinner,sun6i-a31-i2c";
 319                         reg = <0x07081400 0x400>;
 320                         interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
 321                         clocks = <&r_ccu CLK_R_APB2_I2C0>;
 322                         resets = <&r_ccu RST_R_APB2_I2C0>;
 323                         pinctrl-names = "default";
 324                         pinctrl-0 = <&r_i2c0_pins>;
 325                         status = "disabled";
 326                         #address-cells = <1>;
 327                         #size-cells = <0>;
 328                 };
 329
 330                 r_i2c1: i2c@7081800 {
 331                         compatible = "allwinner,sun50i-a100-i2c",
 332                                      "allwinner,sun6i-a31-i2c";
 333                         reg = <0x07081800 0x400>;
 334                         interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
 335                         clocks = <&r_ccu CLK_R_APB2_I2C1>;
 336                         resets = <&r_ccu RST_R_APB2_I2C1>;
 337                         pinctrl-names = "default";
 338                         pinctrl-0 = <&r_i2c1_pins>;
 339                         status = "disabled";
 340                         #address-cells = <1>;
 341                         #size-cells = <0>;
 342                 };
 343         };
 344
 345         thermal-zones {
 346                 cpu-thermal-zone {
 347                         polling-delay-passive = <0>;
 348                         polling-delay = <0>;
 349                         thermal-sensors = <&ths 0>;
 350                 };
 351
 352                 ddr-thermal-zone {
 353                         polling-delay-passive = <0>;
 354                         polling-delay = <0>;
 355                         thermal-sensors = <&ths 2>;
 356                 };
 357
 358                 gpu-thermal-zone {
 359                         polling-delay-passive = <0>;
 360                         polling-delay = <0>;
 361                         thermal-sensors = <&ths 1>;
 362                 };
 363         };
 364 };