1 # SPDX-License-Identifier: GPL-2.0-only
4 select ACPI_CCA_REQUIRED if ACPI
5 select ACPI_GENERIC_GSI if ACPI
6 select ACPI_GTDT if ACPI
7 select ACPI_IORT if ACPI
8 select ACPI_REDUCED_HARDWARE_ONLY if ACPI
9 select ACPI_MCFG if (ACPI && PCI)
10 select ACPI_SPCR_TABLE if ACPI
11 select ACPI_PPTT if ACPI
12 select ARCH_CLOCKSOURCE_DATA
13 select ARCH_HAS_DEBUG_VIRTUAL
14 select ARCH_HAS_DEVMEM_IS_ALLOWED
15 select ARCH_HAS_DMA_PREP_COHERENT
16 select ARCH_HAS_ACPI_TABLE_UPGRADE if ACPI
17 select ARCH_HAS_FAST_MULTIPLIER
18 select ARCH_HAS_FORTIFY_SOURCE
19 select ARCH_HAS_GCOV_PROFILE_ALL
20 select ARCH_HAS_GIGANTIC_PAGE
22 select ARCH_HAS_KEEPINITRD
23 select ARCH_HAS_MEMBARRIER_SYNC_CORE
24 select ARCH_HAS_PTE_DEVMAP
25 select ARCH_HAS_PTE_SPECIAL
26 select ARCH_HAS_SETUP_DMA_OPS
27 select ARCH_HAS_SET_DIRECT_MAP
28 select ARCH_HAS_SET_MEMORY
29 select ARCH_HAS_STRICT_KERNEL_RWX
30 select ARCH_HAS_STRICT_MODULE_RWX
31 select ARCH_HAS_SYNC_DMA_FOR_DEVICE
32 select ARCH_HAS_SYNC_DMA_FOR_CPU
33 select ARCH_HAS_SYSCALL_WRAPPER
34 select ARCH_HAS_TEARDOWN_DMA_OPS if IOMMU_SUPPORT
35 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
36 select ARCH_HAVE_NMI_SAFE_CMPXCHG
37 select ARCH_INLINE_READ_LOCK if !PREEMPT
38 select ARCH_INLINE_READ_LOCK_BH if !PREEMPT
39 select ARCH_INLINE_READ_LOCK_IRQ if !PREEMPT
40 select ARCH_INLINE_READ_LOCK_IRQSAVE if !PREEMPT
41 select ARCH_INLINE_READ_UNLOCK if !PREEMPT
42 select ARCH_INLINE_READ_UNLOCK_BH if !PREEMPT
43 select ARCH_INLINE_READ_UNLOCK_IRQ if !PREEMPT
44 select ARCH_INLINE_READ_UNLOCK_IRQRESTORE if !PREEMPT
45 select ARCH_INLINE_WRITE_LOCK if !PREEMPT
46 select ARCH_INLINE_WRITE_LOCK_BH if !PREEMPT
47 select ARCH_INLINE_WRITE_LOCK_IRQ if !PREEMPT
48 select ARCH_INLINE_WRITE_LOCK_IRQSAVE if !PREEMPT
49 select ARCH_INLINE_WRITE_UNLOCK if !PREEMPT
50 select ARCH_INLINE_WRITE_UNLOCK_BH if !PREEMPT
51 select ARCH_INLINE_WRITE_UNLOCK_IRQ if !PREEMPT
52 select ARCH_INLINE_WRITE_UNLOCK_IRQRESTORE if !PREEMPT
53 select ARCH_INLINE_SPIN_TRYLOCK if !PREEMPT
54 select ARCH_INLINE_SPIN_TRYLOCK_BH if !PREEMPT
55 select ARCH_INLINE_SPIN_LOCK if !PREEMPT
56 select ARCH_INLINE_SPIN_LOCK_BH if !PREEMPT
57 select ARCH_INLINE_SPIN_LOCK_IRQ if !PREEMPT
58 select ARCH_INLINE_SPIN_LOCK_IRQSAVE if !PREEMPT
59 select ARCH_INLINE_SPIN_UNLOCK if !PREEMPT
60 select ARCH_INLINE_SPIN_UNLOCK_BH if !PREEMPT
61 select ARCH_INLINE_SPIN_UNLOCK_IRQ if !PREEMPT
62 select ARCH_INLINE_SPIN_UNLOCK_IRQRESTORE if !PREEMPT
63 select ARCH_KEEP_MEMBLOCK
64 select ARCH_USE_CMPXCHG_LOCKREF
65 select ARCH_USE_QUEUED_RWLOCKS
66 select ARCH_USE_QUEUED_SPINLOCKS
67 select ARCH_SUPPORTS_MEMORY_FAILURE
68 select ARCH_SUPPORTS_ATOMIC_RMW
69 select ARCH_SUPPORTS_INT128 if CC_HAS_INT128 && (GCC_VERSION >= 50000 || CC_IS_CLANG)
70 select ARCH_SUPPORTS_NUMA_BALANCING
71 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION if COMPAT
72 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT
73 select ARCH_WANT_FRAME_POINTERS
74 select ARCH_WANT_HUGE_PMD_SHARE if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36)
75 select ARCH_HAS_UBSAN_SANITIZE_ALL
79 select AUDIT_ARCH_COMPAT_GENERIC
80 select ARM_GIC_V2M if PCI
82 select ARM_GIC_V3_ITS if PCI
84 select BUILDTIME_EXTABLE_SORT
85 select CLONE_BACKWARDS
87 select CPU_PM if (SUSPEND || CPU_IDLE)
89 select DCACHE_WORD_ACCESS
90 select DMA_DIRECT_REMAP
93 select GENERIC_ALLOCATOR
94 select GENERIC_ARCH_TOPOLOGY
95 select GENERIC_CLOCKEVENTS
96 select GENERIC_CLOCKEVENTS_BROADCAST
97 select GENERIC_CPU_AUTOPROBE
98 select GENERIC_CPU_VULNERABILITIES
99 select GENERIC_EARLY_IOREMAP
100 select GENERIC_IDLE_POLL_SETUP
101 select GENERIC_IRQ_MULTI_HANDLER
102 select GENERIC_IRQ_PROBE
103 select GENERIC_IRQ_SHOW
104 select GENERIC_IRQ_SHOW_LEVEL
105 select GENERIC_PCI_IOMAP
106 select GENERIC_SCHED_CLOCK
107 select GENERIC_SMP_IDLE_THREAD
108 select GENERIC_STRNCPY_FROM_USER
109 select GENERIC_STRNLEN_USER
110 select GENERIC_TIME_VSYSCALL
111 select GENERIC_GETTIMEOFDAY
112 select HANDLE_DOMAIN_IRQ
113 select HARDIRQS_SW_RESEND
115 select HAVE_ACPI_APEI if (ACPI && EFI)
116 select HAVE_ALIGNED_STRUCT_PAGE if SLUB
117 select HAVE_ARCH_AUDITSYSCALL
118 select HAVE_ARCH_BITREVERSE
119 select HAVE_ARCH_HUGE_VMAP
120 select HAVE_ARCH_JUMP_LABEL
121 select HAVE_ARCH_JUMP_LABEL_RELATIVE
122 select HAVE_ARCH_KASAN if !(ARM64_16K_PAGES && ARM64_VA_BITS_48)
123 select HAVE_ARCH_KASAN_SW_TAGS if HAVE_ARCH_KASAN
124 select HAVE_ARCH_KGDB
125 select HAVE_ARCH_MMAP_RND_BITS
126 select HAVE_ARCH_MMAP_RND_COMPAT_BITS if COMPAT
127 select HAVE_ARCH_PREL32_RELOCATIONS
128 select HAVE_ARCH_SECCOMP_FILTER
129 select HAVE_ARCH_STACKLEAK
130 select HAVE_ARCH_THREAD_STRUCT_WHITELIST
131 select HAVE_ARCH_TRACEHOOK
132 select HAVE_ARCH_TRANSPARENT_HUGEPAGE
133 select HAVE_ARCH_VMAP_STACK
134 select HAVE_ARM_SMCCC
135 select HAVE_ASM_MODVERSIONS
137 select HAVE_C_RECORDMCOUNT
138 select HAVE_CMPXCHG_DOUBLE
139 select HAVE_CMPXCHG_LOCAL
140 select HAVE_CONTEXT_TRACKING
141 select HAVE_DEBUG_BUGVERBOSE
142 select HAVE_DEBUG_KMEMLEAK
143 select HAVE_DMA_CONTIGUOUS
144 select HAVE_DYNAMIC_FTRACE
145 select HAVE_DYNAMIC_FTRACE_WITH_REGS \
146 if $(cc-option,-fpatchable-function-entry=2)
147 select HAVE_EFFICIENT_UNALIGNED_ACCESS
149 select HAVE_FTRACE_MCOUNT_RECORD
150 select HAVE_FUNCTION_TRACER
151 select HAVE_FUNCTION_ERROR_INJECTION
152 select HAVE_FUNCTION_GRAPH_TRACER
153 select HAVE_GCC_PLUGINS
154 select HAVE_HW_BREAKPOINT if PERF_EVENTS
155 select HAVE_IRQ_TIME_ACCOUNTING
156 select HAVE_MEMBLOCK_NODE_MAP if NUMA
158 select HAVE_PATA_PLATFORM
159 select HAVE_PERF_EVENTS
160 select HAVE_PERF_REGS
161 select HAVE_PERF_USER_STACK_DUMP
162 select HAVE_REGS_AND_STACK_ACCESS_API
163 select HAVE_FUNCTION_ARG_ACCESS_API
164 select HAVE_RCU_TABLE_FREE
166 select HAVE_STACKPROTECTOR
167 select HAVE_SYSCALL_TRACEPOINTS
169 select HAVE_KRETPROBES
170 select HAVE_GENERIC_VDSO
171 select IOMMU_DMA if IOMMU_SUPPORT
173 select IRQ_FORCED_THREADING
174 select MODULES_USE_ELF_RELA
175 select NEED_DMA_MAP_STATE
176 select NEED_SG_DMA_LENGTH
178 select OF_EARLY_FLATTREE
179 select PCI_DOMAINS_GENERIC if PCI
180 select PCI_ECAM if (ACPI && PCI)
181 select PCI_SYSCALL if PCI
186 select SYSCTL_EXCEPTION_TRACE
187 select THREAD_INFO_IN_TASK
189 ARM 64-bit (AArch64) Linux support.
197 config ARM64_PAGE_SHIFT
199 default 16 if ARM64_64K_PAGES
200 default 14 if ARM64_16K_PAGES
203 config ARM64_CONT_SHIFT
205 default 5 if ARM64_64K_PAGES
206 default 7 if ARM64_16K_PAGES
209 config ARCH_MMAP_RND_BITS_MIN
210 default 14 if ARM64_64K_PAGES
211 default 16 if ARM64_16K_PAGES
214 # max bits determined by the following formula:
215 # VA_BITS - PAGE_SHIFT - 3
216 config ARCH_MMAP_RND_BITS_MAX
217 default 19 if ARM64_VA_BITS=36
218 default 24 if ARM64_VA_BITS=39
219 default 27 if ARM64_VA_BITS=42
220 default 30 if ARM64_VA_BITS=47
221 default 29 if ARM64_VA_BITS=48 && ARM64_64K_PAGES
222 default 31 if ARM64_VA_BITS=48 && ARM64_16K_PAGES
223 default 33 if ARM64_VA_BITS=48
224 default 14 if ARM64_64K_PAGES
225 default 16 if ARM64_16K_PAGES
228 config ARCH_MMAP_RND_COMPAT_BITS_MIN
229 default 7 if ARM64_64K_PAGES
230 default 9 if ARM64_16K_PAGES
233 config ARCH_MMAP_RND_COMPAT_BITS_MAX
239 config STACKTRACE_SUPPORT
242 config ILLEGAL_POINTER_VALUE
244 default 0xdead000000000000
246 config LOCKDEP_SUPPORT
249 config TRACE_IRQFLAGS_SUPPORT
256 config GENERIC_BUG_RELATIVE_POINTERS
258 depends on GENERIC_BUG
260 config GENERIC_HWEIGHT
266 config GENERIC_CALIBRATE_DELAY
270 bool "Support DMA zone" if EXPERT
274 bool "Support DMA32 zone" if EXPERT
277 config ARCH_ENABLE_MEMORY_HOTPLUG
283 config KERNEL_MODE_NEON
286 config FIX_EARLYCON_MEM
289 config PGTABLE_LEVELS
291 default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36
292 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42
293 default 3 if ARM64_64K_PAGES && (ARM64_VA_BITS_48 || ARM64_VA_BITS_52)
294 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39
295 default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47
296 default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48
298 config ARCH_SUPPORTS_UPROBES
301 config ARCH_PROC_KCORE_TEXT
304 config KASAN_SHADOW_OFFSET
307 default 0xdfffa00000000000 if (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) && !KASAN_SW_TAGS
308 default 0xdfffd00000000000 if ARM64_VA_BITS_47 && !KASAN_SW_TAGS
309 default 0xdffffe8000000000 if ARM64_VA_BITS_42 && !KASAN_SW_TAGS
310 default 0xdfffffd000000000 if ARM64_VA_BITS_39 && !KASAN_SW_TAGS
311 default 0xdffffffa00000000 if ARM64_VA_BITS_36 && !KASAN_SW_TAGS
312 default 0xefff900000000000 if (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) && KASAN_SW_TAGS
313 default 0xefffc80000000000 if ARM64_VA_BITS_47 && KASAN_SW_TAGS
314 default 0xeffffe4000000000 if ARM64_VA_BITS_42 && KASAN_SW_TAGS
315 default 0xefffffc800000000 if ARM64_VA_BITS_39 && KASAN_SW_TAGS
316 default 0xeffffff900000000 if ARM64_VA_BITS_36 && KASAN_SW_TAGS
317 default 0xffffffffffffffff
319 source "arch/arm64/Kconfig.platforms"
321 menu "Kernel Features"
323 menu "ARM errata workarounds via the alternatives framework"
325 config ARM64_WORKAROUND_CLEAN_CACHE
328 config ARM64_ERRATUM_826319
329 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"
331 select ARM64_WORKAROUND_CLEAN_CACHE
333 This option adds an alternative code sequence to work around ARM
334 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
335 AXI master interface and an L2 cache.
337 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
338 and is unable to accept a certain write via this interface, it will
339 not progress on read data presented on the read data channel and the
342 The workaround promotes data cache clean instructions to
343 data cache clean-and-invalidate.
344 Please note that this does not necessarily enable the workaround,
345 as it depends on the alternative framework, which will only patch
346 the kernel if an affected CPU is detected.
350 config ARM64_ERRATUM_827319
351 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
353 select ARM64_WORKAROUND_CLEAN_CACHE
355 This option adds an alternative code sequence to work around ARM
356 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
357 master interface and an L2 cache.
359 Under certain conditions this erratum can cause a clean line eviction
360 to occur at the same time as another transaction to the same address
361 on the AMBA 5 CHI interface, which can cause data corruption if the
362 interconnect reorders the two transactions.
364 The workaround promotes data cache clean instructions to
365 data cache clean-and-invalidate.
366 Please note that this does not necessarily enable the workaround,
367 as it depends on the alternative framework, which will only patch
368 the kernel if an affected CPU is detected.
372 config ARM64_ERRATUM_824069
373 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
375 select ARM64_WORKAROUND_CLEAN_CACHE
377 This option adds an alternative code sequence to work around ARM
378 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
379 to a coherent interconnect.
381 If a Cortex-A53 processor is executing a store or prefetch for
382 write instruction at the same time as a processor in another
383 cluster is executing a cache maintenance operation to the same
384 address, then this erratum might cause a clean cache line to be
385 incorrectly marked as dirty.
387 The workaround promotes data cache clean instructions to
388 data cache clean-and-invalidate.
389 Please note that this option does not necessarily enable the
390 workaround, as it depends on the alternative framework, which will
391 only patch the kernel if an affected CPU is detected.
395 config ARM64_ERRATUM_819472
396 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
398 select ARM64_WORKAROUND_CLEAN_CACHE
400 This option adds an alternative code sequence to work around ARM
401 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
402 present when it is connected to a coherent interconnect.
404 If the processor is executing a load and store exclusive sequence at
405 the same time as a processor in another cluster is executing a cache
406 maintenance operation to the same address, then this erratum might
407 cause data corruption.
409 The workaround promotes data cache clean instructions to
410 data cache clean-and-invalidate.
411 Please note that this does not necessarily enable the workaround,
412 as it depends on the alternative framework, which will only patch
413 the kernel if an affected CPU is detected.
417 config ARM64_ERRATUM_832075
418 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
421 This option adds an alternative code sequence to work around ARM
422 erratum 832075 on Cortex-A57 parts up to r1p2.
424 Affected Cortex-A57 parts might deadlock when exclusive load/store
425 instructions to Write-Back memory are mixed with Device loads.
427 The workaround is to promote device loads to use Load-Acquire
429 Please note that this does not necessarily enable the workaround,
430 as it depends on the alternative framework, which will only patch
431 the kernel if an affected CPU is detected.
435 config ARM64_ERRATUM_834220
436 bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault"
440 This option adds an alternative code sequence to work around ARM
441 erratum 834220 on Cortex-A57 parts up to r1p2.
443 Affected Cortex-A57 parts might report a Stage 2 translation
444 fault as the result of a Stage 1 fault for load crossing a
445 page boundary when there is a permission or device memory
446 alignment fault at Stage 1 and a translation fault at Stage 2.
448 The workaround is to verify that the Stage 1 translation
449 doesn't generate a fault before handling the Stage 2 fault.
450 Please note that this does not necessarily enable the workaround,
451 as it depends on the alternative framework, which will only patch
452 the kernel if an affected CPU is detected.
456 config ARM64_ERRATUM_845719
457 bool "Cortex-A53: 845719: a load might read incorrect data"
461 This option adds an alternative code sequence to work around ARM
462 erratum 845719 on Cortex-A53 parts up to r0p4.
464 When running a compat (AArch32) userspace on an affected Cortex-A53
465 part, a load at EL0 from a virtual address that matches the bottom 32
466 bits of the virtual address used by a recent load at (AArch64) EL1
467 might return incorrect data.
469 The workaround is to write the contextidr_el1 register on exception
470 return to a 32-bit task.
471 Please note that this does not necessarily enable the workaround,
472 as it depends on the alternative framework, which will only patch
473 the kernel if an affected CPU is detected.
477 config ARM64_ERRATUM_843419
478 bool "Cortex-A53: 843419: A load or store might access an incorrect address"
480 select ARM64_MODULE_PLTS if MODULES
482 This option links the kernel with '--fix-cortex-a53-843419' and
483 enables PLT support to replace certain ADRP instructions, which can
484 cause subsequent memory accesses to use an incorrect address on
485 Cortex-A53 parts up to r0p4.
489 config ARM64_ERRATUM_1024718
490 bool "Cortex-A55: 1024718: Update of DBM/AP bits without break before make might result in incorrect update"
493 This option adds a workaround for ARM Cortex-A55 Erratum 1024718.
495 Affected Cortex-A55 cores (r0p0, r0p1, r1p0) could cause incorrect
496 update of the hardware dirty bit when the DBM/AP bits are updated
497 without a break-before-make. The workaround is to disable the usage
498 of hardware DBM locally on the affected cores. CPUs not affected by
499 this erratum will continue to use the feature.
503 config ARM64_ERRATUM_1418040
504 bool "Cortex-A76/Neoverse-N1: MRC read following MRRC read of specific Generic Timer in AArch32 might give incorrect result"
508 This option adds a workaround for ARM Cortex-A76/Neoverse-N1
509 errata 1188873 and 1418040.
511 Affected Cortex-A76/Neoverse-N1 cores (r0p0 to r3p1) could
512 cause register corruption when accessing the timer registers
513 from AArch32 userspace.
517 config ARM64_WORKAROUND_SPECULATIVE_AT_VHE
520 config ARM64_ERRATUM_1165522
521 bool "Cortex-A76: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"
523 select ARM64_WORKAROUND_SPECULATIVE_AT_VHE
525 This option adds a workaround for ARM Cortex-A76 erratum 1165522.
527 Affected Cortex-A76 cores (r0p0, r1p0, r2p0) could end-up with
528 corrupted TLBs by speculating an AT instruction during a guest
533 config ARM64_ERRATUM_1286807
534 bool "Cortex-A76: Modification of the translation table for a virtual address might lead to read-after-read ordering violation"
536 select ARM64_WORKAROUND_REPEAT_TLBI
538 This option adds a workaround for ARM Cortex-A76 erratum 1286807.
540 On the affected Cortex-A76 cores (r0p0 to r3p0), if a virtual
541 address for a cacheable mapping of a location is being
542 accessed by a core while another core is remapping the virtual
543 address to a new physical page using the recommended
544 break-before-make sequence, then under very rare circumstances
545 TLBI+DSB completes before a read using the translation being
546 invalidated has been observed by other observers. The
547 workaround repeats the TLBI+DSB operation.
549 config ARM64_WORKAROUND_SPECULATIVE_AT_NVHE
552 config ARM64_ERRATUM_1319367
553 bool "Cortex-A57/A72: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"
555 select ARM64_WORKAROUND_SPECULATIVE_AT_NVHE
557 This option adds work arounds for ARM Cortex-A57 erratum 1319537
558 and A72 erratum 1319367
560 Cortex-A57 and A72 cores could end-up with corrupted TLBs by
561 speculating an AT instruction during a guest context switch.
565 config ARM64_ERRATUM_1463225
566 bool "Cortex-A76: Software Step might prevent interrupt recognition"
569 This option adds a workaround for Arm Cortex-A76 erratum 1463225.
571 On the affected Cortex-A76 cores (r0p0 to r3p1), software stepping
572 of a system call instruction (SVC) can prevent recognition of
573 subsequent interrupts when software stepping is disabled in the
574 exception handler of the system call and either kernel debugging
575 is enabled or VHE is in use.
577 Work around the erratum by triggering a dummy step exception
578 when handling a system call from a task that is being stepped
579 in a VHE configuration of the kernel.
583 config ARM64_ERRATUM_1542419
584 bool "Neoverse-N1: workaround mis-ordering of instruction fetches"
587 This option adds a workaround for ARM Neoverse-N1 erratum
590 Affected Neoverse-N1 cores could execute a stale instruction when
591 modified by another CPU. The workaround depends on a firmware
594 Workaround the issue by hiding the DIC feature from EL0. This
595 forces user-space to perform cache maintenance.
599 config CAVIUM_ERRATUM_22375
600 bool "Cavium erratum 22375, 24313"
603 Enable workaround for errata 22375 and 24313.
605 This implements two gicv3-its errata workarounds for ThunderX. Both
606 with a small impact affecting only ITS table allocation.
608 erratum 22375: only alloc 8MB table size
609 erratum 24313: ignore memory access type
611 The fixes are in ITS initialization and basically ignore memory access
612 type and table size provided by the TYPER and BASER registers.
616 config CAVIUM_ERRATUM_23144
617 bool "Cavium erratum 23144: ITS SYNC hang on dual socket system"
621 ITS SYNC command hang for cross node io and collections/cpu mapping.
625 config CAVIUM_ERRATUM_23154
626 bool "Cavium erratum 23154: Access to ICC_IAR1_EL1 is not sync'ed"
629 The gicv3 of ThunderX requires a modified version for
630 reading the IAR status to ensure data synchronization
631 (access to icc_iar1_el1 is not sync'ed before and after).
635 config CAVIUM_ERRATUM_27456
636 bool "Cavium erratum 27456: Broadcast TLBI instructions may cause icache corruption"
639 On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI
640 instructions may cause the icache to become corrupted if it
641 contains data for a non-current ASID. The fix is to
642 invalidate the icache when changing the mm context.
646 config CAVIUM_ERRATUM_30115
647 bool "Cavium erratum 30115: Guest may disable interrupts in host"
650 On ThunderX T88 pass 1.x through 2.2, T81 pass 1.0 through
651 1.2, and T83 Pass 1.0, KVM guest execution may disable
652 interrupts in host. Trapping both GICv3 group-0 and group-1
653 accesses sidesteps the issue.
657 config CAVIUM_TX2_ERRATUM_219
658 bool "Cavium ThunderX2 erratum 219: PRFM between TTBR change and ISB fails"
661 On Cavium ThunderX2, a load, store or prefetch instruction between a
662 TTBR update and the corresponding context synchronizing operation can
663 cause a spurious Data Abort to be delivered to any hardware thread in
666 Work around the issue by avoiding the problematic code sequence and
667 trapping KVM guest TTBRx_EL1 writes to EL2 when SMT is enabled. The
668 trap handler performs the corresponding register access, skips the
669 instruction and ensures context synchronization by virtue of the
674 config QCOM_FALKOR_ERRATUM_1003
675 bool "Falkor E1003: Incorrect translation due to ASID change"
678 On Falkor v1, an incorrect ASID may be cached in the TLB when ASID
679 and BADDR are changed together in TTBRx_EL1. Since we keep the ASID
680 in TTBR1_EL1, this situation only occurs in the entry trampoline and
681 then only for entries in the walk cache, since the leaf translation
682 is unchanged. Work around the erratum by invalidating the walk cache
683 entries for the trampoline before entering the kernel proper.
685 config ARM64_WORKAROUND_REPEAT_TLBI
688 config QCOM_FALKOR_ERRATUM_1009
689 bool "Falkor E1009: Prematurely complete a DSB after a TLBI"
691 select ARM64_WORKAROUND_REPEAT_TLBI
693 On Falkor v1, the CPU may prematurely complete a DSB following a
694 TLBI xxIS invalidate maintenance operation. Repeat the TLBI operation
695 one more time to fix the issue.
699 config QCOM_QDF2400_ERRATUM_0065
700 bool "QDF2400 E0065: Incorrect GITS_TYPER.ITT_Entry_size"
703 On Qualcomm Datacenter Technologies QDF2400 SoC, ITS hardware reports
704 ITE size incorrectly. The GITS_TYPER.ITT_Entry_size field should have
705 been indicated as 16Bytes (0xf), not 8Bytes (0x7).
709 config SOCIONEXT_SYNQUACER_PREITS
710 bool "Socionext Synquacer: Workaround for GICv3 pre-ITS"
713 Socionext Synquacer SoCs implement a separate h/w block to generate
714 MSI doorbell writes with non-zero values for the device ID.
718 config HISILICON_ERRATUM_161600802
719 bool "Hip07 161600802: Erroneous redistributor VLPI base"
722 The HiSilicon Hip07 SoC uses the wrong redistributor base
723 when issued ITS commands such as VMOVP and VMAPP, and requires
724 a 128kB offset to be applied to the target address in this commands.
728 config QCOM_FALKOR_ERRATUM_E1041
729 bool "Falkor E1041: Speculative instruction fetches might cause errant memory access"
732 Falkor CPU may speculatively fetch instructions from an improper
733 memory location when MMU translation is changed from SCTLR_ELn[M]=1
734 to SCTLR_ELn[M]=0. Prefix an ISB instruction to fix the problem.
738 config FUJITSU_ERRATUM_010001
739 bool "Fujitsu-A64FX erratum E#010001: Undefined fault may occur wrongly"
742 This option adds a workaround for Fujitsu-A64FX erratum E#010001.
743 On some variants of the Fujitsu-A64FX cores ver(1.0, 1.1), memory
744 accesses may cause undefined fault (Data abort, DFSC=0b111111).
745 This fault occurs under a specific hardware condition when a
746 load/store instruction performs an address translation using:
747 case-1 TTBR0_EL1 with TCR_EL1.NFD0 == 1.
748 case-2 TTBR0_EL2 with TCR_EL2.NFD0 == 1.
749 case-3 TTBR1_EL1 with TCR_EL1.NFD1 == 1.
750 case-4 TTBR1_EL2 with TCR_EL2.NFD1 == 1.
752 The workaround is to ensure these bits are clear in TCR_ELx.
753 The workaround only affects the Fujitsu-A64FX.
762 default ARM64_4K_PAGES
764 Page size (translation granule) configuration.
766 config ARM64_4K_PAGES
769 This feature enables 4KB pages support.
771 config ARM64_16K_PAGES
774 The system will use 16KB pages support. AArch32 emulation
775 requires applications compiled with 16K (or a multiple of 16K)
778 config ARM64_64K_PAGES
781 This feature enables 64KB pages support (4KB by default)
782 allowing only two levels of page tables and faster TLB
783 look-up. AArch32 emulation requires applications compiled
784 with 64K aligned segments.
789 prompt "Virtual address space size"
790 default ARM64_VA_BITS_39 if ARM64_4K_PAGES
791 default ARM64_VA_BITS_47 if ARM64_16K_PAGES
792 default ARM64_VA_BITS_42 if ARM64_64K_PAGES
794 Allows choosing one of multiple possible virtual address
795 space sizes. The level of translation table is determined by
796 a combination of page size and virtual address space size.
798 config ARM64_VA_BITS_36
799 bool "36-bit" if EXPERT
800 depends on ARM64_16K_PAGES
802 config ARM64_VA_BITS_39
804 depends on ARM64_4K_PAGES
806 config ARM64_VA_BITS_42
808 depends on ARM64_64K_PAGES
810 config ARM64_VA_BITS_47
812 depends on ARM64_16K_PAGES
814 config ARM64_VA_BITS_48
817 config ARM64_VA_BITS_52
819 depends on ARM64_64K_PAGES && (ARM64_PAN || !ARM64_SW_TTBR0_PAN)
821 Enable 52-bit virtual addressing for userspace when explicitly
822 requested via a hint to mmap(). The kernel will also use 52-bit
823 virtual addresses for its own mappings (provided HW support for
824 this feature is available, otherwise it reverts to 48-bit).
826 NOTE: Enabling 52-bit virtual addressing in conjunction with
827 ARMv8.3 Pointer Authentication will result in the PAC being
828 reduced from 7 bits to 3 bits, which may have a significant
829 impact on its susceptibility to brute-force attacks.
831 If unsure, select 48-bit virtual addressing instead.
835 config ARM64_FORCE_52BIT
836 bool "Force 52-bit virtual addresses for userspace"
837 depends on ARM64_VA_BITS_52 && EXPERT
839 For systems with 52-bit userspace VAs enabled, the kernel will attempt
840 to maintain compatibility with older software by providing 48-bit VAs
841 unless a hint is supplied to mmap.
843 This configuration option disables the 48-bit compatibility logic, and
844 forces all userspace addresses to be 52-bit on HW that supports it. One
845 should only enable this configuration option for stress testing userspace
846 memory management code. If unsure say N here.
850 default 36 if ARM64_VA_BITS_36
851 default 39 if ARM64_VA_BITS_39
852 default 42 if ARM64_VA_BITS_42
853 default 47 if ARM64_VA_BITS_47
854 default 48 if ARM64_VA_BITS_48
855 default 52 if ARM64_VA_BITS_52
858 prompt "Physical address space size"
859 default ARM64_PA_BITS_48
861 Choose the maximum physical address range that the kernel will
864 config ARM64_PA_BITS_48
867 config ARM64_PA_BITS_52
868 bool "52-bit (ARMv8.2)"
869 depends on ARM64_64K_PAGES
870 depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN
872 Enable support for a 52-bit physical address space, introduced as
873 part of the ARMv8.2-LPA extension.
875 With this enabled, the kernel will also continue to work on CPUs that
876 do not support ARMv8.2-LPA, but with some added memory overhead (and
877 minor performance overhead).
883 default 48 if ARM64_PA_BITS_48
884 default 52 if ARM64_PA_BITS_52
888 default CPU_LITTLE_ENDIAN
890 Select the endianness of data accesses performed by the CPU. Userspace
891 applications will need to be compiled and linked for the endianness
892 that is selected here.
894 config CPU_BIG_ENDIAN
895 bool "Build big-endian kernel"
897 Say Y if you plan on running a kernel with a big-endian userspace.
899 config CPU_LITTLE_ENDIAN
900 bool "Build little-endian kernel"
902 Say Y if you plan on running a kernel with a little-endian userspace.
903 This is usually the case for distributions targeting arm64.
908 bool "Multi-core scheduler support"
910 Multi-core scheduler support improves the CPU scheduler's decision
911 making when dealing with multi-core CPU chips at a cost of slightly
912 increased overhead in some places. If unsure say N here.
915 bool "SMT scheduler support"
917 Improves the CPU scheduler's decision making when dealing with
918 MultiThreading at a cost of slightly increased overhead in some
919 places. If unsure say N here.
922 int "Maximum number of CPUs (2-4096)"
927 bool "Support for hot-pluggable CPUs"
928 select GENERIC_IRQ_MIGRATION
930 Say Y here to experiment with turning CPUs off and on. CPUs
931 can be controlled through /sys/devices/system/cpu.
933 # Common NUMA Features
935 bool "Numa Memory Allocation and Scheduler Support"
936 select ACPI_NUMA if ACPI
939 Enable NUMA (Non Uniform Memory Access) support.
941 The kernel will try to allocate memory used by a CPU on the
942 local memory of the CPU and add some more
943 NUMA awareness to the kernel.
946 int "Maximum NUMA Nodes (as a power of 2)"
949 depends on NEED_MULTIPLE_NODES
951 Specify the maximum number of NUMA Nodes available on the target
952 system. Increases memory reserved to accommodate various tables.
954 config USE_PERCPU_NUMA_NODE_ID
958 config HAVE_SETUP_PER_CPU_AREA
962 config NEED_PER_CPU_EMBED_FIRST_CHUNK
969 source "kernel/Kconfig.hz"
971 config ARCH_SUPPORTS_DEBUG_PAGEALLOC
974 config ARCH_SPARSEMEM_ENABLE
976 select SPARSEMEM_VMEMMAP_ENABLE
978 config ARCH_SPARSEMEM_DEFAULT
979 def_bool ARCH_SPARSEMEM_ENABLE
981 config ARCH_SELECT_MEMORY_MODEL
982 def_bool ARCH_SPARSEMEM_ENABLE
984 config ARCH_FLATMEM_ENABLE
987 config HAVE_ARCH_PFN_VALID
990 config HW_PERF_EVENTS
994 config SYS_SUPPORTS_HUGETLBFS
997 config ARCH_WANT_HUGE_PMD_SHARE
999 config ARCH_HAS_CACHE_LINE_SIZE
1002 config ARCH_ENABLE_SPLIT_PMD_PTLOCK
1003 def_bool y if PGTABLE_LEVELS > 2
1006 bool "Enable seccomp to safely compute untrusted bytecode"
1008 This kernel feature is useful for number crunching applications
1009 that may need to compute untrusted bytecode during their
1010 execution. By using pipes or other transports made available to
1011 the process as file descriptors supporting the read/write
1012 syscalls, it's possible to isolate those applications in
1013 their own address space using seccomp. Once seccomp is
1014 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1015 and the task is only allowed to execute a few safe syscalls
1016 defined by each seccomp mode.
1019 bool "Enable paravirtualization code"
1021 This changes the kernel so it can modify itself when it is run
1022 under a hypervisor, potentially improving performance significantly
1023 over full virtualization.
1025 config PARAVIRT_TIME_ACCOUNTING
1026 bool "Paravirtual steal time accounting"
1029 Select this option to enable fine granularity task steal time
1030 accounting. Time spent executing other tasks in parallel with
1031 the current vCPU is discounted from the vCPU power. To account for
1032 that, there can be a small performance impact.
1034 If in doubt, say N here.
1037 depends on PM_SLEEP_SMP
1039 bool "kexec system call"
1041 kexec is a system call that implements the ability to shutdown your
1042 current kernel, and to start another kernel. It is like a reboot
1043 but it is independent of the system firmware. And like a reboot
1044 you can start any kernel with it, not just Linux.
1047 bool "kexec file based system call"
1050 This is new version of kexec system call. This system call is
1051 file based and takes file descriptors as system call argument
1052 for kernel and initramfs as opposed to list of segments as
1053 accepted by previous system call.
1056 bool "Verify kernel signature during kexec_file_load() syscall"
1057 depends on KEXEC_FILE
1059 Select this option to verify a signature with loaded kernel
1060 image. If configured, any attempt of loading a image without
1061 valid signature will fail.
1063 In addition to that option, you need to enable signature
1064 verification for the corresponding kernel image type being
1065 loaded in order for this to work.
1067 config KEXEC_IMAGE_VERIFY_SIG
1068 bool "Enable Image signature verification support"
1070 depends on KEXEC_SIG
1071 depends on EFI && SIGNED_PE_FILE_VERIFICATION
1073 Enable Image signature verification support.
1075 comment "Support for PE file signature verification disabled"
1076 depends on KEXEC_SIG
1077 depends on !EFI || !SIGNED_PE_FILE_VERIFICATION
1080 bool "Build kdump crash kernel"
1082 Generate crash dump after being started by kexec. This should
1083 be normally only set in special crash dump kernels which are
1084 loaded in the main kernel with kexec-tools into a specially
1085 reserved region and then later executed after a crash by
1088 For more details see Documentation/admin-guide/kdump/kdump.rst
1095 bool "Xen guest support on ARM64"
1096 depends on ARM64 && OF
1100 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64.
1102 config FORCE_MAX_ZONEORDER
1104 default "14" if (ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE)
1105 default "12" if (ARM64_16K_PAGES && TRANSPARENT_HUGEPAGE)
1108 The kernel memory allocator divides physically contiguous memory
1109 blocks into "zones", where each zone is a power of two number of
1110 pages. This option selects the largest power of two that the kernel
1111 keeps in the memory allocator. If you need to allocate very large
1112 blocks of physically contiguous memory, then you may need to
1113 increase this value.
1115 This config option is actually maximum order plus one. For example,
1116 a value of 11 means that the largest free memory block is 2^10 pages.
1118 We make sure that we can allocate upto a HugePage size for each configuration.
1120 MAX_ORDER = (PMD_SHIFT - PAGE_SHIFT) + 1 => PAGE_SHIFT - 2
1122 However for 4K, we choose a higher default value, 11 as opposed to 10, giving us
1123 4M allocations matching the default size used by generic code.
1125 config UNMAP_KERNEL_AT_EL0
1126 bool "Unmap kernel when running in userspace (aka \"KAISER\")" if EXPERT
1129 Speculation attacks against some high-performance processors can
1130 be used to bypass MMU permission checks and leak kernel data to
1131 userspace. This can be defended against by unmapping the kernel
1132 when running in userspace, mapping it back in on exception entry
1133 via a trampoline page in the vector table.
1137 config HARDEN_BRANCH_PREDICTOR
1138 bool "Harden the branch predictor against aliasing attacks" if EXPERT
1141 Speculation attacks against some high-performance processors rely on
1142 being able to manipulate the branch predictor for a victim context by
1143 executing aliasing branches in the attacker context. Such attacks
1144 can be partially mitigated against by clearing internal branch
1145 predictor state and limiting the prediction logic in some situations.
1147 This config option will take CPU-specific actions to harden the
1148 branch predictor against aliasing attacks and may rely on specific
1149 instruction sequences or control bits being set by the system
1154 config HARDEN_EL2_VECTORS
1155 bool "Harden EL2 vector mapping against system register leak" if EXPERT
1158 Speculation attacks against some high-performance processors can
1159 be used to leak privileged information such as the vector base
1160 register, resulting in a potential defeat of the EL2 layout
1163 This config option will map the vectors to a fixed location,
1164 independent of the EL2 code mapping, so that revealing VBAR_EL2
1165 to an attacker does not give away any extra information. This
1166 only gets enabled on affected CPUs.
1171 bool "Speculative Store Bypass Disable" if EXPERT
1174 This enables mitigation of the bypassing of previous stores
1175 by speculative loads.
1179 config RODATA_FULL_DEFAULT_ENABLED
1180 bool "Apply r/o permissions of VM areas also to their linear aliases"
1183 Apply read-only attributes of VM areas to the linear alias of
1184 the backing pages as well. This prevents code or read-only data
1185 from being modified (inadvertently or intentionally) via another
1186 mapping of the same memory page. This additional enhancement can
1187 be turned off at runtime by passing rodata=[off|on] (and turned on
1188 with rodata=full if this option is set to 'n')
1190 This requires the linear region to be mapped down to pages,
1191 which may adversely affect performance in some cases.
1193 config ARM64_SW_TTBR0_PAN
1194 bool "Emulate Privileged Access Never using TTBR0_EL1 switching"
1196 Enabling this option prevents the kernel from accessing
1197 user-space memory directly by pointing TTBR0_EL1 to a reserved
1198 zeroed area and reserved ASID. The user access routines
1199 restore the valid TTBR0_EL1 temporarily.
1201 config ARM64_TAGGED_ADDR_ABI
1202 bool "Enable the tagged user addresses syscall ABI"
1205 When this option is enabled, user applications can opt in to a
1206 relaxed ABI via prctl() allowing tagged addresses to be passed
1207 to system calls as pointer arguments. For details, see
1208 Documentation/arm64/tagged-address-abi.rst.
1211 bool "Kernel support for 32-bit EL0"
1212 depends on ARM64_4K_PAGES || EXPERT
1213 select COMPAT_BINFMT_ELF if BINFMT_ELF
1215 select OLD_SIGSUSPEND3
1216 select COMPAT_OLD_SIGACTION
1218 This option enables support for a 32-bit EL0 running under a 64-bit
1219 kernel at EL1. AArch32-specific components such as system calls,
1220 the user helper functions, VFP support and the ptrace interface are
1221 handled appropriately by the kernel.
1223 If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware
1224 that you will only be able to execute AArch32 binaries that were compiled
1225 with page size aligned segments.
1227 If you want to execute 32-bit userspace applications, say Y.
1231 config KUSER_HELPERS
1232 bool "Enable kuser helpers page for 32-bit applications"
1235 Warning: disabling this option may break 32-bit user programs.
1237 Provide kuser helpers to compat tasks. The kernel provides
1238 helper code to userspace in read only form at a fixed location
1239 to allow userspace to be independent of the CPU type fitted to
1240 the system. This permits binaries to be run on ARMv4 through
1241 to ARMv8 without modification.
1243 See Documentation/arm/kernel_user_helpers.rst for details.
1245 However, the fixed address nature of these helpers can be used
1246 by ROP (return orientated programming) authors when creating
1249 If all of the binaries and libraries which run on your platform
1250 are built specifically for your platform, and make no use of
1251 these helpers, then you can turn this option off to hinder
1252 such exploits. However, in that case, if a binary or library
1253 relying on those helpers is run, it will not function correctly.
1255 Say N here only if you are absolutely certain that you do not
1256 need these helpers; otherwise, the safe option is to say Y.
1259 bool "Enable vDSO for 32-bit applications"
1260 depends on !CPU_BIG_ENDIAN && "$(CROSS_COMPILE_COMPAT)" != ""
1261 select GENERIC_COMPAT_VDSO
1264 Place in the process address space of 32-bit applications an
1265 ELF shared object providing fast implementations of gettimeofday
1268 You must have a 32-bit build of glibc 2.22 or later for programs
1269 to seamlessly take advantage of this.
1271 menuconfig ARMV8_DEPRECATED
1272 bool "Emulate deprecated/obsolete ARMv8 instructions"
1275 Legacy software support may require certain instructions
1276 that have been deprecated or obsoleted in the architecture.
1278 Enable this config to enable selective emulation of these
1285 config SWP_EMULATION
1286 bool "Emulate SWP/SWPB instructions"
1288 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that
1289 they are always undefined. Say Y here to enable software
1290 emulation of these instructions for userspace using LDXR/STXR.
1292 In some older versions of glibc [<=2.8] SWP is used during futex
1293 trylock() operations with the assumption that the code will not
1294 be preempted. This invalid assumption may be more likely to fail
1295 with SWP emulation enabled, leading to deadlock of the user
1298 NOTE: when accessing uncached shared regions, LDXR/STXR rely
1299 on an external transaction monitoring block called a global
1300 monitor to maintain update atomicity. If your system does not
1301 implement a global monitor, this option can cause programs that
1302 perform SWP operations to uncached memory to deadlock.
1306 config CP15_BARRIER_EMULATION
1307 bool "Emulate CP15 Barrier instructions"
1309 The CP15 barrier instructions - CP15ISB, CP15DSB, and
1310 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
1311 strongly recommended to use the ISB, DSB, and DMB
1312 instructions instead.
1314 Say Y here to enable software emulation of these
1315 instructions for AArch32 userspace code. When this option is
1316 enabled, CP15 barrier usage is traced which can help
1317 identify software that needs updating.
1321 config SETEND_EMULATION
1322 bool "Emulate SETEND instruction"
1324 The SETEND instruction alters the data-endianness of the
1325 AArch32 EL0, and is deprecated in ARMv8.
1327 Say Y here to enable software emulation of the instruction
1328 for AArch32 userspace code.
1330 Note: All the cpus on the system must have mixed endian support at EL0
1331 for this feature to be enabled. If a new CPU - which doesn't support mixed
1332 endian - is hotplugged in after this feature has been enabled, there could
1333 be unexpected results in the applications.
1340 menu "ARMv8.1 architectural features"
1342 config ARM64_HW_AFDBM
1343 bool "Support for hardware updates of the Access and Dirty page flags"
1346 The ARMv8.1 architecture extensions introduce support for
1347 hardware updates of the access and dirty information in page
1348 table entries. When enabled in TCR_EL1 (HA and HD bits) on
1349 capable processors, accesses to pages with PTE_AF cleared will
1350 set this bit instead of raising an access flag fault.
1351 Similarly, writes to read-only pages with the DBM bit set will
1352 clear the read-only bit (AP[2]) instead of raising a
1355 Kernels built with this configuration option enabled continue
1356 to work on pre-ARMv8.1 hardware and the performance impact is
1357 minimal. If unsure, say Y.
1360 bool "Enable support for Privileged Access Never (PAN)"
1363 Privileged Access Never (PAN; part of the ARMv8.1 Extensions)
1364 prevents the kernel or hypervisor from accessing user-space (EL0)
1367 Choosing this option will cause any unprotected (not using
1368 copy_to_user et al) memory access to fail with a permission fault.
1370 The feature is detected at runtime, and will remain as a 'nop'
1371 instruction if the cpu does not implement the feature.
1373 config ARM64_LSE_ATOMICS
1374 bool "Atomic instructions"
1375 depends on JUMP_LABEL
1378 As part of the Large System Extensions, ARMv8.1 introduces new
1379 atomic instructions that are designed specifically to scale in
1382 Say Y here to make use of these instructions for the in-kernel
1383 atomic routines. This incurs a small overhead on CPUs that do
1384 not support these instructions and requires the kernel to be
1385 built with binutils >= 2.25 in order for the new instructions
1389 bool "Enable support for Virtualization Host Extensions (VHE)"
1392 Virtualization Host Extensions (VHE) allow the kernel to run
1393 directly at EL2 (instead of EL1) on processors that support
1394 it. This leads to better performance for KVM, as they reduce
1395 the cost of the world switch.
1397 Selecting this option allows the VHE feature to be detected
1398 at runtime, and does not affect processors that do not
1399 implement this feature.
1403 menu "ARMv8.2 architectural features"
1406 bool "Enable support for User Access Override (UAO)"
1409 User Access Override (UAO; part of the ARMv8.2 Extensions)
1410 causes the 'unprivileged' variant of the load/store instructions to
1411 be overridden to be privileged.
1413 This option changes get_user() and friends to use the 'unprivileged'
1414 variant of the load/store instructions. This ensures that user-space
1415 really did have access to the supplied memory. When addr_limit is
1416 set to kernel memory the UAO bit will be set, allowing privileged
1417 access to kernel memory.
1419 Choosing this option will cause copy_to_user() et al to use user-space
1422 The feature is detected at runtime, the kernel will use the
1423 regular load/store instructions if the cpu does not implement the
1427 bool "Enable support for persistent memory"
1428 select ARCH_HAS_PMEM_API
1429 select ARCH_HAS_UACCESS_FLUSHCACHE
1431 Say Y to enable support for the persistent memory API based on the
1432 ARMv8.2 DCPoP feature.
1434 The feature is detected at runtime, and the kernel will use DC CVAC
1435 operations if DC CVAP is not supported (following the behaviour of
1436 DC CVAP itself if the system does not define a point of persistence).
1438 config ARM64_RAS_EXTN
1439 bool "Enable support for RAS CPU Extensions"
1442 CPUs that support the Reliability, Availability and Serviceability
1443 (RAS) Extensions, part of ARMv8.2 are able to track faults and
1444 errors, classify them and report them to software.
1446 On CPUs with these extensions system software can use additional
1447 barriers to determine if faults are pending and read the
1448 classification from a new set of registers.
1450 Selecting this feature will allow the kernel to use these barriers
1451 and access the new registers if the system supports the extension.
1452 Platform RAS features may additionally depend on firmware support.
1455 bool "Enable support for Common Not Private (CNP) translations"
1457 depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN
1459 Common Not Private (CNP) allows translation table entries to
1460 be shared between different PEs in the same inner shareable
1461 domain, so the hardware can use this fact to optimise the
1462 caching of such entries in the TLB.
1464 Selecting this option allows the CNP feature to be detected
1465 at runtime, and does not affect PEs that do not implement
1470 menu "ARMv8.3 architectural features"
1472 config ARM64_PTR_AUTH
1473 bool "Enable support for pointer authentication"
1475 depends on !KVM || ARM64_VHE
1477 Pointer authentication (part of the ARMv8.3 Extensions) provides
1478 instructions for signing and authenticating pointers against secret
1479 keys, which can be used to mitigate Return Oriented Programming (ROP)
1482 This option enables these instructions at EL0 (i.e. for userspace).
1484 Choosing this option will cause the kernel to initialise secret keys
1485 for each process at exec() time, with these keys being
1486 context-switched along with the process.
1488 The feature is detected at runtime. If the feature is not present in
1489 hardware it will not be advertised to userspace/KVM guest nor will it
1490 be enabled. However, KVM guest also require VHE mode and hence
1491 CONFIG_ARM64_VHE=y option to use this feature.
1496 bool "ARM Scalable Vector Extension support"
1498 depends on !KVM || ARM64_VHE
1500 The Scalable Vector Extension (SVE) is an extension to the AArch64
1501 execution state which complements and extends the SIMD functionality
1502 of the base architecture to support much larger vectors and to enable
1503 additional vectorisation opportunities.
1505 To enable use of this extension on CPUs that implement it, say Y.
1507 On CPUs that support the SVE2 extensions, this option will enable
1510 Note that for architectural reasons, firmware _must_ implement SVE
1511 support when running on SVE capable hardware. The required support
1514 * version 1.5 and later of the ARM Trusted Firmware
1515 * the AArch64 boot wrapper since commit 5e1261e08abf
1516 ("bootwrapper: SVE: Enable SVE for EL2 and below").
1518 For other firmware implementations, consult the firmware documentation
1521 If you need the kernel to boot on SVE-capable hardware with broken
1522 firmware, you may need to say N here until you get your firmware
1523 fixed. Otherwise, you may experience firmware panics or lockups when
1524 booting the kernel. If unsure and you are not observing these
1525 symptoms, you should assume that it is safe to say Y.
1527 CPUs that support SVE are architecturally required to support the
1528 Virtualization Host Extensions (VHE), so the kernel makes no
1529 provision for supporting SVE alongside KVM without VHE enabled.
1530 Thus, you will need to enable CONFIG_ARM64_VHE if you want to support
1531 KVM in the same kernel image.
1533 config ARM64_MODULE_PLTS
1534 bool "Use PLTs to allow module memory to spill over into vmalloc area"
1536 select HAVE_MOD_ARCH_SPECIFIC
1538 Allocate PLTs when loading modules so that jumps and calls whose
1539 targets are too far away for their relative offsets to be encoded
1540 in the instructions themselves can be bounced via veneers in the
1541 module's PLT. This allows modules to be allocated in the generic
1542 vmalloc area after the dedicated module memory area has been
1545 When running with address space randomization (KASLR), the module
1546 region itself may be too far away for ordinary relative jumps and
1547 calls, and so in that case, module PLTs are required and cannot be
1550 Specific errata workaround(s) might also force module PLTs to be
1551 enabled (ARM64_ERRATUM_843419).
1553 config ARM64_PSEUDO_NMI
1554 bool "Support for NMI-like interrupts"
1555 select CONFIG_ARM_GIC_V3
1557 Adds support for mimicking Non-Maskable Interrupts through the use of
1558 GIC interrupt priority. This support requires version 3 or later of
1561 This high priority configuration for interrupts needs to be
1562 explicitly enabled by setting the kernel parameter
1563 "irqchip.gicv3_pseudo_nmi" to 1.
1568 config ARM64_DEBUG_PRIORITY_MASKING
1569 bool "Debug interrupt priority masking"
1571 This adds runtime checks to functions enabling/disabling
1572 interrupts when using priority masking. The additional checks verify
1573 the validity of ICC_PMR_EL1 when calling concerned functions.
1580 select ARCH_HAS_RELR
1582 This builds the kernel as a Position Independent Executable (PIE),
1583 which retains all relocation metadata required to relocate the
1584 kernel binary at runtime to a different virtual address than the
1585 address it was linked at.
1586 Since AArch64 uses the RELA relocation format, this requires a
1587 relocation pass at runtime even if the kernel is loaded at the
1588 same address it was linked at.
1590 config RANDOMIZE_BASE
1591 bool "Randomize the address of the kernel image"
1592 select ARM64_MODULE_PLTS if MODULES
1595 Randomizes the virtual address at which the kernel image is
1596 loaded, as a security feature that deters exploit attempts
1597 relying on knowledge of the location of kernel internals.
1599 It is the bootloader's job to provide entropy, by passing a
1600 random u64 value in /chosen/kaslr-seed at kernel entry.
1602 When booting via the UEFI stub, it will invoke the firmware's
1603 EFI_RNG_PROTOCOL implementation (if available) to supply entropy
1604 to the kernel proper. In addition, it will randomise the physical
1605 location of the kernel Image as well.
1609 config RANDOMIZE_MODULE_REGION_FULL
1610 bool "Randomize the module region over a 4 GB range"
1611 depends on RANDOMIZE_BASE
1614 Randomizes the location of the module region inside a 4 GB window
1615 covering the core kernel. This way, it is less likely for modules
1616 to leak information about the location of core kernel data structures
1617 but it does imply that function calls between modules and the core
1618 kernel will need to be resolved via veneers in the module PLT.
1620 When this option is not set, the module region will be randomized over
1621 a limited range that contains the [_stext, _etext] interval of the
1622 core kernel, so branch relocations are always in range.
1624 config CC_HAVE_STACKPROTECTOR_SYSREG
1625 def_bool $(cc-option,-mstack-protector-guard=sysreg -mstack-protector-guard-reg=sp_el0 -mstack-protector-guard-offset=0)
1627 config STACKPROTECTOR_PER_TASK
1629 depends on STACKPROTECTOR && CC_HAVE_STACKPROTECTOR_SYSREG
1635 config ARM64_ACPI_PARKING_PROTOCOL
1636 bool "Enable support for the ARM64 ACPI parking protocol"
1639 Enable support for the ARM64 ACPI parking protocol. If disabled
1640 the kernel will not allow booting through the ARM64 ACPI parking
1641 protocol even if the corresponding data is present in the ACPI
1645 string "Default kernel command string"
1648 Provide a set of default command-line options at build time by
1649 entering them here. As a minimum, you should specify the the
1650 root device (e.g. root=/dev/nfs).
1652 config CMDLINE_FORCE
1653 bool "Always use the default kernel command string"
1654 depends on CMDLINE != ""
1656 Always use the default kernel command string, even if the boot
1657 loader passes other arguments to the kernel.
1658 This is useful if you cannot or don't want to change the
1659 command-line options your boot loader passes to the kernel.
1665 bool "UEFI runtime support"
1666 depends on OF && !CPU_BIG_ENDIAN
1667 depends on KERNEL_MODE_NEON
1668 select ARCH_SUPPORTS_ACPI
1671 select EFI_PARAMS_FROM_FDT
1672 select EFI_RUNTIME_WRAPPERS
1677 This option provides support for runtime services provided
1678 by UEFI firmware (such as non-volatile variables, realtime
1679 clock, and platform reset). A UEFI stub is also provided to
1680 allow the kernel to be booted as an EFI application. This
1681 is only useful on systems that have UEFI firmware.
1684 bool "Enable support for SMBIOS (DMI) tables"
1688 This enables SMBIOS/DMI feature for systems.
1690 This option is only useful on systems that have UEFI firmware.
1691 However, even with this option, the resultant kernel should
1692 continue to boot on existing non-UEFI platforms.
1696 config SYSVIPC_COMPAT
1698 depends on COMPAT && SYSVIPC
1700 config ARCH_ENABLE_HUGEPAGE_MIGRATION
1702 depends on HUGETLB_PAGE && MIGRATION
1704 menu "Power management options"
1706 source "kernel/power/Kconfig"
1708 config ARCH_HIBERNATION_POSSIBLE
1712 config ARCH_HIBERNATION_HEADER
1714 depends on HIBERNATION
1716 config ARCH_SUSPEND_POSSIBLE
1721 menu "CPU Power Management"
1723 source "drivers/cpuidle/Kconfig"
1725 source "drivers/cpufreq/Kconfig"
1729 source "drivers/firmware/Kconfig"
1731 source "drivers/acpi/Kconfig"
1733 source "arch/arm64/kvm/Kconfig"
1736 source "arch/arm64/crypto/Kconfig"