1 # SPDX-License-Identifier: GPL-2.0-only
4 select ACPI_CCA_REQUIRED if ACPI
5 select ACPI_GENERIC_GSI if ACPI
6 select ACPI_GTDT if ACPI
7 select ACPI_IORT if ACPI
8 select ACPI_REDUCED_HARDWARE_ONLY if ACPI
9 select ACPI_MCFG if (ACPI && PCI)
10 select ACPI_SPCR_TABLE if ACPI
11 select ACPI_PPTT if ACPI
12 select ARCH_HAS_DEBUG_WX
13 select ARCH_BINFMT_ELF_STATE
14 select ARCH_ENABLE_MEMORY_HOTPLUG
15 select ARCH_ENABLE_MEMORY_HOTREMOVE
16 select ARCH_HAS_CACHE_LINE_SIZE
17 select ARCH_HAS_DEBUG_VIRTUAL
18 select ARCH_HAS_DEBUG_VM_PGTABLE
19 select ARCH_HAS_DMA_PREP_COHERENT
20 select ARCH_HAS_ACPI_TABLE_UPGRADE if ACPI
21 select ARCH_HAS_FAST_MULTIPLIER
22 select ARCH_HAS_FORTIFY_SOURCE
23 select ARCH_HAS_GCOV_PROFILE_ALL
24 select ARCH_HAS_GIGANTIC_PAGE
26 select ARCH_HAS_KEEPINITRD
27 select ARCH_HAS_MEMBARRIER_SYNC_CORE
28 select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE
29 select ARCH_HAS_PTE_DEVMAP
30 select ARCH_HAS_PTE_SPECIAL
31 select ARCH_HAS_SETUP_DMA_OPS
32 select ARCH_HAS_SET_DIRECT_MAP
33 select ARCH_HAS_SET_MEMORY
35 select ARCH_HAS_STRICT_KERNEL_RWX
36 select ARCH_HAS_STRICT_MODULE_RWX
37 select ARCH_HAS_SYNC_DMA_FOR_DEVICE
38 select ARCH_HAS_SYNC_DMA_FOR_CPU
39 select ARCH_HAS_SYSCALL_WRAPPER
40 select ARCH_HAS_TEARDOWN_DMA_OPS if IOMMU_SUPPORT
41 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
42 select ARCH_HAVE_ELF_PROT
43 select ARCH_HAVE_NMI_SAFE_CMPXCHG
44 select ARCH_INLINE_READ_LOCK if !PREEMPTION
45 select ARCH_INLINE_READ_LOCK_BH if !PREEMPTION
46 select ARCH_INLINE_READ_LOCK_IRQ if !PREEMPTION
47 select ARCH_INLINE_READ_LOCK_IRQSAVE if !PREEMPTION
48 select ARCH_INLINE_READ_UNLOCK if !PREEMPTION
49 select ARCH_INLINE_READ_UNLOCK_BH if !PREEMPTION
50 select ARCH_INLINE_READ_UNLOCK_IRQ if !PREEMPTION
51 select ARCH_INLINE_READ_UNLOCK_IRQRESTORE if !PREEMPTION
52 select ARCH_INLINE_WRITE_LOCK if !PREEMPTION
53 select ARCH_INLINE_WRITE_LOCK_BH if !PREEMPTION
54 select ARCH_INLINE_WRITE_LOCK_IRQ if !PREEMPTION
55 select ARCH_INLINE_WRITE_LOCK_IRQSAVE if !PREEMPTION
56 select ARCH_INLINE_WRITE_UNLOCK if !PREEMPTION
57 select ARCH_INLINE_WRITE_UNLOCK_BH if !PREEMPTION
58 select ARCH_INLINE_WRITE_UNLOCK_IRQ if !PREEMPTION
59 select ARCH_INLINE_WRITE_UNLOCK_IRQRESTORE if !PREEMPTION
60 select ARCH_INLINE_SPIN_TRYLOCK if !PREEMPTION
61 select ARCH_INLINE_SPIN_TRYLOCK_BH if !PREEMPTION
62 select ARCH_INLINE_SPIN_LOCK if !PREEMPTION
63 select ARCH_INLINE_SPIN_LOCK_BH if !PREEMPTION
64 select ARCH_INLINE_SPIN_LOCK_IRQ if !PREEMPTION
65 select ARCH_INLINE_SPIN_LOCK_IRQSAVE if !PREEMPTION
66 select ARCH_INLINE_SPIN_UNLOCK if !PREEMPTION
67 select ARCH_INLINE_SPIN_UNLOCK_BH if !PREEMPTION
68 select ARCH_INLINE_SPIN_UNLOCK_IRQ if !PREEMPTION
69 select ARCH_INLINE_SPIN_UNLOCK_IRQRESTORE if !PREEMPTION
70 select ARCH_KEEP_MEMBLOCK
71 select ARCH_USE_CMPXCHG_LOCKREF
72 select ARCH_USE_GNU_PROPERTY
73 select ARCH_USE_MEMTEST
74 select ARCH_USE_QUEUED_RWLOCKS
75 select ARCH_USE_QUEUED_SPINLOCKS
76 select ARCH_USE_SYM_ANNOTATIONS
77 select ARCH_SUPPORTS_DEBUG_PAGEALLOC
78 select ARCH_SUPPORTS_HUGETLBFS
79 select ARCH_SUPPORTS_MEMORY_FAILURE
80 select ARCH_SUPPORTS_SHADOW_CALL_STACK if CC_HAVE_SHADOW_CALL_STACK
81 select ARCH_SUPPORTS_LTO_CLANG if CPU_LITTLE_ENDIAN
82 select ARCH_SUPPORTS_LTO_CLANG_THIN
83 select ARCH_SUPPORTS_CFI_CLANG
84 select ARCH_SUPPORTS_ATOMIC_RMW
85 select ARCH_SUPPORTS_INT128 if CC_HAS_INT128 && (GCC_VERSION >= 50000 || CC_IS_CLANG)
86 select ARCH_SUPPORTS_NUMA_BALANCING
87 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION if COMPAT
88 select ARCH_WANT_DEFAULT_BPF_JIT
89 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT
90 select ARCH_WANT_FRAME_POINTERS
91 select ARCH_WANT_HUGE_PMD_SHARE if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36)
92 select ARCH_WANT_LD_ORPHAN_WARN
93 select ARCH_HAS_UBSAN_SANITIZE_ALL
97 select AUDIT_ARCH_COMPAT_GENERIC
98 select ARM_GIC_V2M if PCI
100 select ARM_GIC_V3_ITS if PCI
102 select BUILDTIME_TABLE_SORT
103 select CLONE_BACKWARDS
105 select CPU_PM if (SUSPEND || CPU_IDLE)
107 select DCACHE_WORD_ACCESS
108 select DMA_DIRECT_REMAP
111 select GENERIC_ALLOCATOR
112 select GENERIC_ARCH_TOPOLOGY
113 select GENERIC_CLOCKEVENTS_BROADCAST
114 select GENERIC_CPU_AUTOPROBE
115 select GENERIC_CPU_VULNERABILITIES
116 select GENERIC_EARLY_IOREMAP
117 select GENERIC_FIND_FIRST_BIT
118 select GENERIC_IDLE_POLL_SETUP
119 select GENERIC_IRQ_IPI
120 select GENERIC_IRQ_PROBE
121 select GENERIC_IRQ_SHOW
122 select GENERIC_IRQ_SHOW_LEVEL
123 select GENERIC_LIB_DEVMEM_IS_ALLOWED
124 select GENERIC_PCI_IOMAP
125 select GENERIC_PTDUMP
126 select GENERIC_SCHED_CLOCK
127 select GENERIC_SMP_IDLE_THREAD
128 select GENERIC_STRNCPY_FROM_USER
129 select GENERIC_STRNLEN_USER
130 select GENERIC_TIME_VSYSCALL
131 select GENERIC_GETTIMEOFDAY
132 select GENERIC_VDSO_TIME_NS
133 select HANDLE_DOMAIN_IRQ
134 select HARDIRQS_SW_RESEND
138 select HAVE_ACPI_APEI if (ACPI && EFI)
139 select HAVE_ALIGNED_STRUCT_PAGE if SLUB
140 select HAVE_ARCH_AUDITSYSCALL
141 select HAVE_ARCH_BITREVERSE
142 select HAVE_ARCH_COMPILER_H
143 select HAVE_ARCH_HUGE_VMAP
144 select HAVE_ARCH_JUMP_LABEL
145 select HAVE_ARCH_JUMP_LABEL_RELATIVE
146 select HAVE_ARCH_KASAN if !(ARM64_16K_PAGES && ARM64_VA_BITS_48)
147 select HAVE_ARCH_KASAN_VMALLOC if HAVE_ARCH_KASAN
148 select HAVE_ARCH_KASAN_SW_TAGS if HAVE_ARCH_KASAN
149 select HAVE_ARCH_KASAN_HW_TAGS if (HAVE_ARCH_KASAN && ARM64_MTE)
150 select HAVE_ARCH_KFENCE
151 select HAVE_ARCH_KGDB
152 select HAVE_ARCH_MMAP_RND_BITS
153 select HAVE_ARCH_MMAP_RND_COMPAT_BITS if COMPAT
154 select HAVE_ARCH_PFN_VALID
155 select HAVE_ARCH_PREL32_RELOCATIONS
156 select HAVE_ARCH_RANDOMIZE_KSTACK_OFFSET
157 select HAVE_ARCH_SECCOMP_FILTER
158 select HAVE_ARCH_STACKLEAK
159 select HAVE_ARCH_THREAD_STRUCT_WHITELIST
160 select HAVE_ARCH_TRACEHOOK
161 select HAVE_ARCH_TRANSPARENT_HUGEPAGE
162 select HAVE_ARCH_VMAP_STACK
163 select HAVE_ARM_SMCCC
164 select HAVE_ASM_MODVERSIONS
166 select HAVE_C_RECORDMCOUNT
167 select HAVE_CMPXCHG_DOUBLE
168 select HAVE_CMPXCHG_LOCAL
169 select HAVE_CONTEXT_TRACKING
170 select HAVE_DEBUG_BUGVERBOSE
171 select HAVE_DEBUG_KMEMLEAK
172 select HAVE_DMA_CONTIGUOUS
173 select HAVE_DYNAMIC_FTRACE
174 select HAVE_DYNAMIC_FTRACE_WITH_REGS \
175 if $(cc-option,-fpatchable-function-entry=2)
176 select FTRACE_MCOUNT_USE_PATCHABLE_FUNCTION_ENTRY \
177 if DYNAMIC_FTRACE_WITH_REGS
178 select HAVE_EFFICIENT_UNALIGNED_ACCESS
180 select HAVE_FTRACE_MCOUNT_RECORD
181 select HAVE_FUNCTION_TRACER
182 select HAVE_FUNCTION_ERROR_INJECTION
183 select HAVE_FUNCTION_GRAPH_TRACER
184 select HAVE_GCC_PLUGINS
185 select HAVE_HW_BREAKPOINT if PERF_EVENTS
186 select HAVE_IRQ_TIME_ACCOUNTING
188 select HAVE_PATA_PLATFORM
189 select HAVE_PERF_EVENTS
190 select HAVE_PERF_REGS
191 select HAVE_PERF_USER_STACK_DUMP
192 select HAVE_REGS_AND_STACK_ACCESS_API
193 select HAVE_FUNCTION_ARG_ACCESS_API
194 select HAVE_FUTEX_CMPXCHG if FUTEX
195 select MMU_GATHER_RCU_TABLE_FREE
197 select HAVE_STACKPROTECTOR
198 select HAVE_SYSCALL_TRACEPOINTS
200 select HAVE_KRETPROBES
201 select HAVE_GENERIC_VDSO
202 select IOMMU_DMA if IOMMU_SUPPORT
204 select IRQ_FORCED_THREADING
205 select KASAN_VMALLOC if KASAN_GENERIC
206 select MODULES_USE_ELF_RELA
207 select NEED_DMA_MAP_STATE
208 select NEED_SG_DMA_LENGTH
210 select OF_EARLY_FLATTREE
211 select PCI_DOMAINS_GENERIC if PCI
212 select PCI_ECAM if (ACPI && PCI)
213 select PCI_SYSCALL if PCI
218 select SYSCTL_EXCEPTION_TRACE
219 select THREAD_INFO_IN_TASK
220 select HAVE_ARCH_USERFAULTFD_MINOR if USERFAULTFD
222 ARM 64-bit (AArch64) Linux support.
230 config ARM64_PAGE_SHIFT
232 default 16 if ARM64_64K_PAGES
233 default 14 if ARM64_16K_PAGES
236 config ARM64_CONT_PTE_SHIFT
238 default 5 if ARM64_64K_PAGES
239 default 7 if ARM64_16K_PAGES
242 config ARM64_CONT_PMD_SHIFT
244 default 5 if ARM64_64K_PAGES
245 default 5 if ARM64_16K_PAGES
248 config ARCH_MMAP_RND_BITS_MIN
249 default 14 if ARM64_64K_PAGES
250 default 16 if ARM64_16K_PAGES
253 # max bits determined by the following formula:
254 # VA_BITS - PAGE_SHIFT - 3
255 config ARCH_MMAP_RND_BITS_MAX
256 default 19 if ARM64_VA_BITS=36
257 default 24 if ARM64_VA_BITS=39
258 default 27 if ARM64_VA_BITS=42
259 default 30 if ARM64_VA_BITS=47
260 default 29 if ARM64_VA_BITS=48 && ARM64_64K_PAGES
261 default 31 if ARM64_VA_BITS=48 && ARM64_16K_PAGES
262 default 33 if ARM64_VA_BITS=48
263 default 14 if ARM64_64K_PAGES
264 default 16 if ARM64_16K_PAGES
267 config ARCH_MMAP_RND_COMPAT_BITS_MIN
268 default 7 if ARM64_64K_PAGES
269 default 9 if ARM64_16K_PAGES
272 config ARCH_MMAP_RND_COMPAT_BITS_MAX
278 config STACKTRACE_SUPPORT
281 config ILLEGAL_POINTER_VALUE
283 default 0xdead000000000000
285 config LOCKDEP_SUPPORT
288 config TRACE_IRQFLAGS_SUPPORT
295 config GENERIC_BUG_RELATIVE_POINTERS
297 depends on GENERIC_BUG
299 config GENERIC_HWEIGHT
305 config GENERIC_CALIBRATE_DELAY
309 bool "Support DMA zone" if EXPERT
313 bool "Support DMA32 zone" if EXPERT
319 config KERNEL_MODE_NEON
322 config FIX_EARLYCON_MEM
325 config PGTABLE_LEVELS
327 default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36
328 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42
329 default 3 if ARM64_64K_PAGES && (ARM64_VA_BITS_48 || ARM64_VA_BITS_52)
330 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39
331 default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47
332 default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48
334 config ARCH_SUPPORTS_UPROBES
337 config ARCH_PROC_KCORE_TEXT
340 config BROKEN_GAS_INST
341 def_bool !$(as-instr,1:\n.inst 0\n.rept . - 1b\n\nnop\n.endr\n)
343 config KASAN_SHADOW_OFFSET
345 depends on KASAN_GENERIC || KASAN_SW_TAGS
346 default 0xdfff800000000000 if (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) && !KASAN_SW_TAGS
347 default 0xdfffc00000000000 if ARM64_VA_BITS_47 && !KASAN_SW_TAGS
348 default 0xdffffe0000000000 if ARM64_VA_BITS_42 && !KASAN_SW_TAGS
349 default 0xdfffffc000000000 if ARM64_VA_BITS_39 && !KASAN_SW_TAGS
350 default 0xdffffff800000000 if ARM64_VA_BITS_36 && !KASAN_SW_TAGS
351 default 0xefff800000000000 if (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) && KASAN_SW_TAGS
352 default 0xefffc00000000000 if ARM64_VA_BITS_47 && KASAN_SW_TAGS
353 default 0xeffffe0000000000 if ARM64_VA_BITS_42 && KASAN_SW_TAGS
354 default 0xefffffc000000000 if ARM64_VA_BITS_39 && KASAN_SW_TAGS
355 default 0xeffffff800000000 if ARM64_VA_BITS_36 && KASAN_SW_TAGS
356 default 0xffffffffffffffff
358 source "arch/arm64/Kconfig.platforms"
360 menu "Kernel Features"
362 menu "ARM errata workarounds via the alternatives framework"
364 config ARM64_WORKAROUND_CLEAN_CACHE
367 config ARM64_ERRATUM_826319
368 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"
370 select ARM64_WORKAROUND_CLEAN_CACHE
372 This option adds an alternative code sequence to work around ARM
373 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
374 AXI master interface and an L2 cache.
376 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
377 and is unable to accept a certain write via this interface, it will
378 not progress on read data presented on the read data channel and the
381 The workaround promotes data cache clean instructions to
382 data cache clean-and-invalidate.
383 Please note that this does not necessarily enable the workaround,
384 as it depends on the alternative framework, which will only patch
385 the kernel if an affected CPU is detected.
389 config ARM64_ERRATUM_827319
390 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
392 select ARM64_WORKAROUND_CLEAN_CACHE
394 This option adds an alternative code sequence to work around ARM
395 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
396 master interface and an L2 cache.
398 Under certain conditions this erratum can cause a clean line eviction
399 to occur at the same time as another transaction to the same address
400 on the AMBA 5 CHI interface, which can cause data corruption if the
401 interconnect reorders the two transactions.
403 The workaround promotes data cache clean instructions to
404 data cache clean-and-invalidate.
405 Please note that this does not necessarily enable the workaround,
406 as it depends on the alternative framework, which will only patch
407 the kernel if an affected CPU is detected.
411 config ARM64_ERRATUM_824069
412 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
414 select ARM64_WORKAROUND_CLEAN_CACHE
416 This option adds an alternative code sequence to work around ARM
417 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
418 to a coherent interconnect.
420 If a Cortex-A53 processor is executing a store or prefetch for
421 write instruction at the same time as a processor in another
422 cluster is executing a cache maintenance operation to the same
423 address, then this erratum might cause a clean cache line to be
424 incorrectly marked as dirty.
426 The workaround promotes data cache clean instructions to
427 data cache clean-and-invalidate.
428 Please note that this option does not necessarily enable the
429 workaround, as it depends on the alternative framework, which will
430 only patch the kernel if an affected CPU is detected.
434 config ARM64_ERRATUM_819472
435 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
437 select ARM64_WORKAROUND_CLEAN_CACHE
439 This option adds an alternative code sequence to work around ARM
440 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
441 present when it is connected to a coherent interconnect.
443 If the processor is executing a load and store exclusive sequence at
444 the same time as a processor in another cluster is executing a cache
445 maintenance operation to the same address, then this erratum might
446 cause data corruption.
448 The workaround promotes data cache clean instructions to
449 data cache clean-and-invalidate.
450 Please note that this does not necessarily enable the workaround,
451 as it depends on the alternative framework, which will only patch
452 the kernel if an affected CPU is detected.
456 config ARM64_ERRATUM_832075
457 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
460 This option adds an alternative code sequence to work around ARM
461 erratum 832075 on Cortex-A57 parts up to r1p2.
463 Affected Cortex-A57 parts might deadlock when exclusive load/store
464 instructions to Write-Back memory are mixed with Device loads.
466 The workaround is to promote device loads to use Load-Acquire
468 Please note that this does not necessarily enable the workaround,
469 as it depends on the alternative framework, which will only patch
470 the kernel if an affected CPU is detected.
474 config ARM64_ERRATUM_834220
475 bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault"
479 This option adds an alternative code sequence to work around ARM
480 erratum 834220 on Cortex-A57 parts up to r1p2.
482 Affected Cortex-A57 parts might report a Stage 2 translation
483 fault as the result of a Stage 1 fault for load crossing a
484 page boundary when there is a permission or device memory
485 alignment fault at Stage 1 and a translation fault at Stage 2.
487 The workaround is to verify that the Stage 1 translation
488 doesn't generate a fault before handling the Stage 2 fault.
489 Please note that this does not necessarily enable the workaround,
490 as it depends on the alternative framework, which will only patch
491 the kernel if an affected CPU is detected.
495 config ARM64_ERRATUM_845719
496 bool "Cortex-A53: 845719: a load might read incorrect data"
500 This option adds an alternative code sequence to work around ARM
501 erratum 845719 on Cortex-A53 parts up to r0p4.
503 When running a compat (AArch32) userspace on an affected Cortex-A53
504 part, a load at EL0 from a virtual address that matches the bottom 32
505 bits of the virtual address used by a recent load at (AArch64) EL1
506 might return incorrect data.
508 The workaround is to write the contextidr_el1 register on exception
509 return to a 32-bit task.
510 Please note that this does not necessarily enable the workaround,
511 as it depends on the alternative framework, which will only patch
512 the kernel if an affected CPU is detected.
516 config ARM64_ERRATUM_843419
517 bool "Cortex-A53: 843419: A load or store might access an incorrect address"
519 select ARM64_MODULE_PLTS if MODULES
521 This option links the kernel with '--fix-cortex-a53-843419' and
522 enables PLT support to replace certain ADRP instructions, which can
523 cause subsequent memory accesses to use an incorrect address on
524 Cortex-A53 parts up to r0p4.
528 config ARM64_LD_HAS_FIX_ERRATUM_843419
529 def_bool $(ld-option,--fix-cortex-a53-843419)
531 config ARM64_ERRATUM_1024718
532 bool "Cortex-A55: 1024718: Update of DBM/AP bits without break before make might result in incorrect update"
535 This option adds a workaround for ARM Cortex-A55 Erratum 1024718.
537 Affected Cortex-A55 cores (all revisions) could cause incorrect
538 update of the hardware dirty bit when the DBM/AP bits are updated
539 without a break-before-make. The workaround is to disable the usage
540 of hardware DBM locally on the affected cores. CPUs not affected by
541 this erratum will continue to use the feature.
545 config ARM64_ERRATUM_1418040
546 bool "Cortex-A76/Neoverse-N1: MRC read following MRRC read of specific Generic Timer in AArch32 might give incorrect result"
550 This option adds a workaround for ARM Cortex-A76/Neoverse-N1
551 errata 1188873 and 1418040.
553 Affected Cortex-A76/Neoverse-N1 cores (r0p0 to r3p1) could
554 cause register corruption when accessing the timer registers
555 from AArch32 userspace.
559 config ARM64_WORKAROUND_SPECULATIVE_AT
562 config ARM64_ERRATUM_1165522
563 bool "Cortex-A76: 1165522: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"
565 select ARM64_WORKAROUND_SPECULATIVE_AT
567 This option adds a workaround for ARM Cortex-A76 erratum 1165522.
569 Affected Cortex-A76 cores (r0p0, r1p0, r2p0) could end-up with
570 corrupted TLBs by speculating an AT instruction during a guest
575 config ARM64_ERRATUM_1319367
576 bool "Cortex-A57/A72: 1319537: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"
578 select ARM64_WORKAROUND_SPECULATIVE_AT
580 This option adds work arounds for ARM Cortex-A57 erratum 1319537
581 and A72 erratum 1319367
583 Cortex-A57 and A72 cores could end-up with corrupted TLBs by
584 speculating an AT instruction during a guest context switch.
588 config ARM64_ERRATUM_1530923
589 bool "Cortex-A55: 1530923: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"
591 select ARM64_WORKAROUND_SPECULATIVE_AT
593 This option adds a workaround for ARM Cortex-A55 erratum 1530923.
595 Affected Cortex-A55 cores (r0p0, r0p1, r1p0, r2p0) could end-up with
596 corrupted TLBs by speculating an AT instruction during a guest
601 config ARM64_WORKAROUND_REPEAT_TLBI
604 config ARM64_ERRATUM_1286807
605 bool "Cortex-A76: Modification of the translation table for a virtual address might lead to read-after-read ordering violation"
607 select ARM64_WORKAROUND_REPEAT_TLBI
609 This option adds a workaround for ARM Cortex-A76 erratum 1286807.
611 On the affected Cortex-A76 cores (r0p0 to r3p0), if a virtual
612 address for a cacheable mapping of a location is being
613 accessed by a core while another core is remapping the virtual
614 address to a new physical page using the recommended
615 break-before-make sequence, then under very rare circumstances
616 TLBI+DSB completes before a read using the translation being
617 invalidated has been observed by other observers. The
618 workaround repeats the TLBI+DSB operation.
620 config ARM64_ERRATUM_1463225
621 bool "Cortex-A76: Software Step might prevent interrupt recognition"
624 This option adds a workaround for Arm Cortex-A76 erratum 1463225.
626 On the affected Cortex-A76 cores (r0p0 to r3p1), software stepping
627 of a system call instruction (SVC) can prevent recognition of
628 subsequent interrupts when software stepping is disabled in the
629 exception handler of the system call and either kernel debugging
630 is enabled or VHE is in use.
632 Work around the erratum by triggering a dummy step exception
633 when handling a system call from a task that is being stepped
634 in a VHE configuration of the kernel.
638 config ARM64_ERRATUM_1542419
639 bool "Neoverse-N1: workaround mis-ordering of instruction fetches"
642 This option adds a workaround for ARM Neoverse-N1 erratum
645 Affected Neoverse-N1 cores could execute a stale instruction when
646 modified by another CPU. The workaround depends on a firmware
649 Workaround the issue by hiding the DIC feature from EL0. This
650 forces user-space to perform cache maintenance.
654 config ARM64_ERRATUM_1508412
655 bool "Cortex-A77: 1508412: workaround deadlock on sequence of NC/Device load and store exclusive or PAR read"
658 This option adds a workaround for Arm Cortex-A77 erratum 1508412.
660 Affected Cortex-A77 cores (r0p0, r1p0) could deadlock on a sequence
661 of a store-exclusive or read of PAR_EL1 and a load with device or
662 non-cacheable memory attributes. The workaround depends on a firmware
665 KVM guests must also have the workaround implemented or they can
668 Work around the issue by inserting DMB SY barriers around PAR_EL1
669 register reads and warning KVM users. The DMB barrier is sufficient
670 to prevent a speculative PAR_EL1 read.
674 config CAVIUM_ERRATUM_22375
675 bool "Cavium erratum 22375, 24313"
678 Enable workaround for errata 22375 and 24313.
680 This implements two gicv3-its errata workarounds for ThunderX. Both
681 with a small impact affecting only ITS table allocation.
683 erratum 22375: only alloc 8MB table size
684 erratum 24313: ignore memory access type
686 The fixes are in ITS initialization and basically ignore memory access
687 type and table size provided by the TYPER and BASER registers.
691 config CAVIUM_ERRATUM_23144
692 bool "Cavium erratum 23144: ITS SYNC hang on dual socket system"
696 ITS SYNC command hang for cross node io and collections/cpu mapping.
700 config CAVIUM_ERRATUM_23154
701 bool "Cavium erratum 23154: Access to ICC_IAR1_EL1 is not sync'ed"
704 The gicv3 of ThunderX requires a modified version for
705 reading the IAR status to ensure data synchronization
706 (access to icc_iar1_el1 is not sync'ed before and after).
710 config CAVIUM_ERRATUM_27456
711 bool "Cavium erratum 27456: Broadcast TLBI instructions may cause icache corruption"
714 On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI
715 instructions may cause the icache to become corrupted if it
716 contains data for a non-current ASID. The fix is to
717 invalidate the icache when changing the mm context.
721 config CAVIUM_ERRATUM_30115
722 bool "Cavium erratum 30115: Guest may disable interrupts in host"
725 On ThunderX T88 pass 1.x through 2.2, T81 pass 1.0 through
726 1.2, and T83 Pass 1.0, KVM guest execution may disable
727 interrupts in host. Trapping both GICv3 group-0 and group-1
728 accesses sidesteps the issue.
732 config CAVIUM_TX2_ERRATUM_219
733 bool "Cavium ThunderX2 erratum 219: PRFM between TTBR change and ISB fails"
736 On Cavium ThunderX2, a load, store or prefetch instruction between a
737 TTBR update and the corresponding context synchronizing operation can
738 cause a spurious Data Abort to be delivered to any hardware thread in
741 Work around the issue by avoiding the problematic code sequence and
742 trapping KVM guest TTBRx_EL1 writes to EL2 when SMT is enabled. The
743 trap handler performs the corresponding register access, skips the
744 instruction and ensures context synchronization by virtue of the
749 config FUJITSU_ERRATUM_010001
750 bool "Fujitsu-A64FX erratum E#010001: Undefined fault may occur wrongly"
753 This option adds a workaround for Fujitsu-A64FX erratum E#010001.
754 On some variants of the Fujitsu-A64FX cores ver(1.0, 1.1), memory
755 accesses may cause undefined fault (Data abort, DFSC=0b111111).
756 This fault occurs under a specific hardware condition when a
757 load/store instruction performs an address translation using:
758 case-1 TTBR0_EL1 with TCR_EL1.NFD0 == 1.
759 case-2 TTBR0_EL2 with TCR_EL2.NFD0 == 1.
760 case-3 TTBR1_EL1 with TCR_EL1.NFD1 == 1.
761 case-4 TTBR1_EL2 with TCR_EL2.NFD1 == 1.
763 The workaround is to ensure these bits are clear in TCR_ELx.
764 The workaround only affects the Fujitsu-A64FX.
768 config HISILICON_ERRATUM_161600802
769 bool "Hip07 161600802: Erroneous redistributor VLPI base"
772 The HiSilicon Hip07 SoC uses the wrong redistributor base
773 when issued ITS commands such as VMOVP and VMAPP, and requires
774 a 128kB offset to be applied to the target address in this commands.
778 config QCOM_FALKOR_ERRATUM_1003
779 bool "Falkor E1003: Incorrect translation due to ASID change"
782 On Falkor v1, an incorrect ASID may be cached in the TLB when ASID
783 and BADDR are changed together in TTBRx_EL1. Since we keep the ASID
784 in TTBR1_EL1, this situation only occurs in the entry trampoline and
785 then only for entries in the walk cache, since the leaf translation
786 is unchanged. Work around the erratum by invalidating the walk cache
787 entries for the trampoline before entering the kernel proper.
789 config QCOM_FALKOR_ERRATUM_1009
790 bool "Falkor E1009: Prematurely complete a DSB after a TLBI"
792 select ARM64_WORKAROUND_REPEAT_TLBI
794 On Falkor v1, the CPU may prematurely complete a DSB following a
795 TLBI xxIS invalidate maintenance operation. Repeat the TLBI operation
796 one more time to fix the issue.
800 config QCOM_QDF2400_ERRATUM_0065
801 bool "QDF2400 E0065: Incorrect GITS_TYPER.ITT_Entry_size"
804 On Qualcomm Datacenter Technologies QDF2400 SoC, ITS hardware reports
805 ITE size incorrectly. The GITS_TYPER.ITT_Entry_size field should have
806 been indicated as 16Bytes (0xf), not 8Bytes (0x7).
810 config QCOM_FALKOR_ERRATUM_E1041
811 bool "Falkor E1041: Speculative instruction fetches might cause errant memory access"
814 Falkor CPU may speculatively fetch instructions from an improper
815 memory location when MMU translation is changed from SCTLR_ELn[M]=1
816 to SCTLR_ELn[M]=0. Prefix an ISB instruction to fix the problem.
820 config NVIDIA_CARMEL_CNP_ERRATUM
821 bool "NVIDIA Carmel CNP: CNP on Carmel semantically different than ARM cores"
824 If CNP is enabled on Carmel cores, non-sharable TLBIs on a core will not
825 invalidate shared TLB entries installed by a different core, as it would
826 on standard ARM cores.
830 config SOCIONEXT_SYNQUACER_PREITS
831 bool "Socionext Synquacer: Workaround for GICv3 pre-ITS"
834 Socionext Synquacer SoCs implement a separate h/w block to generate
835 MSI doorbell writes with non-zero values for the device ID.
844 default ARM64_4K_PAGES
846 Page size (translation granule) configuration.
848 config ARM64_4K_PAGES
851 This feature enables 4KB pages support.
853 config ARM64_16K_PAGES
856 The system will use 16KB pages support. AArch32 emulation
857 requires applications compiled with 16K (or a multiple of 16K)
860 config ARM64_64K_PAGES
863 This feature enables 64KB pages support (4KB by default)
864 allowing only two levels of page tables and faster TLB
865 look-up. AArch32 emulation requires applications compiled
866 with 64K aligned segments.
871 prompt "Virtual address space size"
872 default ARM64_VA_BITS_39 if ARM64_4K_PAGES
873 default ARM64_VA_BITS_47 if ARM64_16K_PAGES
874 default ARM64_VA_BITS_42 if ARM64_64K_PAGES
876 Allows choosing one of multiple possible virtual address
877 space sizes. The level of translation table is determined by
878 a combination of page size and virtual address space size.
880 config ARM64_VA_BITS_36
881 bool "36-bit" if EXPERT
882 depends on ARM64_16K_PAGES
884 config ARM64_VA_BITS_39
886 depends on ARM64_4K_PAGES
888 config ARM64_VA_BITS_42
890 depends on ARM64_64K_PAGES
892 config ARM64_VA_BITS_47
894 depends on ARM64_16K_PAGES
896 config ARM64_VA_BITS_48
899 config ARM64_VA_BITS_52
901 depends on ARM64_64K_PAGES && (ARM64_PAN || !ARM64_SW_TTBR0_PAN)
903 Enable 52-bit virtual addressing for userspace when explicitly
904 requested via a hint to mmap(). The kernel will also use 52-bit
905 virtual addresses for its own mappings (provided HW support for
906 this feature is available, otherwise it reverts to 48-bit).
908 NOTE: Enabling 52-bit virtual addressing in conjunction with
909 ARMv8.3 Pointer Authentication will result in the PAC being
910 reduced from 7 bits to 3 bits, which may have a significant
911 impact on its susceptibility to brute-force attacks.
913 If unsure, select 48-bit virtual addressing instead.
917 config ARM64_FORCE_52BIT
918 bool "Force 52-bit virtual addresses for userspace"
919 depends on ARM64_VA_BITS_52 && EXPERT
921 For systems with 52-bit userspace VAs enabled, the kernel will attempt
922 to maintain compatibility with older software by providing 48-bit VAs
923 unless a hint is supplied to mmap.
925 This configuration option disables the 48-bit compatibility logic, and
926 forces all userspace addresses to be 52-bit on HW that supports it. One
927 should only enable this configuration option for stress testing userspace
928 memory management code. If unsure say N here.
932 default 36 if ARM64_VA_BITS_36
933 default 39 if ARM64_VA_BITS_39
934 default 42 if ARM64_VA_BITS_42
935 default 47 if ARM64_VA_BITS_47
936 default 48 if ARM64_VA_BITS_48
937 default 52 if ARM64_VA_BITS_52
940 prompt "Physical address space size"
941 default ARM64_PA_BITS_48
943 Choose the maximum physical address range that the kernel will
946 config ARM64_PA_BITS_48
949 config ARM64_PA_BITS_52
950 bool "52-bit (ARMv8.2)"
951 depends on ARM64_64K_PAGES
952 depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN
954 Enable support for a 52-bit physical address space, introduced as
955 part of the ARMv8.2-LPA extension.
957 With this enabled, the kernel will also continue to work on CPUs that
958 do not support ARMv8.2-LPA, but with some added memory overhead (and
959 minor performance overhead).
965 default 48 if ARM64_PA_BITS_48
966 default 52 if ARM64_PA_BITS_52
970 default CPU_LITTLE_ENDIAN
972 Select the endianness of data accesses performed by the CPU. Userspace
973 applications will need to be compiled and linked for the endianness
974 that is selected here.
976 config CPU_BIG_ENDIAN
977 bool "Build big-endian kernel"
978 depends on !LD_IS_LLD || LLD_VERSION >= 130000
980 Say Y if you plan on running a kernel with a big-endian userspace.
982 config CPU_LITTLE_ENDIAN
983 bool "Build little-endian kernel"
985 Say Y if you plan on running a kernel with a little-endian userspace.
986 This is usually the case for distributions targeting arm64.
991 bool "Multi-core scheduler support"
993 Multi-core scheduler support improves the CPU scheduler's decision
994 making when dealing with multi-core CPU chips at a cost of slightly
995 increased overhead in some places. If unsure say N here.
998 bool "SMT scheduler support"
1000 Improves the CPU scheduler's decision making when dealing with
1001 MultiThreading at a cost of slightly increased overhead in some
1002 places. If unsure say N here.
1005 int "Maximum number of CPUs (2-4096)"
1010 bool "Support for hot-pluggable CPUs"
1011 select GENERIC_IRQ_MIGRATION
1013 Say Y here to experiment with turning CPUs off and on. CPUs
1014 can be controlled through /sys/devices/system/cpu.
1016 # Common NUMA Features
1018 bool "NUMA Memory Allocation and Scheduler Support"
1019 select GENERIC_ARCH_NUMA
1020 select ACPI_NUMA if ACPI
1023 Enable NUMA (Non-Uniform Memory Access) support.
1025 The kernel will try to allocate memory used by a CPU on the
1026 local memory of the CPU and add some more
1027 NUMA awareness to the kernel.
1030 int "Maximum NUMA Nodes (as a power of 2)"
1033 depends on NEED_MULTIPLE_NODES
1035 Specify the maximum number of NUMA Nodes available on the target
1036 system. Increases memory reserved to accommodate various tables.
1038 config USE_PERCPU_NUMA_NODE_ID
1042 config HAVE_SETUP_PER_CPU_AREA
1046 config NEED_PER_CPU_EMBED_FIRST_CHUNK
1050 config HOLES_IN_ZONE
1053 source "kernel/Kconfig.hz"
1055 config ARCH_SPARSEMEM_ENABLE
1057 select SPARSEMEM_VMEMMAP_ENABLE
1059 config ARCH_SPARSEMEM_DEFAULT
1060 def_bool ARCH_SPARSEMEM_ENABLE
1062 config ARCH_SELECT_MEMORY_MODEL
1063 def_bool ARCH_SPARSEMEM_ENABLE
1065 config ARCH_FLATMEM_ENABLE
1068 config HW_PERF_EVENTS
1072 config ARCH_HAS_FILTER_PGPROT
1075 config ARCH_ENABLE_SPLIT_PMD_PTLOCK
1076 def_bool y if PGTABLE_LEVELS > 2
1078 # Supported by clang >= 7.0
1079 config CC_HAVE_SHADOW_CALL_STACK
1080 def_bool $(cc-option, -fsanitize=shadow-call-stack -ffixed-x18)
1083 bool "Enable paravirtualization code"
1085 This changes the kernel so it can modify itself when it is run
1086 under a hypervisor, potentially improving performance significantly
1087 over full virtualization.
1089 config PARAVIRT_TIME_ACCOUNTING
1090 bool "Paravirtual steal time accounting"
1093 Select this option to enable fine granularity task steal time
1094 accounting. Time spent executing other tasks in parallel with
1095 the current vCPU is discounted from the vCPU power. To account for
1096 that, there can be a small performance impact.
1098 If in doubt, say N here.
1101 depends on PM_SLEEP_SMP
1103 bool "kexec system call"
1105 kexec is a system call that implements the ability to shutdown your
1106 current kernel, and to start another kernel. It is like a reboot
1107 but it is independent of the system firmware. And like a reboot
1108 you can start any kernel with it, not just Linux.
1111 bool "kexec file based system call"
1113 select HAVE_IMA_KEXEC if IMA
1115 This is new version of kexec system call. This system call is
1116 file based and takes file descriptors as system call argument
1117 for kernel and initramfs as opposed to list of segments as
1118 accepted by previous system call.
1121 bool "Verify kernel signature during kexec_file_load() syscall"
1122 depends on KEXEC_FILE
1124 Select this option to verify a signature with loaded kernel
1125 image. If configured, any attempt of loading a image without
1126 valid signature will fail.
1128 In addition to that option, you need to enable signature
1129 verification for the corresponding kernel image type being
1130 loaded in order for this to work.
1132 config KEXEC_IMAGE_VERIFY_SIG
1133 bool "Enable Image signature verification support"
1135 depends on KEXEC_SIG
1136 depends on EFI && SIGNED_PE_FILE_VERIFICATION
1138 Enable Image signature verification support.
1140 comment "Support for PE file signature verification disabled"
1141 depends on KEXEC_SIG
1142 depends on !EFI || !SIGNED_PE_FILE_VERIFICATION
1145 bool "Build kdump crash kernel"
1147 Generate crash dump after being started by kexec. This should
1148 be normally only set in special crash dump kernels which are
1149 loaded in the main kernel with kexec-tools into a specially
1150 reserved region and then later executed after a crash by
1153 For more details see Documentation/admin-guide/kdump/kdump.rst
1157 depends on HIBERNATION
1164 bool "Xen guest support on ARM64"
1165 depends on ARM64 && OF
1169 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64.
1171 config FORCE_MAX_ZONEORDER
1173 default "14" if ARM64_64K_PAGES
1174 default "12" if ARM64_16K_PAGES
1177 The kernel memory allocator divides physically contiguous memory
1178 blocks into "zones", where each zone is a power of two number of
1179 pages. This option selects the largest power of two that the kernel
1180 keeps in the memory allocator. If you need to allocate very large
1181 blocks of physically contiguous memory, then you may need to
1182 increase this value.
1184 This config option is actually maximum order plus one. For example,
1185 a value of 11 means that the largest free memory block is 2^10 pages.
1187 We make sure that we can allocate upto a HugePage size for each configuration.
1189 MAX_ORDER = (PMD_SHIFT - PAGE_SHIFT) + 1 => PAGE_SHIFT - 2
1191 However for 4K, we choose a higher default value, 11 as opposed to 10, giving us
1192 4M allocations matching the default size used by generic code.
1194 config UNMAP_KERNEL_AT_EL0
1195 bool "Unmap kernel when running in userspace (aka \"KAISER\")" if EXPERT
1198 Speculation attacks against some high-performance processors can
1199 be used to bypass MMU permission checks and leak kernel data to
1200 userspace. This can be defended against by unmapping the kernel
1201 when running in userspace, mapping it back in on exception entry
1202 via a trampoline page in the vector table.
1206 config RODATA_FULL_DEFAULT_ENABLED
1207 bool "Apply r/o permissions of VM areas also to their linear aliases"
1210 Apply read-only attributes of VM areas to the linear alias of
1211 the backing pages as well. This prevents code or read-only data
1212 from being modified (inadvertently or intentionally) via another
1213 mapping of the same memory page. This additional enhancement can
1214 be turned off at runtime by passing rodata=[off|on] (and turned on
1215 with rodata=full if this option is set to 'n')
1217 This requires the linear region to be mapped down to pages,
1218 which may adversely affect performance in some cases.
1220 config ARM64_SW_TTBR0_PAN
1221 bool "Emulate Privileged Access Never using TTBR0_EL1 switching"
1223 Enabling this option prevents the kernel from accessing
1224 user-space memory directly by pointing TTBR0_EL1 to a reserved
1225 zeroed area and reserved ASID. The user access routines
1226 restore the valid TTBR0_EL1 temporarily.
1228 config ARM64_TAGGED_ADDR_ABI
1229 bool "Enable the tagged user addresses syscall ABI"
1232 When this option is enabled, user applications can opt in to a
1233 relaxed ABI via prctl() allowing tagged addresses to be passed
1234 to system calls as pointer arguments. For details, see
1235 Documentation/arm64/tagged-address-abi.rst.
1238 bool "Kernel support for 32-bit EL0"
1239 depends on ARM64_4K_PAGES || EXPERT
1241 select OLD_SIGSUSPEND3
1242 select COMPAT_OLD_SIGACTION
1244 This option enables support for a 32-bit EL0 running under a 64-bit
1245 kernel at EL1. AArch32-specific components such as system calls,
1246 the user helper functions, VFP support and the ptrace interface are
1247 handled appropriately by the kernel.
1249 If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware
1250 that you will only be able to execute AArch32 binaries that were compiled
1251 with page size aligned segments.
1253 If you want to execute 32-bit userspace applications, say Y.
1257 config KUSER_HELPERS
1258 bool "Enable kuser helpers page for 32-bit applications"
1261 Warning: disabling this option may break 32-bit user programs.
1263 Provide kuser helpers to compat tasks. The kernel provides
1264 helper code to userspace in read only form at a fixed location
1265 to allow userspace to be independent of the CPU type fitted to
1266 the system. This permits binaries to be run on ARMv4 through
1267 to ARMv8 without modification.
1269 See Documentation/arm/kernel_user_helpers.rst for details.
1271 However, the fixed address nature of these helpers can be used
1272 by ROP (return orientated programming) authors when creating
1275 If all of the binaries and libraries which run on your platform
1276 are built specifically for your platform, and make no use of
1277 these helpers, then you can turn this option off to hinder
1278 such exploits. However, in that case, if a binary or library
1279 relying on those helpers is run, it will not function correctly.
1281 Say N here only if you are absolutely certain that you do not
1282 need these helpers; otherwise, the safe option is to say Y.
1285 bool "Enable vDSO for 32-bit applications"
1286 depends on !CPU_BIG_ENDIAN && "$(CROSS_COMPILE_COMPAT)" != ""
1287 select GENERIC_COMPAT_VDSO
1290 Place in the process address space of 32-bit applications an
1291 ELF shared object providing fast implementations of gettimeofday
1294 You must have a 32-bit build of glibc 2.22 or later for programs
1295 to seamlessly take advantage of this.
1297 config THUMB2_COMPAT_VDSO
1298 bool "Compile the 32-bit vDSO for Thumb-2 mode" if EXPERT
1299 depends on COMPAT_VDSO
1302 Compile the compat vDSO with '-mthumb -fomit-frame-pointer' if y,
1303 otherwise with '-marm'.
1305 menuconfig ARMV8_DEPRECATED
1306 bool "Emulate deprecated/obsolete ARMv8 instructions"
1309 Legacy software support may require certain instructions
1310 that have been deprecated or obsoleted in the architecture.
1312 Enable this config to enable selective emulation of these
1319 config SWP_EMULATION
1320 bool "Emulate SWP/SWPB instructions"
1322 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that
1323 they are always undefined. Say Y here to enable software
1324 emulation of these instructions for userspace using LDXR/STXR.
1325 This feature can be controlled at runtime with the abi.swp
1326 sysctl which is disabled by default.
1328 In some older versions of glibc [<=2.8] SWP is used during futex
1329 trylock() operations with the assumption that the code will not
1330 be preempted. This invalid assumption may be more likely to fail
1331 with SWP emulation enabled, leading to deadlock of the user
1334 NOTE: when accessing uncached shared regions, LDXR/STXR rely
1335 on an external transaction monitoring block called a global
1336 monitor to maintain update atomicity. If your system does not
1337 implement a global monitor, this option can cause programs that
1338 perform SWP operations to uncached memory to deadlock.
1342 config CP15_BARRIER_EMULATION
1343 bool "Emulate CP15 Barrier instructions"
1345 The CP15 barrier instructions - CP15ISB, CP15DSB, and
1346 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
1347 strongly recommended to use the ISB, DSB, and DMB
1348 instructions instead.
1350 Say Y here to enable software emulation of these
1351 instructions for AArch32 userspace code. When this option is
1352 enabled, CP15 barrier usage is traced which can help
1353 identify software that needs updating. This feature can be
1354 controlled at runtime with the abi.cp15_barrier sysctl.
1358 config SETEND_EMULATION
1359 bool "Emulate SETEND instruction"
1361 The SETEND instruction alters the data-endianness of the
1362 AArch32 EL0, and is deprecated in ARMv8.
1364 Say Y here to enable software emulation of the instruction
1365 for AArch32 userspace code. This feature can be controlled
1366 at runtime with the abi.setend sysctl.
1368 Note: All the cpus on the system must have mixed endian support at EL0
1369 for this feature to be enabled. If a new CPU - which doesn't support mixed
1370 endian - is hotplugged in after this feature has been enabled, there could
1371 be unexpected results in the applications.
1378 menu "ARMv8.1 architectural features"
1380 config ARM64_HW_AFDBM
1381 bool "Support for hardware updates of the Access and Dirty page flags"
1384 The ARMv8.1 architecture extensions introduce support for
1385 hardware updates of the access and dirty information in page
1386 table entries. When enabled in TCR_EL1 (HA and HD bits) on
1387 capable processors, accesses to pages with PTE_AF cleared will
1388 set this bit instead of raising an access flag fault.
1389 Similarly, writes to read-only pages with the DBM bit set will
1390 clear the read-only bit (AP[2]) instead of raising a
1393 Kernels built with this configuration option enabled continue
1394 to work on pre-ARMv8.1 hardware and the performance impact is
1395 minimal. If unsure, say Y.
1398 bool "Enable support for Privileged Access Never (PAN)"
1401 Privileged Access Never (PAN; part of the ARMv8.1 Extensions)
1402 prevents the kernel or hypervisor from accessing user-space (EL0)
1405 Choosing this option will cause any unprotected (not using
1406 copy_to_user et al) memory access to fail with a permission fault.
1408 The feature is detected at runtime, and will remain as a 'nop'
1409 instruction if the cpu does not implement the feature.
1412 def_bool $(as-instr,.arch_extension rcpc)
1414 config AS_HAS_LSE_ATOMICS
1415 def_bool $(as-instr,.arch_extension lse)
1417 config ARM64_LSE_ATOMICS
1419 default ARM64_USE_LSE_ATOMICS
1420 depends on AS_HAS_LSE_ATOMICS
1422 config ARM64_USE_LSE_ATOMICS
1423 bool "Atomic instructions"
1424 depends on JUMP_LABEL
1427 As part of the Large System Extensions, ARMv8.1 introduces new
1428 atomic instructions that are designed specifically to scale in
1431 Say Y here to make use of these instructions for the in-kernel
1432 atomic routines. This incurs a small overhead on CPUs that do
1433 not support these instructions and requires the kernel to be
1434 built with binutils >= 2.25 in order for the new instructions
1439 menu "ARMv8.2 architectural features"
1442 bool "Enable support for persistent memory"
1443 select ARCH_HAS_PMEM_API
1444 select ARCH_HAS_UACCESS_FLUSHCACHE
1446 Say Y to enable support for the persistent memory API based on the
1447 ARMv8.2 DCPoP feature.
1449 The feature is detected at runtime, and the kernel will use DC CVAC
1450 operations if DC CVAP is not supported (following the behaviour of
1451 DC CVAP itself if the system does not define a point of persistence).
1453 config ARM64_RAS_EXTN
1454 bool "Enable support for RAS CPU Extensions"
1457 CPUs that support the Reliability, Availability and Serviceability
1458 (RAS) Extensions, part of ARMv8.2 are able to track faults and
1459 errors, classify them and report them to software.
1461 On CPUs with these extensions system software can use additional
1462 barriers to determine if faults are pending and read the
1463 classification from a new set of registers.
1465 Selecting this feature will allow the kernel to use these barriers
1466 and access the new registers if the system supports the extension.
1467 Platform RAS features may additionally depend on firmware support.
1470 bool "Enable support for Common Not Private (CNP) translations"
1472 depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN
1474 Common Not Private (CNP) allows translation table entries to
1475 be shared between different PEs in the same inner shareable
1476 domain, so the hardware can use this fact to optimise the
1477 caching of such entries in the TLB.
1479 Selecting this option allows the CNP feature to be detected
1480 at runtime, and does not affect PEs that do not implement
1485 menu "ARMv8.3 architectural features"
1487 config ARM64_PTR_AUTH
1488 bool "Enable support for pointer authentication"
1490 depends on (CC_HAS_SIGN_RETURN_ADDRESS || CC_HAS_BRANCH_PROT_PAC_RET) && AS_HAS_PAC
1491 # Modern compilers insert a .note.gnu.property section note for PAC
1492 # which is only understood by binutils starting with version 2.33.1.
1493 depends on LD_IS_LLD || LD_VERSION >= 23301 || (CC_IS_GCC && GCC_VERSION < 90100)
1494 depends on !CC_IS_CLANG || AS_HAS_CFI_NEGATE_RA_STATE
1495 depends on (!FUNCTION_GRAPH_TRACER || DYNAMIC_FTRACE_WITH_REGS)
1497 Pointer authentication (part of the ARMv8.3 Extensions) provides
1498 instructions for signing and authenticating pointers against secret
1499 keys, which can be used to mitigate Return Oriented Programming (ROP)
1502 This option enables these instructions at EL0 (i.e. for userspace).
1503 Choosing this option will cause the kernel to initialise secret keys
1504 for each process at exec() time, with these keys being
1505 context-switched along with the process.
1507 If the compiler supports the -mbranch-protection or
1508 -msign-return-address flag (e.g. GCC 7 or later), then this option
1509 will also cause the kernel itself to be compiled with return address
1510 protection. In this case, and if the target hardware is known to
1511 support pointer authentication, then CONFIG_STACKPROTECTOR can be
1512 disabled with minimal loss of protection.
1514 The feature is detected at runtime. If the feature is not present in
1515 hardware it will not be advertised to userspace/KVM guest nor will it
1518 If the feature is present on the boot CPU but not on a late CPU, then
1519 the late CPU will be parked. Also, if the boot CPU does not have
1520 address auth and the late CPU has then the late CPU will still boot
1521 but with the feature disabled. On such a system, this option should
1524 This feature works with FUNCTION_GRAPH_TRACER option only if
1525 DYNAMIC_FTRACE_WITH_REGS is enabled.
1527 config CC_HAS_BRANCH_PROT_PAC_RET
1528 # GCC 9 or later, clang 8 or later
1529 def_bool $(cc-option,-mbranch-protection=pac-ret+leaf)
1531 config CC_HAS_SIGN_RETURN_ADDRESS
1533 def_bool $(cc-option,-msign-return-address=all)
1536 def_bool $(cc-option,-Wa$(comma)-march=armv8.3-a)
1538 config AS_HAS_CFI_NEGATE_RA_STATE
1539 def_bool $(as-instr,.cfi_startproc\n.cfi_negate_ra_state\n.cfi_endproc\n)
1543 menu "ARMv8.4 architectural features"
1545 config ARM64_AMU_EXTN
1546 bool "Enable support for the Activity Monitors Unit CPU extension"
1549 The activity monitors extension is an optional extension introduced
1550 by the ARMv8.4 CPU architecture. This enables support for version 1
1551 of the activity monitors architecture, AMUv1.
1553 To enable the use of this extension on CPUs that implement it, say Y.
1555 Note that for architectural reasons, firmware _must_ implement AMU
1556 support when running on CPUs that present the activity monitors
1557 extension. The required support is present in:
1558 * Version 1.5 and later of the ARM Trusted Firmware
1560 For kernels that have this configuration enabled but boot with broken
1561 firmware, you may need to say N here until the firmware is fixed.
1562 Otherwise you may experience firmware panics or lockups when
1563 accessing the counter registers. Even if you are not observing these
1564 symptoms, the values returned by the register reads might not
1565 correctly reflect reality. Most commonly, the value read will be 0,
1566 indicating that the counter is not enabled.
1568 config AS_HAS_ARMV8_4
1569 def_bool $(cc-option,-Wa$(comma)-march=armv8.4-a)
1571 config ARM64_TLB_RANGE
1572 bool "Enable support for tlbi range feature"
1574 depends on AS_HAS_ARMV8_4
1576 ARMv8.4-TLBI provides TLBI invalidation instruction that apply to a
1577 range of input addresses.
1579 The feature introduces new assembly instructions, and they were
1580 support when binutils >= 2.30.
1584 menu "ARMv8.5 architectural features"
1586 config AS_HAS_ARMV8_5
1587 def_bool $(cc-option,-Wa$(comma)-march=armv8.5-a)
1590 bool "Branch Target Identification support"
1593 Branch Target Identification (part of the ARMv8.5 Extensions)
1594 provides a mechanism to limit the set of locations to which computed
1595 branch instructions such as BR or BLR can jump.
1597 To make use of BTI on CPUs that support it, say Y.
1599 BTI is intended to provide complementary protection to other control
1600 flow integrity protection mechanisms, such as the Pointer
1601 authentication mechanism provided as part of the ARMv8.3 Extensions.
1602 For this reason, it does not make sense to enable this option without
1603 also enabling support for pointer authentication. Thus, when
1604 enabling this option you should also select ARM64_PTR_AUTH=y.
1606 Userspace binaries must also be specifically compiled to make use of
1607 this mechanism. If you say N here or the hardware does not support
1608 BTI, such binaries can still run, but you get no additional
1609 enforcement of branch destinations.
1611 config ARM64_BTI_KERNEL
1612 bool "Use Branch Target Identification for kernel"
1614 depends on ARM64_BTI
1615 depends on ARM64_PTR_AUTH
1616 depends on CC_HAS_BRANCH_PROT_PAC_RET_BTI
1617 # https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94697
1618 depends on !CC_IS_GCC || GCC_VERSION >= 100100
1619 depends on !(CC_IS_CLANG && GCOV_KERNEL)
1620 depends on (!FUNCTION_GRAPH_TRACER || DYNAMIC_FTRACE_WITH_REGS)
1622 Build the kernel with Branch Target Identification annotations
1623 and enable enforcement of this for kernel code. When this option
1624 is enabled and the system supports BTI all kernel code including
1625 modular code must have BTI enabled.
1627 config CC_HAS_BRANCH_PROT_PAC_RET_BTI
1628 # GCC 9 or later, clang 8 or later
1629 def_bool $(cc-option,-mbranch-protection=pac-ret+leaf+bti)
1632 bool "Enable support for E0PD"
1635 E0PD (part of the ARMv8.5 extensions) allows us to ensure
1636 that EL0 accesses made via TTBR1 always fault in constant time,
1637 providing similar benefits to KASLR as those provided by KPTI, but
1638 with lower overhead and without disrupting legitimate access to
1639 kernel memory such as SPE.
1641 This option enables E0PD for TTBR1 where available.
1644 bool "Enable support for random number generation"
1647 Random number generation (part of the ARMv8.5 Extensions)
1648 provides a high bandwidth, cryptographically secure
1649 hardware random number generator.
1651 config ARM64_AS_HAS_MTE
1652 # Initial support for MTE went in binutils 2.32.0, checked with
1653 # ".arch armv8.5-a+memtag" below. However, this was incomplete
1654 # as a late addition to the final architecture spec (LDGM/STGM)
1655 # is only supported in the newer 2.32.x and 2.33 binutils
1656 # versions, hence the extra "stgm" instruction check below.
1657 def_bool $(as-instr,.arch armv8.5-a+memtag\nstgm xzr$(comma)[x0])
1660 bool "Memory Tagging Extension support"
1662 depends on ARM64_AS_HAS_MTE && ARM64_TAGGED_ADDR_ABI
1663 depends on AS_HAS_ARMV8_5
1664 depends on AS_HAS_LSE_ATOMICS
1665 # Required for tag checking in the uaccess routines
1666 depends on ARM64_PAN
1667 select ARCH_USES_HIGH_VMA_FLAGS
1669 Memory Tagging (part of the ARMv8.5 Extensions) provides
1670 architectural support for run-time, always-on detection of
1671 various classes of memory error to aid with software debugging
1672 to eliminate vulnerabilities arising from memory-unsafe
1675 This option enables the support for the Memory Tagging
1676 Extension at EL0 (i.e. for userspace).
1678 Selecting this option allows the feature to be detected at
1679 runtime. Any secondary CPU not implementing this feature will
1680 not be allowed a late bring-up.
1682 Userspace binaries that want to use this feature must
1683 explicitly opt in. The mechanism for the userspace is
1686 Documentation/arm64/memory-tagging-extension.rst.
1690 menu "ARMv8.7 architectural features"
1693 bool "Enable support for Enhanced Privileged Access Never (EPAN)"
1695 depends on ARM64_PAN
1697 Enhanced Privileged Access Never (EPAN) allows Privileged
1698 Access Never to be used with Execute-only mappings.
1700 The feature is detected at runtime, and will remain disabled
1701 if the cpu does not implement the feature.
1705 bool "ARM Scalable Vector Extension support"
1708 The Scalable Vector Extension (SVE) is an extension to the AArch64
1709 execution state which complements and extends the SIMD functionality
1710 of the base architecture to support much larger vectors and to enable
1711 additional vectorisation opportunities.
1713 To enable use of this extension on CPUs that implement it, say Y.
1715 On CPUs that support the SVE2 extensions, this option will enable
1718 Note that for architectural reasons, firmware _must_ implement SVE
1719 support when running on SVE capable hardware. The required support
1722 * version 1.5 and later of the ARM Trusted Firmware
1723 * the AArch64 boot wrapper since commit 5e1261e08abf
1724 ("bootwrapper: SVE: Enable SVE for EL2 and below").
1726 For other firmware implementations, consult the firmware documentation
1729 If you need the kernel to boot on SVE-capable hardware with broken
1730 firmware, you may need to say N here until you get your firmware
1731 fixed. Otherwise, you may experience firmware panics or lockups when
1732 booting the kernel. If unsure and you are not observing these
1733 symptoms, you should assume that it is safe to say Y.
1735 config ARM64_MODULE_PLTS
1736 bool "Use PLTs to allow module memory to spill over into vmalloc area"
1738 select HAVE_MOD_ARCH_SPECIFIC
1740 Allocate PLTs when loading modules so that jumps and calls whose
1741 targets are too far away for their relative offsets to be encoded
1742 in the instructions themselves can be bounced via veneers in the
1743 module's PLT. This allows modules to be allocated in the generic
1744 vmalloc area after the dedicated module memory area has been
1747 When running with address space randomization (KASLR), the module
1748 region itself may be too far away for ordinary relative jumps and
1749 calls, and so in that case, module PLTs are required and cannot be
1752 Specific errata workaround(s) might also force module PLTs to be
1753 enabled (ARM64_ERRATUM_843419).
1755 config ARM64_PSEUDO_NMI
1756 bool "Support for NMI-like interrupts"
1759 Adds support for mimicking Non-Maskable Interrupts through the use of
1760 GIC interrupt priority. This support requires version 3 or later of
1763 This high priority configuration for interrupts needs to be
1764 explicitly enabled by setting the kernel parameter
1765 "irqchip.gicv3_pseudo_nmi" to 1.
1770 config ARM64_DEBUG_PRIORITY_MASKING
1771 bool "Debug interrupt priority masking"
1773 This adds runtime checks to functions enabling/disabling
1774 interrupts when using priority masking. The additional checks verify
1775 the validity of ICC_PMR_EL1 when calling concerned functions.
1781 bool "Build a relocatable kernel image" if EXPERT
1782 select ARCH_HAS_RELR
1785 This builds the kernel as a Position Independent Executable (PIE),
1786 which retains all relocation metadata required to relocate the
1787 kernel binary at runtime to a different virtual address than the
1788 address it was linked at.
1789 Since AArch64 uses the RELA relocation format, this requires a
1790 relocation pass at runtime even if the kernel is loaded at the
1791 same address it was linked at.
1793 config RANDOMIZE_BASE
1794 bool "Randomize the address of the kernel image"
1795 select ARM64_MODULE_PLTS if MODULES
1798 Randomizes the virtual address at which the kernel image is
1799 loaded, as a security feature that deters exploit attempts
1800 relying on knowledge of the location of kernel internals.
1802 It is the bootloader's job to provide entropy, by passing a
1803 random u64 value in /chosen/kaslr-seed at kernel entry.
1805 When booting via the UEFI stub, it will invoke the firmware's
1806 EFI_RNG_PROTOCOL implementation (if available) to supply entropy
1807 to the kernel proper. In addition, it will randomise the physical
1808 location of the kernel Image as well.
1812 config RANDOMIZE_MODULE_REGION_FULL
1813 bool "Randomize the module region over a 4 GB range"
1814 depends on RANDOMIZE_BASE
1817 Randomizes the location of the module region inside a 4 GB window
1818 covering the core kernel. This way, it is less likely for modules
1819 to leak information about the location of core kernel data structures
1820 but it does imply that function calls between modules and the core
1821 kernel will need to be resolved via veneers in the module PLT.
1823 When this option is not set, the module region will be randomized over
1824 a limited range that contains the [_stext, _etext] interval of the
1825 core kernel, so branch relocations are always in range.
1827 config CC_HAVE_STACKPROTECTOR_SYSREG
1828 def_bool $(cc-option,-mstack-protector-guard=sysreg -mstack-protector-guard-reg=sp_el0 -mstack-protector-guard-offset=0)
1830 config STACKPROTECTOR_PER_TASK
1832 depends on STACKPROTECTOR && CC_HAVE_STACKPROTECTOR_SYSREG
1838 config ARM64_ACPI_PARKING_PROTOCOL
1839 bool "Enable support for the ARM64 ACPI parking protocol"
1842 Enable support for the ARM64 ACPI parking protocol. If disabled
1843 the kernel will not allow booting through the ARM64 ACPI parking
1844 protocol even if the corresponding data is present in the ACPI
1848 string "Default kernel command string"
1851 Provide a set of default command-line options at build time by
1852 entering them here. As a minimum, you should specify the the
1853 root device (e.g. root=/dev/nfs).
1856 prompt "Kernel command line type" if CMDLINE != ""
1857 default CMDLINE_FROM_BOOTLOADER
1859 Choose how the kernel will handle the provided default kernel
1860 command line string.
1862 config CMDLINE_FROM_BOOTLOADER
1863 bool "Use bootloader kernel arguments if available"
1865 Uses the command-line options passed by the boot loader. If
1866 the boot loader doesn't provide any, the default kernel command
1867 string provided in CMDLINE will be used.
1869 config CMDLINE_FORCE
1870 bool "Always use the default kernel command string"
1872 Always use the default kernel command string, even if the boot
1873 loader passes other arguments to the kernel.
1874 This is useful if you cannot or don't want to change the
1875 command-line options your boot loader passes to the kernel.
1883 bool "UEFI runtime support"
1884 depends on OF && !CPU_BIG_ENDIAN
1885 depends on KERNEL_MODE_NEON
1886 select ARCH_SUPPORTS_ACPI
1889 select EFI_PARAMS_FROM_FDT
1890 select EFI_RUNTIME_WRAPPERS
1892 select EFI_GENERIC_STUB
1893 imply IMA_SECURE_AND_OR_TRUSTED_BOOT
1896 This option provides support for runtime services provided
1897 by UEFI firmware (such as non-volatile variables, realtime
1898 clock, and platform reset). A UEFI stub is also provided to
1899 allow the kernel to be booted as an EFI application. This
1900 is only useful on systems that have UEFI firmware.
1903 bool "Enable support for SMBIOS (DMI) tables"
1907 This enables SMBIOS/DMI feature for systems.
1909 This option is only useful on systems that have UEFI firmware.
1910 However, even with this option, the resultant kernel should
1911 continue to boot on existing non-UEFI platforms.
1915 config SYSVIPC_COMPAT
1917 depends on COMPAT && SYSVIPC
1919 config ARCH_ENABLE_HUGEPAGE_MIGRATION
1921 depends on HUGETLB_PAGE && MIGRATION
1923 config ARCH_ENABLE_THP_MIGRATION
1925 depends on TRANSPARENT_HUGEPAGE
1927 menu "Power management options"
1929 source "kernel/power/Kconfig"
1931 config ARCH_HIBERNATION_POSSIBLE
1935 config ARCH_HIBERNATION_HEADER
1937 depends on HIBERNATION
1939 config ARCH_SUSPEND_POSSIBLE
1944 menu "CPU Power Management"
1946 source "drivers/cpuidle/Kconfig"
1948 source "drivers/cpufreq/Kconfig"
1952 source "drivers/firmware/Kconfig"
1954 source "drivers/acpi/Kconfig"
1956 source "arch/arm64/kvm/Kconfig"
1959 source "arch/arm64/crypto/Kconfig"