1 # SPDX-License-Identifier: GPL-2.0-only
4 select ACPI_CCA_REQUIRED if ACPI
5 select ACPI_GENERIC_GSI if ACPI
6 select ACPI_GTDT if ACPI
7 select ACPI_IORT if ACPI
8 select ACPI_REDUCED_HARDWARE_ONLY if ACPI
9 select ACPI_MCFG if (ACPI && PCI)
10 select ACPI_SPCR_TABLE if ACPI
11 select ACPI_PPTT if ACPI
12 select ARCH_HAS_DEBUG_WX
13 select ARCH_BINFMT_ELF_EXTRA_PHDRS
14 select ARCH_BINFMT_ELF_STATE
15 select ARCH_CORRECT_STACKTRACE_ON_KRETPROBE
16 select ARCH_ENABLE_HUGEPAGE_MIGRATION if HUGETLB_PAGE && MIGRATION
17 select ARCH_ENABLE_MEMORY_HOTPLUG
18 select ARCH_ENABLE_MEMORY_HOTREMOVE
19 select ARCH_ENABLE_SPLIT_PMD_PTLOCK if PGTABLE_LEVELS > 2
20 select ARCH_ENABLE_THP_MIGRATION if TRANSPARENT_HUGEPAGE
21 select ARCH_HAS_CACHE_LINE_SIZE
22 select ARCH_HAS_CURRENT_STACK_POINTER
23 select ARCH_HAS_DEBUG_VIRTUAL
24 select ARCH_HAS_DEBUG_VM_PGTABLE
25 select ARCH_HAS_DMA_PREP_COHERENT
26 select ARCH_HAS_ACPI_TABLE_UPGRADE if ACPI
27 select ARCH_HAS_FAST_MULTIPLIER
28 select ARCH_HAS_FORTIFY_SOURCE
29 select ARCH_HAS_GCOV_PROFILE_ALL
30 select ARCH_HAS_GIGANTIC_PAGE
32 select ARCH_HAS_KEEPINITRD
33 select ARCH_HAS_MEMBARRIER_SYNC_CORE
34 select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE
35 select ARCH_HAS_PTE_DEVMAP
36 select ARCH_HAS_PTE_SPECIAL
37 select ARCH_HAS_SETUP_DMA_OPS
38 select ARCH_HAS_SET_DIRECT_MAP
39 select ARCH_HAS_SET_MEMORY
41 select ARCH_HAS_STRICT_KERNEL_RWX
42 select ARCH_HAS_STRICT_MODULE_RWX
43 select ARCH_HAS_SYNC_DMA_FOR_DEVICE
44 select ARCH_HAS_SYNC_DMA_FOR_CPU
45 select ARCH_HAS_SYSCALL_WRAPPER
46 select ARCH_HAS_TEARDOWN_DMA_OPS if IOMMU_SUPPORT
47 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
48 select ARCH_HAS_VM_GET_PAGE_PROT
49 select ARCH_HAS_ZONE_DMA_SET if EXPERT
50 select ARCH_HAVE_ELF_PROT
51 select ARCH_HAVE_NMI_SAFE_CMPXCHG
52 select ARCH_INLINE_READ_LOCK if !PREEMPTION
53 select ARCH_INLINE_READ_LOCK_BH if !PREEMPTION
54 select ARCH_INLINE_READ_LOCK_IRQ if !PREEMPTION
55 select ARCH_INLINE_READ_LOCK_IRQSAVE if !PREEMPTION
56 select ARCH_INLINE_READ_UNLOCK if !PREEMPTION
57 select ARCH_INLINE_READ_UNLOCK_BH if !PREEMPTION
58 select ARCH_INLINE_READ_UNLOCK_IRQ if !PREEMPTION
59 select ARCH_INLINE_READ_UNLOCK_IRQRESTORE if !PREEMPTION
60 select ARCH_INLINE_WRITE_LOCK if !PREEMPTION
61 select ARCH_INLINE_WRITE_LOCK_BH if !PREEMPTION
62 select ARCH_INLINE_WRITE_LOCK_IRQ if !PREEMPTION
63 select ARCH_INLINE_WRITE_LOCK_IRQSAVE if !PREEMPTION
64 select ARCH_INLINE_WRITE_UNLOCK if !PREEMPTION
65 select ARCH_INLINE_WRITE_UNLOCK_BH if !PREEMPTION
66 select ARCH_INLINE_WRITE_UNLOCK_IRQ if !PREEMPTION
67 select ARCH_INLINE_WRITE_UNLOCK_IRQRESTORE if !PREEMPTION
68 select ARCH_INLINE_SPIN_TRYLOCK if !PREEMPTION
69 select ARCH_INLINE_SPIN_TRYLOCK_BH if !PREEMPTION
70 select ARCH_INLINE_SPIN_LOCK if !PREEMPTION
71 select ARCH_INLINE_SPIN_LOCK_BH if !PREEMPTION
72 select ARCH_INLINE_SPIN_LOCK_IRQ if !PREEMPTION
73 select ARCH_INLINE_SPIN_LOCK_IRQSAVE if !PREEMPTION
74 select ARCH_INLINE_SPIN_UNLOCK if !PREEMPTION
75 select ARCH_INLINE_SPIN_UNLOCK_BH if !PREEMPTION
76 select ARCH_INLINE_SPIN_UNLOCK_IRQ if !PREEMPTION
77 select ARCH_INLINE_SPIN_UNLOCK_IRQRESTORE if !PREEMPTION
78 select ARCH_KEEP_MEMBLOCK
79 select ARCH_USE_CMPXCHG_LOCKREF
80 select ARCH_USE_GNU_PROPERTY
81 select ARCH_USE_MEMTEST
82 select ARCH_USE_QUEUED_RWLOCKS
83 select ARCH_USE_QUEUED_SPINLOCKS
84 select ARCH_USE_SYM_ANNOTATIONS
85 select ARCH_SUPPORTS_DEBUG_PAGEALLOC
86 select ARCH_SUPPORTS_HUGETLBFS
87 select ARCH_SUPPORTS_MEMORY_FAILURE
88 select ARCH_SUPPORTS_SHADOW_CALL_STACK if CC_HAVE_SHADOW_CALL_STACK
89 select ARCH_SUPPORTS_LTO_CLANG if CPU_LITTLE_ENDIAN
90 select ARCH_SUPPORTS_LTO_CLANG_THIN
91 select ARCH_SUPPORTS_CFI_CLANG
92 select ARCH_SUPPORTS_ATOMIC_RMW
93 select ARCH_SUPPORTS_INT128 if CC_HAS_INT128
94 select ARCH_SUPPORTS_NUMA_BALANCING
95 select ARCH_SUPPORTS_PAGE_TABLE_CHECK
96 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION if COMPAT
97 select ARCH_WANT_DEFAULT_BPF_JIT
98 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT
99 select ARCH_WANT_FRAME_POINTERS
100 select ARCH_WANT_HUGE_PMD_SHARE if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36)
101 select ARCH_WANT_HUGETLB_PAGE_OPTIMIZE_VMEMMAP
102 select ARCH_WANT_LD_ORPHAN_WARN
103 select ARCH_WANTS_NO_INSTR
104 select ARCH_HAS_UBSAN_SANITIZE_ALL
106 select ARM_ARCH_TIMER
108 select AUDIT_ARCH_COMPAT_GENERIC
109 select ARM_GIC_V2M if PCI
111 select ARM_GIC_V3_ITS if PCI
113 select BUILDTIME_TABLE_SORT
114 select CLONE_BACKWARDS
116 select CPU_PM if (SUSPEND || CPU_IDLE)
118 select DCACHE_WORD_ACCESS
119 select DMA_DIRECT_REMAP
122 select GENERIC_ALLOCATOR
123 select GENERIC_ARCH_TOPOLOGY
124 select GENERIC_CLOCKEVENTS_BROADCAST
125 select GENERIC_CPU_AUTOPROBE
126 select GENERIC_CPU_VULNERABILITIES
127 select GENERIC_EARLY_IOREMAP
128 select GENERIC_IDLE_POLL_SETUP
129 select GENERIC_IOREMAP
130 select GENERIC_IRQ_IPI
131 select GENERIC_IRQ_PROBE
132 select GENERIC_IRQ_SHOW
133 select GENERIC_IRQ_SHOW_LEVEL
134 select GENERIC_LIB_DEVMEM_IS_ALLOWED
135 select GENERIC_PCI_IOMAP
136 select GENERIC_PTDUMP
137 select GENERIC_SCHED_CLOCK
138 select GENERIC_SMP_IDLE_THREAD
139 select GENERIC_TIME_VSYSCALL
140 select GENERIC_GETTIMEOFDAY
141 select GENERIC_VDSO_TIME_NS
142 select HARDIRQS_SW_RESEND
146 select HAVE_ACPI_APEI if (ACPI && EFI)
147 select HAVE_ALIGNED_STRUCT_PAGE if SLUB
148 select HAVE_ARCH_AUDITSYSCALL
149 select HAVE_ARCH_BITREVERSE
150 select HAVE_ARCH_COMPILER_H
151 select HAVE_ARCH_HUGE_VMAP
152 select HAVE_ARCH_JUMP_LABEL
153 select HAVE_ARCH_JUMP_LABEL_RELATIVE
154 select HAVE_ARCH_KASAN if !(ARM64_16K_PAGES && ARM64_VA_BITS_48)
155 select HAVE_ARCH_KASAN_VMALLOC if HAVE_ARCH_KASAN
156 select HAVE_ARCH_KASAN_SW_TAGS if HAVE_ARCH_KASAN
157 select HAVE_ARCH_KASAN_HW_TAGS if (HAVE_ARCH_KASAN && ARM64_MTE)
158 # Some instrumentation may be unsound, hence EXPERT
159 select HAVE_ARCH_KCSAN if EXPERT
160 select HAVE_ARCH_KFENCE
161 select HAVE_ARCH_KGDB
162 select HAVE_ARCH_MMAP_RND_BITS
163 select HAVE_ARCH_MMAP_RND_COMPAT_BITS if COMPAT
164 select HAVE_ARCH_PREL32_RELOCATIONS
165 select HAVE_ARCH_RANDOMIZE_KSTACK_OFFSET
166 select HAVE_ARCH_SECCOMP_FILTER
167 select HAVE_ARCH_STACKLEAK
168 select HAVE_ARCH_THREAD_STRUCT_WHITELIST
169 select HAVE_ARCH_TRACEHOOK
170 select HAVE_ARCH_TRANSPARENT_HUGEPAGE
171 select HAVE_ARCH_VMAP_STACK
172 select HAVE_ARM_SMCCC
173 select HAVE_ASM_MODVERSIONS
175 select HAVE_C_RECORDMCOUNT
176 select HAVE_CMPXCHG_DOUBLE
177 select HAVE_CMPXCHG_LOCAL
178 select HAVE_CONTEXT_TRACKING
179 select HAVE_DEBUG_KMEMLEAK
180 select HAVE_DMA_CONTIGUOUS
181 select HAVE_DYNAMIC_FTRACE
182 select FTRACE_MCOUNT_USE_PATCHABLE_FUNCTION_ENTRY \
183 if DYNAMIC_FTRACE_WITH_REGS
184 select HAVE_EFFICIENT_UNALIGNED_ACCESS
186 select HAVE_FTRACE_MCOUNT_RECORD
187 select HAVE_FUNCTION_TRACER
188 select HAVE_FUNCTION_ERROR_INJECTION
189 select HAVE_FUNCTION_GRAPH_TRACER
190 select HAVE_GCC_PLUGINS
191 select HAVE_HW_BREAKPOINT if PERF_EVENTS
192 select HAVE_IRQ_TIME_ACCOUNTING
195 select HAVE_PATA_PLATFORM
196 select HAVE_PERF_EVENTS
197 select HAVE_PERF_REGS
198 select HAVE_PERF_USER_STACK_DUMP
199 select HAVE_PREEMPT_DYNAMIC_KEY
200 select HAVE_REGS_AND_STACK_ACCESS_API
201 select HAVE_POSIX_CPU_TIMERS_TASK_WORK
202 select HAVE_FUNCTION_ARG_ACCESS_API
203 select MMU_GATHER_RCU_TABLE_FREE
205 select HAVE_STACKPROTECTOR
206 select HAVE_SYSCALL_TRACEPOINTS
208 select HAVE_KRETPROBES
209 select HAVE_GENERIC_VDSO
210 select IOMMU_DMA if IOMMU_SUPPORT
212 select IRQ_FORCED_THREADING
213 select KASAN_VMALLOC if KASAN
214 select MODULES_USE_ELF_RELA
215 select NEED_DMA_MAP_STATE
216 select NEED_SG_DMA_LENGTH
218 select OF_EARLY_FLATTREE
219 select PCI_DOMAINS_GENERIC if PCI
220 select PCI_ECAM if (ACPI && PCI)
221 select PCI_SYSCALL if PCI
226 select SYSCTL_EXCEPTION_TRACE
227 select THREAD_INFO_IN_TASK
228 select HAVE_ARCH_USERFAULTFD_MINOR if USERFAULTFD
229 select TRACE_IRQFLAGS_SUPPORT
231 ARM 64-bit (AArch64) Linux support.
233 config CLANG_SUPPORTS_DYNAMIC_FTRACE_WITH_REGS
235 # https://github.com/ClangBuiltLinux/linux/issues/1507
236 depends on AS_IS_GNU || (AS_IS_LLVM && (LD_IS_LLD || LD_VERSION >= 23600))
237 select HAVE_DYNAMIC_FTRACE_WITH_REGS
239 config GCC_SUPPORTS_DYNAMIC_FTRACE_WITH_REGS
241 depends on $(cc-option,-fpatchable-function-entry=2)
242 select HAVE_DYNAMIC_FTRACE_WITH_REGS
250 config ARM64_PAGE_SHIFT
252 default 16 if ARM64_64K_PAGES
253 default 14 if ARM64_16K_PAGES
256 config ARM64_CONT_PTE_SHIFT
258 default 5 if ARM64_64K_PAGES
259 default 7 if ARM64_16K_PAGES
262 config ARM64_CONT_PMD_SHIFT
264 default 5 if ARM64_64K_PAGES
265 default 5 if ARM64_16K_PAGES
268 config ARCH_MMAP_RND_BITS_MIN
269 default 14 if ARM64_64K_PAGES
270 default 16 if ARM64_16K_PAGES
273 # max bits determined by the following formula:
274 # VA_BITS - PAGE_SHIFT - 3
275 config ARCH_MMAP_RND_BITS_MAX
276 default 19 if ARM64_VA_BITS=36
277 default 24 if ARM64_VA_BITS=39
278 default 27 if ARM64_VA_BITS=42
279 default 30 if ARM64_VA_BITS=47
280 default 29 if ARM64_VA_BITS=48 && ARM64_64K_PAGES
281 default 31 if ARM64_VA_BITS=48 && ARM64_16K_PAGES
282 default 33 if ARM64_VA_BITS=48
283 default 14 if ARM64_64K_PAGES
284 default 16 if ARM64_16K_PAGES
287 config ARCH_MMAP_RND_COMPAT_BITS_MIN
288 default 7 if ARM64_64K_PAGES
289 default 9 if ARM64_16K_PAGES
292 config ARCH_MMAP_RND_COMPAT_BITS_MAX
298 config STACKTRACE_SUPPORT
301 config ILLEGAL_POINTER_VALUE
303 default 0xdead000000000000
305 config LOCKDEP_SUPPORT
312 config GENERIC_BUG_RELATIVE_POINTERS
314 depends on GENERIC_BUG
316 config GENERIC_HWEIGHT
322 config GENERIC_CALIBRATE_DELAY
325 config ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE
331 config KERNEL_MODE_NEON
334 config FIX_EARLYCON_MEM
337 config PGTABLE_LEVELS
339 default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36
340 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42
341 default 3 if ARM64_64K_PAGES && (ARM64_VA_BITS_48 || ARM64_VA_BITS_52)
342 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39
343 default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47
344 default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48
346 config ARCH_SUPPORTS_UPROBES
349 config ARCH_PROC_KCORE_TEXT
352 config BROKEN_GAS_INST
353 def_bool !$(as-instr,1:\n.inst 0\n.rept . - 1b\n\nnop\n.endr\n)
355 config KASAN_SHADOW_OFFSET
357 depends on KASAN_GENERIC || KASAN_SW_TAGS
358 default 0xdfff800000000000 if (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) && !KASAN_SW_TAGS
359 default 0xdfffc00000000000 if ARM64_VA_BITS_47 && !KASAN_SW_TAGS
360 default 0xdffffe0000000000 if ARM64_VA_BITS_42 && !KASAN_SW_TAGS
361 default 0xdfffffc000000000 if ARM64_VA_BITS_39 && !KASAN_SW_TAGS
362 default 0xdffffff800000000 if ARM64_VA_BITS_36 && !KASAN_SW_TAGS
363 default 0xefff800000000000 if (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) && KASAN_SW_TAGS
364 default 0xefffc00000000000 if ARM64_VA_BITS_47 && KASAN_SW_TAGS
365 default 0xeffffe0000000000 if ARM64_VA_BITS_42 && KASAN_SW_TAGS
366 default 0xefffffc000000000 if ARM64_VA_BITS_39 && KASAN_SW_TAGS
367 default 0xeffffff800000000 if ARM64_VA_BITS_36 && KASAN_SW_TAGS
368 default 0xffffffffffffffff
370 source "arch/arm64/Kconfig.platforms"
372 menu "Kernel Features"
374 menu "ARM errata workarounds via the alternatives framework"
376 config ARM64_WORKAROUND_CLEAN_CACHE
379 config ARM64_ERRATUM_826319
380 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"
382 select ARM64_WORKAROUND_CLEAN_CACHE
384 This option adds an alternative code sequence to work around ARM
385 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
386 AXI master interface and an L2 cache.
388 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
389 and is unable to accept a certain write via this interface, it will
390 not progress on read data presented on the read data channel and the
393 The workaround promotes data cache clean instructions to
394 data cache clean-and-invalidate.
395 Please note that this does not necessarily enable the workaround,
396 as it depends on the alternative framework, which will only patch
397 the kernel if an affected CPU is detected.
401 config ARM64_ERRATUM_827319
402 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
404 select ARM64_WORKAROUND_CLEAN_CACHE
406 This option adds an alternative code sequence to work around ARM
407 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
408 master interface and an L2 cache.
410 Under certain conditions this erratum can cause a clean line eviction
411 to occur at the same time as another transaction to the same address
412 on the AMBA 5 CHI interface, which can cause data corruption if the
413 interconnect reorders the two transactions.
415 The workaround promotes data cache clean instructions to
416 data cache clean-and-invalidate.
417 Please note that this does not necessarily enable the workaround,
418 as it depends on the alternative framework, which will only patch
419 the kernel if an affected CPU is detected.
423 config ARM64_ERRATUM_824069
424 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
426 select ARM64_WORKAROUND_CLEAN_CACHE
428 This option adds an alternative code sequence to work around ARM
429 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
430 to a coherent interconnect.
432 If a Cortex-A53 processor is executing a store or prefetch for
433 write instruction at the same time as a processor in another
434 cluster is executing a cache maintenance operation to the same
435 address, then this erratum might cause a clean cache line to be
436 incorrectly marked as dirty.
438 The workaround promotes data cache clean instructions to
439 data cache clean-and-invalidate.
440 Please note that this option does not necessarily enable the
441 workaround, as it depends on the alternative framework, which will
442 only patch the kernel if an affected CPU is detected.
446 config ARM64_ERRATUM_819472
447 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
449 select ARM64_WORKAROUND_CLEAN_CACHE
451 This option adds an alternative code sequence to work around ARM
452 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
453 present when it is connected to a coherent interconnect.
455 If the processor is executing a load and store exclusive sequence at
456 the same time as a processor in another cluster is executing a cache
457 maintenance operation to the same address, then this erratum might
458 cause data corruption.
460 The workaround promotes data cache clean instructions to
461 data cache clean-and-invalidate.
462 Please note that this does not necessarily enable the workaround,
463 as it depends on the alternative framework, which will only patch
464 the kernel if an affected CPU is detected.
468 config ARM64_ERRATUM_832075
469 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
472 This option adds an alternative code sequence to work around ARM
473 erratum 832075 on Cortex-A57 parts up to r1p2.
475 Affected Cortex-A57 parts might deadlock when exclusive load/store
476 instructions to Write-Back memory are mixed with Device loads.
478 The workaround is to promote device loads to use Load-Acquire
480 Please note that this does not necessarily enable the workaround,
481 as it depends on the alternative framework, which will only patch
482 the kernel if an affected CPU is detected.
486 config ARM64_ERRATUM_834220
487 bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault"
491 This option adds an alternative code sequence to work around ARM
492 erratum 834220 on Cortex-A57 parts up to r1p2.
494 Affected Cortex-A57 parts might report a Stage 2 translation
495 fault as the result of a Stage 1 fault for load crossing a
496 page boundary when there is a permission or device memory
497 alignment fault at Stage 1 and a translation fault at Stage 2.
499 The workaround is to verify that the Stage 1 translation
500 doesn't generate a fault before handling the Stage 2 fault.
501 Please note that this does not necessarily enable the workaround,
502 as it depends on the alternative framework, which will only patch
503 the kernel if an affected CPU is detected.
507 config ARM64_ERRATUM_845719
508 bool "Cortex-A53: 845719: a load might read incorrect data"
512 This option adds an alternative code sequence to work around ARM
513 erratum 845719 on Cortex-A53 parts up to r0p4.
515 When running a compat (AArch32) userspace on an affected Cortex-A53
516 part, a load at EL0 from a virtual address that matches the bottom 32
517 bits of the virtual address used by a recent load at (AArch64) EL1
518 might return incorrect data.
520 The workaround is to write the contextidr_el1 register on exception
521 return to a 32-bit task.
522 Please note that this does not necessarily enable the workaround,
523 as it depends on the alternative framework, which will only patch
524 the kernel if an affected CPU is detected.
528 config ARM64_ERRATUM_843419
529 bool "Cortex-A53: 843419: A load or store might access an incorrect address"
531 select ARM64_MODULE_PLTS if MODULES
533 This option links the kernel with '--fix-cortex-a53-843419' and
534 enables PLT support to replace certain ADRP instructions, which can
535 cause subsequent memory accesses to use an incorrect address on
536 Cortex-A53 parts up to r0p4.
540 config ARM64_LD_HAS_FIX_ERRATUM_843419
541 def_bool $(ld-option,--fix-cortex-a53-843419)
543 config ARM64_ERRATUM_1024718
544 bool "Cortex-A55: 1024718: Update of DBM/AP bits without break before make might result in incorrect update"
547 This option adds a workaround for ARM Cortex-A55 Erratum 1024718.
549 Affected Cortex-A55 cores (all revisions) could cause incorrect
550 update of the hardware dirty bit when the DBM/AP bits are updated
551 without a break-before-make. The workaround is to disable the usage
552 of hardware DBM locally on the affected cores. CPUs not affected by
553 this erratum will continue to use the feature.
557 config ARM64_ERRATUM_1418040
558 bool "Cortex-A76/Neoverse-N1: MRC read following MRRC read of specific Generic Timer in AArch32 might give incorrect result"
562 This option adds a workaround for ARM Cortex-A76/Neoverse-N1
563 errata 1188873 and 1418040.
565 Affected Cortex-A76/Neoverse-N1 cores (r0p0 to r3p1) could
566 cause register corruption when accessing the timer registers
567 from AArch32 userspace.
571 config ARM64_WORKAROUND_SPECULATIVE_AT
574 config ARM64_ERRATUM_1165522
575 bool "Cortex-A76: 1165522: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"
577 select ARM64_WORKAROUND_SPECULATIVE_AT
579 This option adds a workaround for ARM Cortex-A76 erratum 1165522.
581 Affected Cortex-A76 cores (r0p0, r1p0, r2p0) could end-up with
582 corrupted TLBs by speculating an AT instruction during a guest
587 config ARM64_ERRATUM_1319367
588 bool "Cortex-A57/A72: 1319537: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"
590 select ARM64_WORKAROUND_SPECULATIVE_AT
592 This option adds work arounds for ARM Cortex-A57 erratum 1319537
593 and A72 erratum 1319367
595 Cortex-A57 and A72 cores could end-up with corrupted TLBs by
596 speculating an AT instruction during a guest context switch.
600 config ARM64_ERRATUM_1530923
601 bool "Cortex-A55: 1530923: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"
603 select ARM64_WORKAROUND_SPECULATIVE_AT
605 This option adds a workaround for ARM Cortex-A55 erratum 1530923.
607 Affected Cortex-A55 cores (r0p0, r0p1, r1p0, r2p0) could end-up with
608 corrupted TLBs by speculating an AT instruction during a guest
613 config ARM64_WORKAROUND_REPEAT_TLBI
616 config ARM64_ERRATUM_1286807
617 bool "Cortex-A76: Modification of the translation table for a virtual address might lead to read-after-read ordering violation"
619 select ARM64_WORKAROUND_REPEAT_TLBI
621 This option adds a workaround for ARM Cortex-A76 erratum 1286807.
623 On the affected Cortex-A76 cores (r0p0 to r3p0), if a virtual
624 address for a cacheable mapping of a location is being
625 accessed by a core while another core is remapping the virtual
626 address to a new physical page using the recommended
627 break-before-make sequence, then under very rare circumstances
628 TLBI+DSB completes before a read using the translation being
629 invalidated has been observed by other observers. The
630 workaround repeats the TLBI+DSB operation.
632 config ARM64_ERRATUM_1463225
633 bool "Cortex-A76: Software Step might prevent interrupt recognition"
636 This option adds a workaround for Arm Cortex-A76 erratum 1463225.
638 On the affected Cortex-A76 cores (r0p0 to r3p1), software stepping
639 of a system call instruction (SVC) can prevent recognition of
640 subsequent interrupts when software stepping is disabled in the
641 exception handler of the system call and either kernel debugging
642 is enabled or VHE is in use.
644 Work around the erratum by triggering a dummy step exception
645 when handling a system call from a task that is being stepped
646 in a VHE configuration of the kernel.
650 config ARM64_ERRATUM_1542419
651 bool "Neoverse-N1: workaround mis-ordering of instruction fetches"
654 This option adds a workaround for ARM Neoverse-N1 erratum
657 Affected Neoverse-N1 cores could execute a stale instruction when
658 modified by another CPU. The workaround depends on a firmware
661 Workaround the issue by hiding the DIC feature from EL0. This
662 forces user-space to perform cache maintenance.
666 config ARM64_ERRATUM_1508412
667 bool "Cortex-A77: 1508412: workaround deadlock on sequence of NC/Device load and store exclusive or PAR read"
670 This option adds a workaround for Arm Cortex-A77 erratum 1508412.
672 Affected Cortex-A77 cores (r0p0, r1p0) could deadlock on a sequence
673 of a store-exclusive or read of PAR_EL1 and a load with device or
674 non-cacheable memory attributes. The workaround depends on a firmware
677 KVM guests must also have the workaround implemented or they can
680 Work around the issue by inserting DMB SY barriers around PAR_EL1
681 register reads and warning KVM users. The DMB barrier is sufficient
682 to prevent a speculative PAR_EL1 read.
686 config ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE
689 config ARM64_ERRATUM_2051678
690 bool "Cortex-A510: 2051678: disable Hardware Update of the page table dirty bit"
693 This options adds the workaround for ARM Cortex-A510 erratum ARM64_ERRATUM_2051678.
694 Affected Cortex-A510 might not respect the ordering rules for
695 hardware update of the page table's dirty bit. The workaround
696 is to not enable the feature on affected CPUs.
700 config ARM64_ERRATUM_2077057
701 bool "Cortex-A510: 2077057: workaround software-step corrupting SPSR_EL2"
704 This option adds the workaround for ARM Cortex-A510 erratum 2077057.
705 Affected Cortex-A510 may corrupt SPSR_EL2 when the a step exception is
706 expected, but a Pointer Authentication trap is taken instead. The
707 erratum causes SPSR_EL1 to be copied to SPSR_EL2, which could allow
708 EL1 to cause a return to EL2 with a guest controlled ELR_EL2.
710 This can only happen when EL2 is stepping EL1.
712 When these conditions occur, the SPSR_EL2 value is unchanged from the
713 previous guest entry, and can be restored from the in-memory copy.
717 config ARM64_ERRATUM_2119858
718 bool "Cortex-A710/X2: 2119858: workaround TRBE overwriting trace data in FILL mode"
720 depends on CORESIGHT_TRBE
721 select ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE
723 This option adds the workaround for ARM Cortex-A710/X2 erratum 2119858.
725 Affected Cortex-A710/X2 cores could overwrite up to 3 cache lines of trace
726 data at the base of the buffer (pointed to by TRBASER_EL1) in FILL mode in
727 the event of a WRAP event.
729 Work around the issue by always making sure we move the TRBPTR_EL1 by
730 256 bytes before enabling the buffer and filling the first 256 bytes of
731 the buffer with ETM ignore packets upon disabling.
735 config ARM64_ERRATUM_2139208
736 bool "Neoverse-N2: 2139208: workaround TRBE overwriting trace data in FILL mode"
738 depends on CORESIGHT_TRBE
739 select ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE
741 This option adds the workaround for ARM Neoverse-N2 erratum 2139208.
743 Affected Neoverse-N2 cores could overwrite up to 3 cache lines of trace
744 data at the base of the buffer (pointed to by TRBASER_EL1) in FILL mode in
745 the event of a WRAP event.
747 Work around the issue by always making sure we move the TRBPTR_EL1 by
748 256 bytes before enabling the buffer and filling the first 256 bytes of
749 the buffer with ETM ignore packets upon disabling.
753 config ARM64_WORKAROUND_TSB_FLUSH_FAILURE
756 config ARM64_ERRATUM_2054223
757 bool "Cortex-A710: 2054223: workaround TSB instruction failing to flush trace"
759 select ARM64_WORKAROUND_TSB_FLUSH_FAILURE
761 Enable workaround for ARM Cortex-A710 erratum 2054223
763 Affected cores may fail to flush the trace data on a TSB instruction, when
764 the PE is in trace prohibited state. This will cause losing a few bytes
767 Workaround is to issue two TSB consecutively on affected cores.
771 config ARM64_ERRATUM_2067961
772 bool "Neoverse-N2: 2067961: workaround TSB instruction failing to flush trace"
774 select ARM64_WORKAROUND_TSB_FLUSH_FAILURE
776 Enable workaround for ARM Neoverse-N2 erratum 2067961
778 Affected cores may fail to flush the trace data on a TSB instruction, when
779 the PE is in trace prohibited state. This will cause losing a few bytes
782 Workaround is to issue two TSB consecutively on affected cores.
786 config ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE
789 config ARM64_ERRATUM_2253138
790 bool "Neoverse-N2: 2253138: workaround TRBE writing to address out-of-range"
791 depends on CORESIGHT_TRBE
793 select ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE
795 This option adds the workaround for ARM Neoverse-N2 erratum 2253138.
797 Affected Neoverse-N2 cores might write to an out-of-range address, not reserved
798 for TRBE. Under some conditions, the TRBE might generate a write to the next
799 virtually addressed page following the last page of the TRBE address space
800 (i.e., the TRBLIMITR_EL1.LIMIT), instead of wrapping around to the base.
802 Work around this in the driver by always making sure that there is a
803 page beyond the TRBLIMITR_EL1.LIMIT, within the space allowed for the TRBE.
807 config ARM64_ERRATUM_2224489
808 bool "Cortex-A710/X2: 2224489: workaround TRBE writing to address out-of-range"
809 depends on CORESIGHT_TRBE
811 select ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE
813 This option adds the workaround for ARM Cortex-A710/X2 erratum 2224489.
815 Affected Cortex-A710/X2 cores might write to an out-of-range address, not reserved
816 for TRBE. Under some conditions, the TRBE might generate a write to the next
817 virtually addressed page following the last page of the TRBE address space
818 (i.e., the TRBLIMITR_EL1.LIMIT), instead of wrapping around to the base.
820 Work around this in the driver by always making sure that there is a
821 page beyond the TRBLIMITR_EL1.LIMIT, within the space allowed for the TRBE.
825 config ARM64_ERRATUM_2064142
826 bool "Cortex-A510: 2064142: workaround TRBE register writes while disabled"
827 depends on CORESIGHT_TRBE
830 This option adds the workaround for ARM Cortex-A510 erratum 2064142.
832 Affected Cortex-A510 core might fail to write into system registers after the
833 TRBE has been disabled. Under some conditions after the TRBE has been disabled
834 writes into TRBE registers TRBLIMITR_EL1, TRBPTR_EL1, TRBBASER_EL1, TRBSR_EL1,
835 and TRBTRG_EL1 will be ignored and will not be effected.
837 Work around this in the driver by executing TSB CSYNC and DSB after collection
838 is stopped and before performing a system register write to one of the affected
843 config ARM64_ERRATUM_2038923
844 bool "Cortex-A510: 2038923: workaround TRBE corruption with enable"
845 depends on CORESIGHT_TRBE
848 This option adds the workaround for ARM Cortex-A510 erratum 2038923.
850 Affected Cortex-A510 core might cause an inconsistent view on whether trace is
851 prohibited within the CPU. As a result, the trace buffer or trace buffer state
852 might be corrupted. This happens after TRBE buffer has been enabled by setting
853 TRBLIMITR_EL1.E, followed by just a single context synchronization event before
854 execution changes from a context, in which trace is prohibited to one where it
855 isn't, or vice versa. In these mentioned conditions, the view of whether trace
856 is prohibited is inconsistent between parts of the CPU, and the trace buffer or
857 the trace buffer state might be corrupted.
859 Work around this in the driver by preventing an inconsistent view of whether the
860 trace is prohibited or not based on TRBLIMITR_EL1.E by immediately following a
861 change to TRBLIMITR_EL1.E with at least one ISB instruction before an ERET, or
862 two ISB instructions if no ERET is to take place.
866 config ARM64_ERRATUM_1902691
867 bool "Cortex-A510: 1902691: workaround TRBE trace corruption"
868 depends on CORESIGHT_TRBE
871 This option adds the workaround for ARM Cortex-A510 erratum 1902691.
873 Affected Cortex-A510 core might cause trace data corruption, when being written
874 into the memory. Effectively TRBE is broken and hence cannot be used to capture
877 Work around this problem in the driver by just preventing TRBE initialization on
878 affected cpus. The firmware must have disabled the access to TRBE for the kernel
879 on such implementations. This will cover the kernel for any firmware that doesn't
884 config CAVIUM_ERRATUM_22375
885 bool "Cavium erratum 22375, 24313"
888 Enable workaround for errata 22375 and 24313.
890 This implements two gicv3-its errata workarounds for ThunderX. Both
891 with a small impact affecting only ITS table allocation.
893 erratum 22375: only alloc 8MB table size
894 erratum 24313: ignore memory access type
896 The fixes are in ITS initialization and basically ignore memory access
897 type and table size provided by the TYPER and BASER registers.
901 config CAVIUM_ERRATUM_23144
902 bool "Cavium erratum 23144: ITS SYNC hang on dual socket system"
906 ITS SYNC command hang for cross node io and collections/cpu mapping.
910 config CAVIUM_ERRATUM_23154
911 bool "Cavium errata 23154 and 38545: GICv3 lacks HW synchronisation"
914 The ThunderX GICv3 implementation requires a modified version for
915 reading the IAR status to ensure data synchronization
916 (access to icc_iar1_el1 is not sync'ed before and after).
918 It also suffers from erratum 38545 (also present on Marvell's
919 OcteonTX and OcteonTX2), resulting in deactivated interrupts being
920 spuriously presented to the CPU interface.
924 config CAVIUM_ERRATUM_27456
925 bool "Cavium erratum 27456: Broadcast TLBI instructions may cause icache corruption"
928 On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI
929 instructions may cause the icache to become corrupted if it
930 contains data for a non-current ASID. The fix is to
931 invalidate the icache when changing the mm context.
935 config CAVIUM_ERRATUM_30115
936 bool "Cavium erratum 30115: Guest may disable interrupts in host"
939 On ThunderX T88 pass 1.x through 2.2, T81 pass 1.0 through
940 1.2, and T83 Pass 1.0, KVM guest execution may disable
941 interrupts in host. Trapping both GICv3 group-0 and group-1
942 accesses sidesteps the issue.
946 config CAVIUM_TX2_ERRATUM_219
947 bool "Cavium ThunderX2 erratum 219: PRFM between TTBR change and ISB fails"
950 On Cavium ThunderX2, a load, store or prefetch instruction between a
951 TTBR update and the corresponding context synchronizing operation can
952 cause a spurious Data Abort to be delivered to any hardware thread in
955 Work around the issue by avoiding the problematic code sequence and
956 trapping KVM guest TTBRx_EL1 writes to EL2 when SMT is enabled. The
957 trap handler performs the corresponding register access, skips the
958 instruction and ensures context synchronization by virtue of the
963 config FUJITSU_ERRATUM_010001
964 bool "Fujitsu-A64FX erratum E#010001: Undefined fault may occur wrongly"
967 This option adds a workaround for Fujitsu-A64FX erratum E#010001.
968 On some variants of the Fujitsu-A64FX cores ver(1.0, 1.1), memory
969 accesses may cause undefined fault (Data abort, DFSC=0b111111).
970 This fault occurs under a specific hardware condition when a
971 load/store instruction performs an address translation using:
972 case-1 TTBR0_EL1 with TCR_EL1.NFD0 == 1.
973 case-2 TTBR0_EL2 with TCR_EL2.NFD0 == 1.
974 case-3 TTBR1_EL1 with TCR_EL1.NFD1 == 1.
975 case-4 TTBR1_EL2 with TCR_EL2.NFD1 == 1.
977 The workaround is to ensure these bits are clear in TCR_ELx.
978 The workaround only affects the Fujitsu-A64FX.
982 config HISILICON_ERRATUM_161600802
983 bool "Hip07 161600802: Erroneous redistributor VLPI base"
986 The HiSilicon Hip07 SoC uses the wrong redistributor base
987 when issued ITS commands such as VMOVP and VMAPP, and requires
988 a 128kB offset to be applied to the target address in this commands.
992 config QCOM_FALKOR_ERRATUM_1003
993 bool "Falkor E1003: Incorrect translation due to ASID change"
996 On Falkor v1, an incorrect ASID may be cached in the TLB when ASID
997 and BADDR are changed together in TTBRx_EL1. Since we keep the ASID
998 in TTBR1_EL1, this situation only occurs in the entry trampoline and
999 then only for entries in the walk cache, since the leaf translation
1000 is unchanged. Work around the erratum by invalidating the walk cache
1001 entries for the trampoline before entering the kernel proper.
1003 config QCOM_FALKOR_ERRATUM_1009
1004 bool "Falkor E1009: Prematurely complete a DSB after a TLBI"
1006 select ARM64_WORKAROUND_REPEAT_TLBI
1008 On Falkor v1, the CPU may prematurely complete a DSB following a
1009 TLBI xxIS invalidate maintenance operation. Repeat the TLBI operation
1010 one more time to fix the issue.
1014 config QCOM_QDF2400_ERRATUM_0065
1015 bool "QDF2400 E0065: Incorrect GITS_TYPER.ITT_Entry_size"
1018 On Qualcomm Datacenter Technologies QDF2400 SoC, ITS hardware reports
1019 ITE size incorrectly. The GITS_TYPER.ITT_Entry_size field should have
1020 been indicated as 16Bytes (0xf), not 8Bytes (0x7).
1024 config QCOM_FALKOR_ERRATUM_E1041
1025 bool "Falkor E1041: Speculative instruction fetches might cause errant memory access"
1028 Falkor CPU may speculatively fetch instructions from an improper
1029 memory location when MMU translation is changed from SCTLR_ELn[M]=1
1030 to SCTLR_ELn[M]=0. Prefix an ISB instruction to fix the problem.
1034 config NVIDIA_CARMEL_CNP_ERRATUM
1035 bool "NVIDIA Carmel CNP: CNP on Carmel semantically different than ARM cores"
1038 If CNP is enabled on Carmel cores, non-sharable TLBIs on a core will not
1039 invalidate shared TLB entries installed by a different core, as it would
1040 on standard ARM cores.
1044 config SOCIONEXT_SYNQUACER_PREITS
1045 bool "Socionext Synquacer: Workaround for GICv3 pre-ITS"
1048 Socionext Synquacer SoCs implement a separate h/w block to generate
1049 MSI doorbell writes with non-zero values for the device ID.
1053 endmenu # "ARM errata workarounds via the alternatives framework"
1057 default ARM64_4K_PAGES
1059 Page size (translation granule) configuration.
1061 config ARM64_4K_PAGES
1064 This feature enables 4KB pages support.
1066 config ARM64_16K_PAGES
1069 The system will use 16KB pages support. AArch32 emulation
1070 requires applications compiled with 16K (or a multiple of 16K)
1073 config ARM64_64K_PAGES
1076 This feature enables 64KB pages support (4KB by default)
1077 allowing only two levels of page tables and faster TLB
1078 look-up. AArch32 emulation requires applications compiled
1079 with 64K aligned segments.
1084 prompt "Virtual address space size"
1085 default ARM64_VA_BITS_39 if ARM64_4K_PAGES
1086 default ARM64_VA_BITS_47 if ARM64_16K_PAGES
1087 default ARM64_VA_BITS_42 if ARM64_64K_PAGES
1089 Allows choosing one of multiple possible virtual address
1090 space sizes. The level of translation table is determined by
1091 a combination of page size and virtual address space size.
1093 config ARM64_VA_BITS_36
1094 bool "36-bit" if EXPERT
1095 depends on ARM64_16K_PAGES
1097 config ARM64_VA_BITS_39
1099 depends on ARM64_4K_PAGES
1101 config ARM64_VA_BITS_42
1103 depends on ARM64_64K_PAGES
1105 config ARM64_VA_BITS_47
1107 depends on ARM64_16K_PAGES
1109 config ARM64_VA_BITS_48
1112 config ARM64_VA_BITS_52
1114 depends on ARM64_64K_PAGES && (ARM64_PAN || !ARM64_SW_TTBR0_PAN)
1116 Enable 52-bit virtual addressing for userspace when explicitly
1117 requested via a hint to mmap(). The kernel will also use 52-bit
1118 virtual addresses for its own mappings (provided HW support for
1119 this feature is available, otherwise it reverts to 48-bit).
1121 NOTE: Enabling 52-bit virtual addressing in conjunction with
1122 ARMv8.3 Pointer Authentication will result in the PAC being
1123 reduced from 7 bits to 3 bits, which may have a significant
1124 impact on its susceptibility to brute-force attacks.
1126 If unsure, select 48-bit virtual addressing instead.
1130 config ARM64_FORCE_52BIT
1131 bool "Force 52-bit virtual addresses for userspace"
1132 depends on ARM64_VA_BITS_52 && EXPERT
1134 For systems with 52-bit userspace VAs enabled, the kernel will attempt
1135 to maintain compatibility with older software by providing 48-bit VAs
1136 unless a hint is supplied to mmap.
1138 This configuration option disables the 48-bit compatibility logic, and
1139 forces all userspace addresses to be 52-bit on HW that supports it. One
1140 should only enable this configuration option for stress testing userspace
1141 memory management code. If unsure say N here.
1143 config ARM64_VA_BITS
1145 default 36 if ARM64_VA_BITS_36
1146 default 39 if ARM64_VA_BITS_39
1147 default 42 if ARM64_VA_BITS_42
1148 default 47 if ARM64_VA_BITS_47
1149 default 48 if ARM64_VA_BITS_48
1150 default 52 if ARM64_VA_BITS_52
1153 prompt "Physical address space size"
1154 default ARM64_PA_BITS_48
1156 Choose the maximum physical address range that the kernel will
1159 config ARM64_PA_BITS_48
1162 config ARM64_PA_BITS_52
1163 bool "52-bit (ARMv8.2)"
1164 depends on ARM64_64K_PAGES
1165 depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN
1167 Enable support for a 52-bit physical address space, introduced as
1168 part of the ARMv8.2-LPA extension.
1170 With this enabled, the kernel will also continue to work on CPUs that
1171 do not support ARMv8.2-LPA, but with some added memory overhead (and
1172 minor performance overhead).
1176 config ARM64_PA_BITS
1178 default 48 if ARM64_PA_BITS_48
1179 default 52 if ARM64_PA_BITS_52
1183 default CPU_LITTLE_ENDIAN
1185 Select the endianness of data accesses performed by the CPU. Userspace
1186 applications will need to be compiled and linked for the endianness
1187 that is selected here.
1189 config CPU_BIG_ENDIAN
1190 bool "Build big-endian kernel"
1191 depends on !LD_IS_LLD || LLD_VERSION >= 130000
1193 Say Y if you plan on running a kernel with a big-endian userspace.
1195 config CPU_LITTLE_ENDIAN
1196 bool "Build little-endian kernel"
1198 Say Y if you plan on running a kernel with a little-endian userspace.
1199 This is usually the case for distributions targeting arm64.
1204 bool "Multi-core scheduler support"
1206 Multi-core scheduler support improves the CPU scheduler's decision
1207 making when dealing with multi-core CPU chips at a cost of slightly
1208 increased overhead in some places. If unsure say N here.
1210 config SCHED_CLUSTER
1211 bool "Cluster scheduler support"
1213 Cluster scheduler support improves the CPU scheduler's decision
1214 making when dealing with machines that have clusters of CPUs.
1215 Cluster usually means a couple of CPUs which are placed closely
1216 by sharing mid-level caches, last-level cache tags or internal
1220 bool "SMT scheduler support"
1222 Improves the CPU scheduler's decision making when dealing with
1223 MultiThreading at a cost of slightly increased overhead in some
1224 places. If unsure say N here.
1227 int "Maximum number of CPUs (2-4096)"
1232 bool "Support for hot-pluggable CPUs"
1233 select GENERIC_IRQ_MIGRATION
1235 Say Y here to experiment with turning CPUs off and on. CPUs
1236 can be controlled through /sys/devices/system/cpu.
1238 # Common NUMA Features
1240 bool "NUMA Memory Allocation and Scheduler Support"
1241 select GENERIC_ARCH_NUMA
1242 select ACPI_NUMA if ACPI
1244 select HAVE_SETUP_PER_CPU_AREA
1245 select NEED_PER_CPU_EMBED_FIRST_CHUNK
1246 select NEED_PER_CPU_PAGE_FIRST_CHUNK
1247 select USE_PERCPU_NUMA_NODE_ID
1249 Enable NUMA (Non-Uniform Memory Access) support.
1251 The kernel will try to allocate memory used by a CPU on the
1252 local memory of the CPU and add some more
1253 NUMA awareness to the kernel.
1256 int "Maximum NUMA Nodes (as a power of 2)"
1261 Specify the maximum number of NUMA Nodes available on the target
1262 system. Increases memory reserved to accommodate various tables.
1264 source "kernel/Kconfig.hz"
1266 config ARCH_SPARSEMEM_ENABLE
1268 select SPARSEMEM_VMEMMAP_ENABLE
1269 select SPARSEMEM_VMEMMAP
1271 config HW_PERF_EVENTS
1275 # Supported by clang >= 7.0 or GCC >= 12.0.0
1276 config CC_HAVE_SHADOW_CALL_STACK
1277 def_bool $(cc-option, -fsanitize=shadow-call-stack -ffixed-x18)
1280 bool "Enable paravirtualization code"
1282 This changes the kernel so it can modify itself when it is run
1283 under a hypervisor, potentially improving performance significantly
1284 over full virtualization.
1286 config PARAVIRT_TIME_ACCOUNTING
1287 bool "Paravirtual steal time accounting"
1290 Select this option to enable fine granularity task steal time
1291 accounting. Time spent executing other tasks in parallel with
1292 the current vCPU is discounted from the vCPU power. To account for
1293 that, there can be a small performance impact.
1295 If in doubt, say N here.
1298 depends on PM_SLEEP_SMP
1300 bool "kexec system call"
1302 kexec is a system call that implements the ability to shutdown your
1303 current kernel, and to start another kernel. It is like a reboot
1304 but it is independent of the system firmware. And like a reboot
1305 you can start any kernel with it, not just Linux.
1308 bool "kexec file based system call"
1310 select HAVE_IMA_KEXEC if IMA
1312 This is new version of kexec system call. This system call is
1313 file based and takes file descriptors as system call argument
1314 for kernel and initramfs as opposed to list of segments as
1315 accepted by previous system call.
1318 bool "Verify kernel signature during kexec_file_load() syscall"
1319 depends on KEXEC_FILE
1321 Select this option to verify a signature with loaded kernel
1322 image. If configured, any attempt of loading a image without
1323 valid signature will fail.
1325 In addition to that option, you need to enable signature
1326 verification for the corresponding kernel image type being
1327 loaded in order for this to work.
1329 config KEXEC_IMAGE_VERIFY_SIG
1330 bool "Enable Image signature verification support"
1332 depends on KEXEC_SIG
1333 depends on EFI && SIGNED_PE_FILE_VERIFICATION
1335 Enable Image signature verification support.
1337 comment "Support for PE file signature verification disabled"
1338 depends on KEXEC_SIG
1339 depends on !EFI || !SIGNED_PE_FILE_VERIFICATION
1342 bool "Build kdump crash kernel"
1344 Generate crash dump after being started by kexec. This should
1345 be normally only set in special crash dump kernels which are
1346 loaded in the main kernel with kexec-tools into a specially
1347 reserved region and then later executed after a crash by
1350 For more details see Documentation/admin-guide/kdump/kdump.rst
1354 depends on HIBERNATION || KEXEC_CORE
1361 bool "Xen guest support on ARM64"
1362 depends on ARM64 && OF
1366 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64.
1368 config FORCE_MAX_ZONEORDER
1370 default "14" if ARM64_64K_PAGES
1371 default "12" if ARM64_16K_PAGES
1374 The kernel memory allocator divides physically contiguous memory
1375 blocks into "zones", where each zone is a power of two number of
1376 pages. This option selects the largest power of two that the kernel
1377 keeps in the memory allocator. If you need to allocate very large
1378 blocks of physically contiguous memory, then you may need to
1379 increase this value.
1381 This config option is actually maximum order plus one. For example,
1382 a value of 11 means that the largest free memory block is 2^10 pages.
1384 We make sure that we can allocate upto a HugePage size for each configuration.
1386 MAX_ORDER = (PMD_SHIFT - PAGE_SHIFT) + 1 => PAGE_SHIFT - 2
1388 However for 4K, we choose a higher default value, 11 as opposed to 10, giving us
1389 4M allocations matching the default size used by generic code.
1391 config UNMAP_KERNEL_AT_EL0
1392 bool "Unmap kernel when running in userspace (aka \"KAISER\")" if EXPERT
1395 Speculation attacks against some high-performance processors can
1396 be used to bypass MMU permission checks and leak kernel data to
1397 userspace. This can be defended against by unmapping the kernel
1398 when running in userspace, mapping it back in on exception entry
1399 via a trampoline page in the vector table.
1403 config MITIGATE_SPECTRE_BRANCH_HISTORY
1404 bool "Mitigate Spectre style attacks against branch history" if EXPERT
1407 Speculation attacks against some high-performance processors can
1408 make use of branch history to influence future speculation.
1409 When taking an exception from user-space, a sequence of branches
1410 or a firmware call overwrites the branch history.
1412 config RODATA_FULL_DEFAULT_ENABLED
1413 bool "Apply r/o permissions of VM areas also to their linear aliases"
1416 Apply read-only attributes of VM areas to the linear alias of
1417 the backing pages as well. This prevents code or read-only data
1418 from being modified (inadvertently or intentionally) via another
1419 mapping of the same memory page. This additional enhancement can
1420 be turned off at runtime by passing rodata=[off|on] (and turned on
1421 with rodata=full if this option is set to 'n')
1423 This requires the linear region to be mapped down to pages,
1424 which may adversely affect performance in some cases.
1426 config ARM64_SW_TTBR0_PAN
1427 bool "Emulate Privileged Access Never using TTBR0_EL1 switching"
1429 Enabling this option prevents the kernel from accessing
1430 user-space memory directly by pointing TTBR0_EL1 to a reserved
1431 zeroed area and reserved ASID. The user access routines
1432 restore the valid TTBR0_EL1 temporarily.
1434 config ARM64_TAGGED_ADDR_ABI
1435 bool "Enable the tagged user addresses syscall ABI"
1438 When this option is enabled, user applications can opt in to a
1439 relaxed ABI via prctl() allowing tagged addresses to be passed
1440 to system calls as pointer arguments. For details, see
1441 Documentation/arm64/tagged-address-abi.rst.
1444 bool "Kernel support for 32-bit EL0"
1445 depends on ARM64_4K_PAGES || EXPERT
1447 select OLD_SIGSUSPEND3
1448 select COMPAT_OLD_SIGACTION
1450 This option enables support for a 32-bit EL0 running under a 64-bit
1451 kernel at EL1. AArch32-specific components such as system calls,
1452 the user helper functions, VFP support and the ptrace interface are
1453 handled appropriately by the kernel.
1455 If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware
1456 that you will only be able to execute AArch32 binaries that were compiled
1457 with page size aligned segments.
1459 If you want to execute 32-bit userspace applications, say Y.
1463 config KUSER_HELPERS
1464 bool "Enable kuser helpers page for 32-bit applications"
1467 Warning: disabling this option may break 32-bit user programs.
1469 Provide kuser helpers to compat tasks. The kernel provides
1470 helper code to userspace in read only form at a fixed location
1471 to allow userspace to be independent of the CPU type fitted to
1472 the system. This permits binaries to be run on ARMv4 through
1473 to ARMv8 without modification.
1475 See Documentation/arm/kernel_user_helpers.rst for details.
1477 However, the fixed address nature of these helpers can be used
1478 by ROP (return orientated programming) authors when creating
1481 If all of the binaries and libraries which run on your platform
1482 are built specifically for your platform, and make no use of
1483 these helpers, then you can turn this option off to hinder
1484 such exploits. However, in that case, if a binary or library
1485 relying on those helpers is run, it will not function correctly.
1487 Say N here only if you are absolutely certain that you do not
1488 need these helpers; otherwise, the safe option is to say Y.
1491 bool "Enable vDSO for 32-bit applications"
1492 depends on !CPU_BIG_ENDIAN
1493 depends on (CC_IS_CLANG && LD_IS_LLD) || "$(CROSS_COMPILE_COMPAT)" != ""
1494 select GENERIC_COMPAT_VDSO
1497 Place in the process address space of 32-bit applications an
1498 ELF shared object providing fast implementations of gettimeofday
1501 You must have a 32-bit build of glibc 2.22 or later for programs
1502 to seamlessly take advantage of this.
1504 config THUMB2_COMPAT_VDSO
1505 bool "Compile the 32-bit vDSO for Thumb-2 mode" if EXPERT
1506 depends on COMPAT_VDSO
1509 Compile the compat vDSO with '-mthumb -fomit-frame-pointer' if y,
1510 otherwise with '-marm'.
1512 menuconfig ARMV8_DEPRECATED
1513 bool "Emulate deprecated/obsolete ARMv8 instructions"
1516 Legacy software support may require certain instructions
1517 that have been deprecated or obsoleted in the architecture.
1519 Enable this config to enable selective emulation of these
1526 config SWP_EMULATION
1527 bool "Emulate SWP/SWPB instructions"
1529 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that
1530 they are always undefined. Say Y here to enable software
1531 emulation of these instructions for userspace using LDXR/STXR.
1532 This feature can be controlled at runtime with the abi.swp
1533 sysctl which is disabled by default.
1535 In some older versions of glibc [<=2.8] SWP is used during futex
1536 trylock() operations with the assumption that the code will not
1537 be preempted. This invalid assumption may be more likely to fail
1538 with SWP emulation enabled, leading to deadlock of the user
1541 NOTE: when accessing uncached shared regions, LDXR/STXR rely
1542 on an external transaction monitoring block called a global
1543 monitor to maintain update atomicity. If your system does not
1544 implement a global monitor, this option can cause programs that
1545 perform SWP operations to uncached memory to deadlock.
1549 config CP15_BARRIER_EMULATION
1550 bool "Emulate CP15 Barrier instructions"
1552 The CP15 barrier instructions - CP15ISB, CP15DSB, and
1553 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
1554 strongly recommended to use the ISB, DSB, and DMB
1555 instructions instead.
1557 Say Y here to enable software emulation of these
1558 instructions for AArch32 userspace code. When this option is
1559 enabled, CP15 barrier usage is traced which can help
1560 identify software that needs updating. This feature can be
1561 controlled at runtime with the abi.cp15_barrier sysctl.
1565 config SETEND_EMULATION
1566 bool "Emulate SETEND instruction"
1568 The SETEND instruction alters the data-endianness of the
1569 AArch32 EL0, and is deprecated in ARMv8.
1571 Say Y here to enable software emulation of the instruction
1572 for AArch32 userspace code. This feature can be controlled
1573 at runtime with the abi.setend sysctl.
1575 Note: All the cpus on the system must have mixed endian support at EL0
1576 for this feature to be enabled. If a new CPU - which doesn't support mixed
1577 endian - is hotplugged in after this feature has been enabled, there could
1578 be unexpected results in the applications.
1581 endif # ARMV8_DEPRECATED
1585 menu "ARMv8.1 architectural features"
1587 config ARM64_HW_AFDBM
1588 bool "Support for hardware updates of the Access and Dirty page flags"
1591 The ARMv8.1 architecture extensions introduce support for
1592 hardware updates of the access and dirty information in page
1593 table entries. When enabled in TCR_EL1 (HA and HD bits) on
1594 capable processors, accesses to pages with PTE_AF cleared will
1595 set this bit instead of raising an access flag fault.
1596 Similarly, writes to read-only pages with the DBM bit set will
1597 clear the read-only bit (AP[2]) instead of raising a
1600 Kernels built with this configuration option enabled continue
1601 to work on pre-ARMv8.1 hardware and the performance impact is
1602 minimal. If unsure, say Y.
1605 bool "Enable support for Privileged Access Never (PAN)"
1608 Privileged Access Never (PAN; part of the ARMv8.1 Extensions)
1609 prevents the kernel or hypervisor from accessing user-space (EL0)
1612 Choosing this option will cause any unprotected (not using
1613 copy_to_user et al) memory access to fail with a permission fault.
1615 The feature is detected at runtime, and will remain as a 'nop'
1616 instruction if the cpu does not implement the feature.
1619 def_bool $(as-instr,.arch_extension rcpc)
1621 config AS_HAS_LSE_ATOMICS
1622 def_bool $(as-instr,.arch_extension lse)
1624 config ARM64_LSE_ATOMICS
1626 default ARM64_USE_LSE_ATOMICS
1627 depends on AS_HAS_LSE_ATOMICS
1629 config ARM64_USE_LSE_ATOMICS
1630 bool "Atomic instructions"
1631 depends on JUMP_LABEL
1634 As part of the Large System Extensions, ARMv8.1 introduces new
1635 atomic instructions that are designed specifically to scale in
1638 Say Y here to make use of these instructions for the in-kernel
1639 atomic routines. This incurs a small overhead on CPUs that do
1640 not support these instructions and requires the kernel to be
1641 built with binutils >= 2.25 in order for the new instructions
1644 endmenu # "ARMv8.1 architectural features"
1646 menu "ARMv8.2 architectural features"
1648 config AS_HAS_ARMV8_2
1649 def_bool $(cc-option,-Wa$(comma)-march=armv8.2-a)
1652 def_bool $(as-instr,.arch armv8.2-a+sha3)
1655 bool "Enable support for persistent memory"
1656 select ARCH_HAS_PMEM_API
1657 select ARCH_HAS_UACCESS_FLUSHCACHE
1659 Say Y to enable support for the persistent memory API based on the
1660 ARMv8.2 DCPoP feature.
1662 The feature is detected at runtime, and the kernel will use DC CVAC
1663 operations if DC CVAP is not supported (following the behaviour of
1664 DC CVAP itself if the system does not define a point of persistence).
1666 config ARM64_RAS_EXTN
1667 bool "Enable support for RAS CPU Extensions"
1670 CPUs that support the Reliability, Availability and Serviceability
1671 (RAS) Extensions, part of ARMv8.2 are able to track faults and
1672 errors, classify them and report them to software.
1674 On CPUs with these extensions system software can use additional
1675 barriers to determine if faults are pending and read the
1676 classification from a new set of registers.
1678 Selecting this feature will allow the kernel to use these barriers
1679 and access the new registers if the system supports the extension.
1680 Platform RAS features may additionally depend on firmware support.
1683 bool "Enable support for Common Not Private (CNP) translations"
1685 depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN
1687 Common Not Private (CNP) allows translation table entries to
1688 be shared between different PEs in the same inner shareable
1689 domain, so the hardware can use this fact to optimise the
1690 caching of such entries in the TLB.
1692 Selecting this option allows the CNP feature to be detected
1693 at runtime, and does not affect PEs that do not implement
1696 endmenu # "ARMv8.2 architectural features"
1698 menu "ARMv8.3 architectural features"
1700 config ARM64_PTR_AUTH
1701 bool "Enable support for pointer authentication"
1704 Pointer authentication (part of the ARMv8.3 Extensions) provides
1705 instructions for signing and authenticating pointers against secret
1706 keys, which can be used to mitigate Return Oriented Programming (ROP)
1709 This option enables these instructions at EL0 (i.e. for userspace).
1710 Choosing this option will cause the kernel to initialise secret keys
1711 for each process at exec() time, with these keys being
1712 context-switched along with the process.
1714 The feature is detected at runtime. If the feature is not present in
1715 hardware it will not be advertised to userspace/KVM guest nor will it
1718 If the feature is present on the boot CPU but not on a late CPU, then
1719 the late CPU will be parked. Also, if the boot CPU does not have
1720 address auth and the late CPU has then the late CPU will still boot
1721 but with the feature disabled. On such a system, this option should
1724 config ARM64_PTR_AUTH_KERNEL
1725 bool "Use pointer authentication for kernel"
1727 depends on ARM64_PTR_AUTH
1728 depends on (CC_HAS_SIGN_RETURN_ADDRESS || CC_HAS_BRANCH_PROT_PAC_RET) && AS_HAS_PAC
1729 # Modern compilers insert a .note.gnu.property section note for PAC
1730 # which is only understood by binutils starting with version 2.33.1.
1731 depends on LD_IS_LLD || LD_VERSION >= 23301 || (CC_IS_GCC && GCC_VERSION < 90100)
1732 depends on !CC_IS_CLANG || AS_HAS_CFI_NEGATE_RA_STATE
1733 depends on (!FUNCTION_GRAPH_TRACER || DYNAMIC_FTRACE_WITH_REGS)
1735 If the compiler supports the -mbranch-protection or
1736 -msign-return-address flag (e.g. GCC 7 or later), then this option
1737 will cause the kernel itself to be compiled with return address
1738 protection. In this case, and if the target hardware is known to
1739 support pointer authentication, then CONFIG_STACKPROTECTOR can be
1740 disabled with minimal loss of protection.
1742 This feature works with FUNCTION_GRAPH_TRACER option only if
1743 DYNAMIC_FTRACE_WITH_REGS is enabled.
1745 config CC_HAS_BRANCH_PROT_PAC_RET
1746 # GCC 9 or later, clang 8 or later
1747 def_bool $(cc-option,-mbranch-protection=pac-ret+leaf)
1749 config CC_HAS_SIGN_RETURN_ADDRESS
1751 def_bool $(cc-option,-msign-return-address=all)
1754 def_bool $(cc-option,-Wa$(comma)-march=armv8.3-a)
1756 config AS_HAS_CFI_NEGATE_RA_STATE
1757 def_bool $(as-instr,.cfi_startproc\n.cfi_negate_ra_state\n.cfi_endproc\n)
1759 endmenu # "ARMv8.3 architectural features"
1761 menu "ARMv8.4 architectural features"
1763 config ARM64_AMU_EXTN
1764 bool "Enable support for the Activity Monitors Unit CPU extension"
1767 The activity monitors extension is an optional extension introduced
1768 by the ARMv8.4 CPU architecture. This enables support for version 1
1769 of the activity monitors architecture, AMUv1.
1771 To enable the use of this extension on CPUs that implement it, say Y.
1773 Note that for architectural reasons, firmware _must_ implement AMU
1774 support when running on CPUs that present the activity monitors
1775 extension. The required support is present in:
1776 * Version 1.5 and later of the ARM Trusted Firmware
1778 For kernels that have this configuration enabled but boot with broken
1779 firmware, you may need to say N here until the firmware is fixed.
1780 Otherwise you may experience firmware panics or lockups when
1781 accessing the counter registers. Even if you are not observing these
1782 symptoms, the values returned by the register reads might not
1783 correctly reflect reality. Most commonly, the value read will be 0,
1784 indicating that the counter is not enabled.
1786 config AS_HAS_ARMV8_4
1787 def_bool $(cc-option,-Wa$(comma)-march=armv8.4-a)
1789 config ARM64_TLB_RANGE
1790 bool "Enable support for tlbi range feature"
1792 depends on AS_HAS_ARMV8_4
1794 ARMv8.4-TLBI provides TLBI invalidation instruction that apply to a
1795 range of input addresses.
1797 The feature introduces new assembly instructions, and they were
1798 support when binutils >= 2.30.
1800 endmenu # "ARMv8.4 architectural features"
1802 menu "ARMv8.5 architectural features"
1804 config AS_HAS_ARMV8_5
1805 def_bool $(cc-option,-Wa$(comma)-march=armv8.5-a)
1808 bool "Branch Target Identification support"
1811 Branch Target Identification (part of the ARMv8.5 Extensions)
1812 provides a mechanism to limit the set of locations to which computed
1813 branch instructions such as BR or BLR can jump.
1815 To make use of BTI on CPUs that support it, say Y.
1817 BTI is intended to provide complementary protection to other control
1818 flow integrity protection mechanisms, such as the Pointer
1819 authentication mechanism provided as part of the ARMv8.3 Extensions.
1820 For this reason, it does not make sense to enable this option without
1821 also enabling support for pointer authentication. Thus, when
1822 enabling this option you should also select ARM64_PTR_AUTH=y.
1824 Userspace binaries must also be specifically compiled to make use of
1825 this mechanism. If you say N here or the hardware does not support
1826 BTI, such binaries can still run, but you get no additional
1827 enforcement of branch destinations.
1829 config ARM64_BTI_KERNEL
1830 bool "Use Branch Target Identification for kernel"
1832 depends on ARM64_BTI
1833 depends on ARM64_PTR_AUTH_KERNEL
1834 depends on CC_HAS_BRANCH_PROT_PAC_RET_BTI
1835 # https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94697
1836 depends on !CC_IS_GCC || GCC_VERSION >= 100100
1837 # https://github.com/llvm/llvm-project/commit/a88c722e687e6780dcd6a58718350dc76fcc4cc9
1838 depends on !CC_IS_CLANG || CLANG_VERSION >= 120000
1839 depends on (!FUNCTION_GRAPH_TRACER || DYNAMIC_FTRACE_WITH_REGS)
1841 Build the kernel with Branch Target Identification annotations
1842 and enable enforcement of this for kernel code. When this option
1843 is enabled and the system supports BTI all kernel code including
1844 modular code must have BTI enabled.
1846 config CC_HAS_BRANCH_PROT_PAC_RET_BTI
1847 # GCC 9 or later, clang 8 or later
1848 def_bool $(cc-option,-mbranch-protection=pac-ret+leaf+bti)
1851 bool "Enable support for E0PD"
1854 E0PD (part of the ARMv8.5 extensions) allows us to ensure
1855 that EL0 accesses made via TTBR1 always fault in constant time,
1856 providing similar benefits to KASLR as those provided by KPTI, but
1857 with lower overhead and without disrupting legitimate access to
1858 kernel memory such as SPE.
1860 This option enables E0PD for TTBR1 where available.
1863 bool "Enable support for random number generation"
1866 Random number generation (part of the ARMv8.5 Extensions)
1867 provides a high bandwidth, cryptographically secure
1868 hardware random number generator.
1870 config ARM64_AS_HAS_MTE
1871 # Initial support for MTE went in binutils 2.32.0, checked with
1872 # ".arch armv8.5-a+memtag" below. However, this was incomplete
1873 # as a late addition to the final architecture spec (LDGM/STGM)
1874 # is only supported in the newer 2.32.x and 2.33 binutils
1875 # versions, hence the extra "stgm" instruction check below.
1876 def_bool $(as-instr,.arch armv8.5-a+memtag\nstgm xzr$(comma)[x0])
1879 bool "Memory Tagging Extension support"
1881 depends on ARM64_AS_HAS_MTE && ARM64_TAGGED_ADDR_ABI
1882 depends on AS_HAS_ARMV8_5
1883 depends on AS_HAS_LSE_ATOMICS
1884 # Required for tag checking in the uaccess routines
1885 depends on ARM64_PAN
1886 select ARCH_HAS_SUBPAGE_FAULTS
1887 select ARCH_USES_HIGH_VMA_FLAGS
1889 Memory Tagging (part of the ARMv8.5 Extensions) provides
1890 architectural support for run-time, always-on detection of
1891 various classes of memory error to aid with software debugging
1892 to eliminate vulnerabilities arising from memory-unsafe
1895 This option enables the support for the Memory Tagging
1896 Extension at EL0 (i.e. for userspace).
1898 Selecting this option allows the feature to be detected at
1899 runtime. Any secondary CPU not implementing this feature will
1900 not be allowed a late bring-up.
1902 Userspace binaries that want to use this feature must
1903 explicitly opt in. The mechanism for the userspace is
1906 Documentation/arm64/memory-tagging-extension.rst.
1908 endmenu # "ARMv8.5 architectural features"
1910 menu "ARMv8.7 architectural features"
1913 bool "Enable support for Enhanced Privileged Access Never (EPAN)"
1915 depends on ARM64_PAN
1917 Enhanced Privileged Access Never (EPAN) allows Privileged
1918 Access Never to be used with Execute-only mappings.
1920 The feature is detected at runtime, and will remain disabled
1921 if the cpu does not implement the feature.
1922 endmenu # "ARMv8.7 architectural features"
1925 bool "ARM Scalable Vector Extension support"
1928 The Scalable Vector Extension (SVE) is an extension to the AArch64
1929 execution state which complements and extends the SIMD functionality
1930 of the base architecture to support much larger vectors and to enable
1931 additional vectorisation opportunities.
1933 To enable use of this extension on CPUs that implement it, say Y.
1935 On CPUs that support the SVE2 extensions, this option will enable
1938 Note that for architectural reasons, firmware _must_ implement SVE
1939 support when running on SVE capable hardware. The required support
1942 * version 1.5 and later of the ARM Trusted Firmware
1943 * the AArch64 boot wrapper since commit 5e1261e08abf
1944 ("bootwrapper: SVE: Enable SVE for EL2 and below").
1946 For other firmware implementations, consult the firmware documentation
1949 If you need the kernel to boot on SVE-capable hardware with broken
1950 firmware, you may need to say N here until you get your firmware
1951 fixed. Otherwise, you may experience firmware panics or lockups when
1952 booting the kernel. If unsure and you are not observing these
1953 symptoms, you should assume that it is safe to say Y.
1956 bool "ARM Scalable Matrix Extension support"
1958 depends on ARM64_SVE
1960 The Scalable Matrix Extension (SME) is an extension to the AArch64
1961 execution state which utilises a substantial subset of the SVE
1962 instruction set, together with the addition of new architectural
1963 register state capable of holding two dimensional matrix tiles to
1964 enable various matrix operations.
1966 config ARM64_MODULE_PLTS
1967 bool "Use PLTs to allow module memory to spill over into vmalloc area"
1969 select HAVE_MOD_ARCH_SPECIFIC
1971 Allocate PLTs when loading modules so that jumps and calls whose
1972 targets are too far away for their relative offsets to be encoded
1973 in the instructions themselves can be bounced via veneers in the
1974 module's PLT. This allows modules to be allocated in the generic
1975 vmalloc area after the dedicated module memory area has been
1978 When running with address space randomization (KASLR), the module
1979 region itself may be too far away for ordinary relative jumps and
1980 calls, and so in that case, module PLTs are required and cannot be
1983 Specific errata workaround(s) might also force module PLTs to be
1984 enabled (ARM64_ERRATUM_843419).
1986 config ARM64_PSEUDO_NMI
1987 bool "Support for NMI-like interrupts"
1990 Adds support for mimicking Non-Maskable Interrupts through the use of
1991 GIC interrupt priority. This support requires version 3 or later of
1994 This high priority configuration for interrupts needs to be
1995 explicitly enabled by setting the kernel parameter
1996 "irqchip.gicv3_pseudo_nmi" to 1.
2001 config ARM64_DEBUG_PRIORITY_MASKING
2002 bool "Debug interrupt priority masking"
2004 This adds runtime checks to functions enabling/disabling
2005 interrupts when using priority masking. The additional checks verify
2006 the validity of ICC_PMR_EL1 when calling concerned functions.
2009 endif # ARM64_PSEUDO_NMI
2012 bool "Build a relocatable kernel image" if EXPERT
2013 select ARCH_HAS_RELR
2016 This builds the kernel as a Position Independent Executable (PIE),
2017 which retains all relocation metadata required to relocate the
2018 kernel binary at runtime to a different virtual address than the
2019 address it was linked at.
2020 Since AArch64 uses the RELA relocation format, this requires a
2021 relocation pass at runtime even if the kernel is loaded at the
2022 same address it was linked at.
2024 config RANDOMIZE_BASE
2025 bool "Randomize the address of the kernel image"
2026 select ARM64_MODULE_PLTS if MODULES
2029 Randomizes the virtual address at which the kernel image is
2030 loaded, as a security feature that deters exploit attempts
2031 relying on knowledge of the location of kernel internals.
2033 It is the bootloader's job to provide entropy, by passing a
2034 random u64 value in /chosen/kaslr-seed at kernel entry.
2036 When booting via the UEFI stub, it will invoke the firmware's
2037 EFI_RNG_PROTOCOL implementation (if available) to supply entropy
2038 to the kernel proper. In addition, it will randomise the physical
2039 location of the kernel Image as well.
2043 config RANDOMIZE_MODULE_REGION_FULL
2044 bool "Randomize the module region over a 2 GB range"
2045 depends on RANDOMIZE_BASE
2048 Randomizes the location of the module region inside a 2 GB window
2049 covering the core kernel. This way, it is less likely for modules
2050 to leak information about the location of core kernel data structures
2051 but it does imply that function calls between modules and the core
2052 kernel will need to be resolved via veneers in the module PLT.
2054 When this option is not set, the module region will be randomized over
2055 a limited range that contains the [_stext, _etext] interval of the
2056 core kernel, so branch relocations are almost always in range unless
2057 ARM64_MODULE_PLTS is enabled and the region is exhausted. In this
2058 particular case of region exhaustion, modules might be able to fall
2059 back to a larger 2GB area.
2061 config CC_HAVE_STACKPROTECTOR_SYSREG
2062 def_bool $(cc-option,-mstack-protector-guard=sysreg -mstack-protector-guard-reg=sp_el0 -mstack-protector-guard-offset=0)
2064 config STACKPROTECTOR_PER_TASK
2066 depends on STACKPROTECTOR && CC_HAVE_STACKPROTECTOR_SYSREG
2068 # The GPIO number here must be sorted by descending number. In case of
2069 # a multiplatform kernel, we just want the highest value required by the
2070 # selected platforms.
2073 default 2048 if ARCH_APPLE
2076 Maximum number of GPIOs in the system.
2078 If unsure, leave the default value.
2080 endmenu # "Kernel Features"
2084 config ARM64_ACPI_PARKING_PROTOCOL
2085 bool "Enable support for the ARM64 ACPI parking protocol"
2088 Enable support for the ARM64 ACPI parking protocol. If disabled
2089 the kernel will not allow booting through the ARM64 ACPI parking
2090 protocol even if the corresponding data is present in the ACPI
2094 string "Default kernel command string"
2097 Provide a set of default command-line options at build time by
2098 entering them here. As a minimum, you should specify the the
2099 root device (e.g. root=/dev/nfs).
2102 prompt "Kernel command line type" if CMDLINE != ""
2103 default CMDLINE_FROM_BOOTLOADER
2105 Choose how the kernel will handle the provided default kernel
2106 command line string.
2108 config CMDLINE_FROM_BOOTLOADER
2109 bool "Use bootloader kernel arguments if available"
2111 Uses the command-line options passed by the boot loader. If
2112 the boot loader doesn't provide any, the default kernel command
2113 string provided in CMDLINE will be used.
2115 config CMDLINE_FORCE
2116 bool "Always use the default kernel command string"
2118 Always use the default kernel command string, even if the boot
2119 loader passes other arguments to the kernel.
2120 This is useful if you cannot or don't want to change the
2121 command-line options your boot loader passes to the kernel.
2129 bool "UEFI runtime support"
2130 depends on OF && !CPU_BIG_ENDIAN
2131 depends on KERNEL_MODE_NEON
2132 select ARCH_SUPPORTS_ACPI
2135 select EFI_PARAMS_FROM_FDT
2136 select EFI_RUNTIME_WRAPPERS
2138 select EFI_GENERIC_STUB
2139 imply IMA_SECURE_AND_OR_TRUSTED_BOOT
2142 This option provides support for runtime services provided
2143 by UEFI firmware (such as non-volatile variables, realtime
2144 clock, and platform reset). A UEFI stub is also provided to
2145 allow the kernel to be booted as an EFI application. This
2146 is only useful on systems that have UEFI firmware.
2149 bool "Enable support for SMBIOS (DMI) tables"
2153 This enables SMBIOS/DMI feature for systems.
2155 This option is only useful on systems that have UEFI firmware.
2156 However, even with this option, the resultant kernel should
2157 continue to boot on existing non-UEFI platforms.
2159 endmenu # "Boot options"
2161 menu "Power management options"
2163 source "kernel/power/Kconfig"
2165 config ARCH_HIBERNATION_POSSIBLE
2169 config ARCH_HIBERNATION_HEADER
2171 depends on HIBERNATION
2173 config ARCH_SUSPEND_POSSIBLE
2176 endmenu # "Power management options"
2178 menu "CPU Power Management"
2180 source "drivers/cpuidle/Kconfig"
2182 source "drivers/cpufreq/Kconfig"
2184 endmenu # "CPU Power Management"
2186 source "drivers/acpi/Kconfig"
2188 source "arch/arm64/kvm/Kconfig"
2191 source "arch/arm64/crypto/Kconfig"