1 # SPDX-License-Identifier: GPL-2.0-only
4 select ACPI_CCA_REQUIRED if ACPI
5 select ACPI_GENERIC_GSI if ACPI
6 select ACPI_GTDT if ACPI
7 select ACPI_IORT if ACPI
8 select ACPI_REDUCED_HARDWARE_ONLY if ACPI
9 select ACPI_MCFG if (ACPI && PCI)
10 select ACPI_SPCR_TABLE if ACPI
11 select ACPI_PPTT if ACPI
12 select ARCH_HAS_DEBUG_WX
13 select ARCH_BINFMT_ELF_STATE
14 select ARCH_HAS_DEBUG_VIRTUAL
15 select ARCH_HAS_DEBUG_VM_PGTABLE
16 select ARCH_HAS_DEVMEM_IS_ALLOWED
17 select ARCH_HAS_DMA_PREP_COHERENT
18 select ARCH_HAS_ACPI_TABLE_UPGRADE if ACPI
19 select ARCH_HAS_FAST_MULTIPLIER
20 select ARCH_HAS_FORTIFY_SOURCE
21 select ARCH_HAS_GCOV_PROFILE_ALL
22 select ARCH_HAS_GIGANTIC_PAGE
24 select ARCH_HAS_KEEPINITRD
25 select ARCH_HAS_MEMBARRIER_SYNC_CORE
26 select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE
27 select ARCH_HAS_PTE_DEVMAP
28 select ARCH_HAS_PTE_SPECIAL
29 select ARCH_HAS_SETUP_DMA_OPS
30 select ARCH_HAS_SET_DIRECT_MAP
31 select ARCH_HAS_SET_MEMORY
33 select ARCH_HAS_STRICT_KERNEL_RWX
34 select ARCH_HAS_STRICT_MODULE_RWX
35 select ARCH_HAS_SYNC_DMA_FOR_DEVICE
36 select ARCH_HAS_SYNC_DMA_FOR_CPU
37 select ARCH_HAS_SYSCALL_WRAPPER
38 select ARCH_HAS_TEARDOWN_DMA_OPS if IOMMU_SUPPORT
39 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
40 select ARCH_HAVE_ELF_PROT
41 select ARCH_HAVE_NMI_SAFE_CMPXCHG
42 select ARCH_INLINE_READ_LOCK if !PREEMPTION
43 select ARCH_INLINE_READ_LOCK_BH if !PREEMPTION
44 select ARCH_INLINE_READ_LOCK_IRQ if !PREEMPTION
45 select ARCH_INLINE_READ_LOCK_IRQSAVE if !PREEMPTION
46 select ARCH_INLINE_READ_UNLOCK if !PREEMPTION
47 select ARCH_INLINE_READ_UNLOCK_BH if !PREEMPTION
48 select ARCH_INLINE_READ_UNLOCK_IRQ if !PREEMPTION
49 select ARCH_INLINE_READ_UNLOCK_IRQRESTORE if !PREEMPTION
50 select ARCH_INLINE_WRITE_LOCK if !PREEMPTION
51 select ARCH_INLINE_WRITE_LOCK_BH if !PREEMPTION
52 select ARCH_INLINE_WRITE_LOCK_IRQ if !PREEMPTION
53 select ARCH_INLINE_WRITE_LOCK_IRQSAVE if !PREEMPTION
54 select ARCH_INLINE_WRITE_UNLOCK if !PREEMPTION
55 select ARCH_INLINE_WRITE_UNLOCK_BH if !PREEMPTION
56 select ARCH_INLINE_WRITE_UNLOCK_IRQ if !PREEMPTION
57 select ARCH_INLINE_WRITE_UNLOCK_IRQRESTORE if !PREEMPTION
58 select ARCH_INLINE_SPIN_TRYLOCK if !PREEMPTION
59 select ARCH_INLINE_SPIN_TRYLOCK_BH if !PREEMPTION
60 select ARCH_INLINE_SPIN_LOCK if !PREEMPTION
61 select ARCH_INLINE_SPIN_LOCK_BH if !PREEMPTION
62 select ARCH_INLINE_SPIN_LOCK_IRQ if !PREEMPTION
63 select ARCH_INLINE_SPIN_LOCK_IRQSAVE if !PREEMPTION
64 select ARCH_INLINE_SPIN_UNLOCK if !PREEMPTION
65 select ARCH_INLINE_SPIN_UNLOCK_BH if !PREEMPTION
66 select ARCH_INLINE_SPIN_UNLOCK_IRQ if !PREEMPTION
67 select ARCH_INLINE_SPIN_UNLOCK_IRQRESTORE if !PREEMPTION
68 select ARCH_KEEP_MEMBLOCK
69 select ARCH_USE_CMPXCHG_LOCKREF
70 select ARCH_USE_GNU_PROPERTY
71 select ARCH_USE_QUEUED_RWLOCKS
72 select ARCH_USE_QUEUED_SPINLOCKS
73 select ARCH_USE_SYM_ANNOTATIONS
74 select ARCH_SUPPORTS_MEMORY_FAILURE
75 select ARCH_SUPPORTS_SHADOW_CALL_STACK if CC_HAVE_SHADOW_CALL_STACK
76 select ARCH_SUPPORTS_ATOMIC_RMW
77 select ARCH_SUPPORTS_INT128 if CC_HAS_INT128 && (GCC_VERSION >= 50000 || CC_IS_CLANG)
78 select ARCH_SUPPORTS_NUMA_BALANCING
79 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION if COMPAT
80 select ARCH_WANT_DEFAULT_BPF_JIT
81 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT
82 select ARCH_WANT_FRAME_POINTERS
83 select ARCH_WANT_HUGE_PMD_SHARE if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36)
84 select ARCH_HAS_UBSAN_SANITIZE_ALL
88 select AUDIT_ARCH_COMPAT_GENERIC
89 select ARM_GIC_V2M if PCI
91 select ARM_GIC_V3_ITS if PCI
93 select BUILDTIME_TABLE_SORT
94 select CLONE_BACKWARDS
96 select CPU_PM if (SUSPEND || CPU_IDLE)
98 select DCACHE_WORD_ACCESS
99 select DMA_DIRECT_REMAP
102 select GENERIC_ALLOCATOR
103 select GENERIC_ARCH_TOPOLOGY
104 select GENERIC_CLOCKEVENTS
105 select GENERIC_CLOCKEVENTS_BROADCAST
106 select GENERIC_CPU_AUTOPROBE
107 select GENERIC_CPU_VULNERABILITIES
108 select GENERIC_EARLY_IOREMAP
109 select GENERIC_IDLE_POLL_SETUP
110 select GENERIC_IRQ_IPI
111 select GENERIC_IRQ_MULTI_HANDLER
112 select GENERIC_IRQ_PROBE
113 select GENERIC_IRQ_SHOW
114 select GENERIC_IRQ_SHOW_LEVEL
115 select GENERIC_PCI_IOMAP
116 select GENERIC_PTDUMP
117 select GENERIC_SCHED_CLOCK
118 select GENERIC_SMP_IDLE_THREAD
119 select GENERIC_STRNCPY_FROM_USER
120 select GENERIC_STRNLEN_USER
121 select GENERIC_TIME_VSYSCALL
122 select GENERIC_GETTIMEOFDAY
123 select GENERIC_VDSO_TIME_NS
124 select HANDLE_DOMAIN_IRQ
125 select HARDIRQS_SW_RESEND
127 select HAVE_ACPI_APEI if (ACPI && EFI)
128 select HAVE_ALIGNED_STRUCT_PAGE if SLUB
129 select HAVE_ARCH_AUDITSYSCALL
130 select HAVE_ARCH_BITREVERSE
131 select HAVE_ARCH_COMPILER_H
132 select HAVE_ARCH_HUGE_VMAP
133 select HAVE_ARCH_JUMP_LABEL
134 select HAVE_ARCH_JUMP_LABEL_RELATIVE
135 select HAVE_ARCH_KASAN if !(ARM64_16K_PAGES && ARM64_VA_BITS_48)
136 select HAVE_ARCH_KASAN_SW_TAGS if HAVE_ARCH_KASAN
137 select HAVE_ARCH_KGDB
138 select HAVE_ARCH_MMAP_RND_BITS
139 select HAVE_ARCH_MMAP_RND_COMPAT_BITS if COMPAT
140 select HAVE_ARCH_PREL32_RELOCATIONS
141 select HAVE_ARCH_SECCOMP_FILTER
142 select HAVE_ARCH_STACKLEAK
143 select HAVE_ARCH_THREAD_STRUCT_WHITELIST
144 select HAVE_ARCH_TRACEHOOK
145 select HAVE_ARCH_TRANSPARENT_HUGEPAGE
146 select HAVE_ARCH_VMAP_STACK
147 select HAVE_ARM_SMCCC
148 select HAVE_ASM_MODVERSIONS
150 select HAVE_C_RECORDMCOUNT
151 select HAVE_CMPXCHG_DOUBLE
152 select HAVE_CMPXCHG_LOCAL
153 select HAVE_CONTEXT_TRACKING
154 select HAVE_DEBUG_BUGVERBOSE
155 select HAVE_DEBUG_KMEMLEAK
156 select HAVE_DMA_CONTIGUOUS
157 select HAVE_DYNAMIC_FTRACE
158 select HAVE_DYNAMIC_FTRACE_WITH_REGS \
159 if $(cc-option,-fpatchable-function-entry=2)
160 select HAVE_EFFICIENT_UNALIGNED_ACCESS
162 select HAVE_FTRACE_MCOUNT_RECORD
163 select HAVE_FUNCTION_TRACER
164 select HAVE_FUNCTION_ERROR_INJECTION
165 select HAVE_FUNCTION_GRAPH_TRACER
166 select HAVE_GCC_PLUGINS
167 select HAVE_HW_BREAKPOINT if PERF_EVENTS
168 select HAVE_IRQ_TIME_ACCOUNTING
170 select HAVE_PATA_PLATFORM
171 select HAVE_PERF_EVENTS
172 select HAVE_PERF_REGS
173 select HAVE_PERF_USER_STACK_DUMP
174 select HAVE_REGS_AND_STACK_ACCESS_API
175 select HAVE_FUNCTION_ARG_ACCESS_API
176 select HAVE_FUTEX_CMPXCHG if FUTEX
177 select MMU_GATHER_RCU_TABLE_FREE
179 select HAVE_STACKPROTECTOR
180 select HAVE_SYSCALL_TRACEPOINTS
182 select HAVE_KRETPROBES
183 select HAVE_GENERIC_VDSO
184 select IOMMU_DMA if IOMMU_SUPPORT
186 select IRQ_FORCED_THREADING
187 select MODULES_USE_ELF_RELA
188 select NEED_DMA_MAP_STATE
189 select NEED_SG_DMA_LENGTH
191 select OF_EARLY_FLATTREE
192 select PCI_DOMAINS_GENERIC if PCI
193 select PCI_ECAM if (ACPI && PCI)
194 select PCI_SYSCALL if PCI
200 select SYSCTL_EXCEPTION_TRACE
201 select THREAD_INFO_IN_TASK
203 ARM 64-bit (AArch64) Linux support.
211 config ARM64_PAGE_SHIFT
213 default 16 if ARM64_64K_PAGES
214 default 14 if ARM64_16K_PAGES
217 config ARM64_CONT_PTE_SHIFT
219 default 5 if ARM64_64K_PAGES
220 default 7 if ARM64_16K_PAGES
223 config ARM64_CONT_PMD_SHIFT
225 default 5 if ARM64_64K_PAGES
226 default 5 if ARM64_16K_PAGES
229 config ARCH_MMAP_RND_BITS_MIN
230 default 14 if ARM64_64K_PAGES
231 default 16 if ARM64_16K_PAGES
234 # max bits determined by the following formula:
235 # VA_BITS - PAGE_SHIFT - 3
236 config ARCH_MMAP_RND_BITS_MAX
237 default 19 if ARM64_VA_BITS=36
238 default 24 if ARM64_VA_BITS=39
239 default 27 if ARM64_VA_BITS=42
240 default 30 if ARM64_VA_BITS=47
241 default 29 if ARM64_VA_BITS=48 && ARM64_64K_PAGES
242 default 31 if ARM64_VA_BITS=48 && ARM64_16K_PAGES
243 default 33 if ARM64_VA_BITS=48
244 default 14 if ARM64_64K_PAGES
245 default 16 if ARM64_16K_PAGES
248 config ARCH_MMAP_RND_COMPAT_BITS_MIN
249 default 7 if ARM64_64K_PAGES
250 default 9 if ARM64_16K_PAGES
253 config ARCH_MMAP_RND_COMPAT_BITS_MAX
259 config STACKTRACE_SUPPORT
262 config ILLEGAL_POINTER_VALUE
264 default 0xdead000000000000
266 config LOCKDEP_SUPPORT
269 config TRACE_IRQFLAGS_SUPPORT
276 config GENERIC_BUG_RELATIVE_POINTERS
278 depends on GENERIC_BUG
280 config GENERIC_HWEIGHT
286 config GENERIC_CALIBRATE_DELAY
290 bool "Support DMA zone" if EXPERT
294 bool "Support DMA32 zone" if EXPERT
297 config ARCH_ENABLE_MEMORY_HOTPLUG
300 config ARCH_ENABLE_MEMORY_HOTREMOVE
306 config KERNEL_MODE_NEON
309 config FIX_EARLYCON_MEM
312 config PGTABLE_LEVELS
314 default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36
315 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42
316 default 3 if ARM64_64K_PAGES && (ARM64_VA_BITS_48 || ARM64_VA_BITS_52)
317 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39
318 default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47
319 default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48
321 config ARCH_SUPPORTS_UPROBES
324 config ARCH_PROC_KCORE_TEXT
327 config BROKEN_GAS_INST
328 def_bool !$(as-instr,1:\n.inst 0\n.rept . - 1b\n\nnop\n.endr\n)
330 config KASAN_SHADOW_OFFSET
333 default 0xdfffa00000000000 if (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) && !KASAN_SW_TAGS
334 default 0xdfffd00000000000 if ARM64_VA_BITS_47 && !KASAN_SW_TAGS
335 default 0xdffffe8000000000 if ARM64_VA_BITS_42 && !KASAN_SW_TAGS
336 default 0xdfffffd000000000 if ARM64_VA_BITS_39 && !KASAN_SW_TAGS
337 default 0xdffffffa00000000 if ARM64_VA_BITS_36 && !KASAN_SW_TAGS
338 default 0xefff900000000000 if (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) && KASAN_SW_TAGS
339 default 0xefffc80000000000 if ARM64_VA_BITS_47 && KASAN_SW_TAGS
340 default 0xeffffe4000000000 if ARM64_VA_BITS_42 && KASAN_SW_TAGS
341 default 0xefffffc800000000 if ARM64_VA_BITS_39 && KASAN_SW_TAGS
342 default 0xeffffff900000000 if ARM64_VA_BITS_36 && KASAN_SW_TAGS
343 default 0xffffffffffffffff
345 source "arch/arm64/Kconfig.platforms"
347 menu "Kernel Features"
349 menu "ARM errata workarounds via the alternatives framework"
351 config ARM64_WORKAROUND_CLEAN_CACHE
354 config ARM64_ERRATUM_826319
355 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"
357 select ARM64_WORKAROUND_CLEAN_CACHE
359 This option adds an alternative code sequence to work around ARM
360 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
361 AXI master interface and an L2 cache.
363 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
364 and is unable to accept a certain write via this interface, it will
365 not progress on read data presented on the read data channel and the
368 The workaround promotes data cache clean instructions to
369 data cache clean-and-invalidate.
370 Please note that this does not necessarily enable the workaround,
371 as it depends on the alternative framework, which will only patch
372 the kernel if an affected CPU is detected.
376 config ARM64_ERRATUM_827319
377 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
379 select ARM64_WORKAROUND_CLEAN_CACHE
381 This option adds an alternative code sequence to work around ARM
382 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
383 master interface and an L2 cache.
385 Under certain conditions this erratum can cause a clean line eviction
386 to occur at the same time as another transaction to the same address
387 on the AMBA 5 CHI interface, which can cause data corruption if the
388 interconnect reorders the two transactions.
390 The workaround promotes data cache clean instructions to
391 data cache clean-and-invalidate.
392 Please note that this does not necessarily enable the workaround,
393 as it depends on the alternative framework, which will only patch
394 the kernel if an affected CPU is detected.
398 config ARM64_ERRATUM_824069
399 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
401 select ARM64_WORKAROUND_CLEAN_CACHE
403 This option adds an alternative code sequence to work around ARM
404 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
405 to a coherent interconnect.
407 If a Cortex-A53 processor is executing a store or prefetch for
408 write instruction at the same time as a processor in another
409 cluster is executing a cache maintenance operation to the same
410 address, then this erratum might cause a clean cache line to be
411 incorrectly marked as dirty.
413 The workaround promotes data cache clean instructions to
414 data cache clean-and-invalidate.
415 Please note that this option does not necessarily enable the
416 workaround, as it depends on the alternative framework, which will
417 only patch the kernel if an affected CPU is detected.
421 config ARM64_ERRATUM_819472
422 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
424 select ARM64_WORKAROUND_CLEAN_CACHE
426 This option adds an alternative code sequence to work around ARM
427 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
428 present when it is connected to a coherent interconnect.
430 If the processor is executing a load and store exclusive sequence at
431 the same time as a processor in another cluster is executing a cache
432 maintenance operation to the same address, then this erratum might
433 cause data corruption.
435 The workaround promotes data cache clean instructions to
436 data cache clean-and-invalidate.
437 Please note that this does not necessarily enable the workaround,
438 as it depends on the alternative framework, which will only patch
439 the kernel if an affected CPU is detected.
443 config ARM64_ERRATUM_832075
444 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
447 This option adds an alternative code sequence to work around ARM
448 erratum 832075 on Cortex-A57 parts up to r1p2.
450 Affected Cortex-A57 parts might deadlock when exclusive load/store
451 instructions to Write-Back memory are mixed with Device loads.
453 The workaround is to promote device loads to use Load-Acquire
455 Please note that this does not necessarily enable the workaround,
456 as it depends on the alternative framework, which will only patch
457 the kernel if an affected CPU is detected.
461 config ARM64_ERRATUM_834220
462 bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault"
466 This option adds an alternative code sequence to work around ARM
467 erratum 834220 on Cortex-A57 parts up to r1p2.
469 Affected Cortex-A57 parts might report a Stage 2 translation
470 fault as the result of a Stage 1 fault for load crossing a
471 page boundary when there is a permission or device memory
472 alignment fault at Stage 1 and a translation fault at Stage 2.
474 The workaround is to verify that the Stage 1 translation
475 doesn't generate a fault before handling the Stage 2 fault.
476 Please note that this does not necessarily enable the workaround,
477 as it depends on the alternative framework, which will only patch
478 the kernel if an affected CPU is detected.
482 config ARM64_ERRATUM_845719
483 bool "Cortex-A53: 845719: a load might read incorrect data"
487 This option adds an alternative code sequence to work around ARM
488 erratum 845719 on Cortex-A53 parts up to r0p4.
490 When running a compat (AArch32) userspace on an affected Cortex-A53
491 part, a load at EL0 from a virtual address that matches the bottom 32
492 bits of the virtual address used by a recent load at (AArch64) EL1
493 might return incorrect data.
495 The workaround is to write the contextidr_el1 register on exception
496 return to a 32-bit task.
497 Please note that this does not necessarily enable the workaround,
498 as it depends on the alternative framework, which will only patch
499 the kernel if an affected CPU is detected.
503 config ARM64_ERRATUM_843419
504 bool "Cortex-A53: 843419: A load or store might access an incorrect address"
506 select ARM64_MODULE_PLTS if MODULES
508 This option links the kernel with '--fix-cortex-a53-843419' and
509 enables PLT support to replace certain ADRP instructions, which can
510 cause subsequent memory accesses to use an incorrect address on
511 Cortex-A53 parts up to r0p4.
515 config ARM64_ERRATUM_1024718
516 bool "Cortex-A55: 1024718: Update of DBM/AP bits without break before make might result in incorrect update"
519 This option adds a workaround for ARM Cortex-A55 Erratum 1024718.
521 Affected Cortex-A55 cores (r0p0, r0p1, r1p0) could cause incorrect
522 update of the hardware dirty bit when the DBM/AP bits are updated
523 without a break-before-make. The workaround is to disable the usage
524 of hardware DBM locally on the affected cores. CPUs not affected by
525 this erratum will continue to use the feature.
529 config ARM64_ERRATUM_1418040
530 bool "Cortex-A76/Neoverse-N1: MRC read following MRRC read of specific Generic Timer in AArch32 might give incorrect result"
534 This option adds a workaround for ARM Cortex-A76/Neoverse-N1
535 errata 1188873 and 1418040.
537 Affected Cortex-A76/Neoverse-N1 cores (r0p0 to r3p1) could
538 cause register corruption when accessing the timer registers
539 from AArch32 userspace.
543 config ARM64_WORKAROUND_SPECULATIVE_AT
546 config ARM64_ERRATUM_1165522
547 bool "Cortex-A76: 1165522: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"
549 select ARM64_WORKAROUND_SPECULATIVE_AT
551 This option adds a workaround for ARM Cortex-A76 erratum 1165522.
553 Affected Cortex-A76 cores (r0p0, r1p0, r2p0) could end-up with
554 corrupted TLBs by speculating an AT instruction during a guest
559 config ARM64_ERRATUM_1319367
560 bool "Cortex-A57/A72: 1319537: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"
562 select ARM64_WORKAROUND_SPECULATIVE_AT
564 This option adds work arounds for ARM Cortex-A57 erratum 1319537
565 and A72 erratum 1319367
567 Cortex-A57 and A72 cores could end-up with corrupted TLBs by
568 speculating an AT instruction during a guest context switch.
572 config ARM64_ERRATUM_1530923
573 bool "Cortex-A55: 1530923: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"
575 select ARM64_WORKAROUND_SPECULATIVE_AT
577 This option adds a workaround for ARM Cortex-A55 erratum 1530923.
579 Affected Cortex-A55 cores (r0p0, r0p1, r1p0, r2p0) could end-up with
580 corrupted TLBs by speculating an AT instruction during a guest
585 config ARM64_WORKAROUND_REPEAT_TLBI
588 config ARM64_ERRATUM_1286807
589 bool "Cortex-A76: Modification of the translation table for a virtual address might lead to read-after-read ordering violation"
591 select ARM64_WORKAROUND_REPEAT_TLBI
593 This option adds a workaround for ARM Cortex-A76 erratum 1286807.
595 On the affected Cortex-A76 cores (r0p0 to r3p0), if a virtual
596 address for a cacheable mapping of a location is being
597 accessed by a core while another core is remapping the virtual
598 address to a new physical page using the recommended
599 break-before-make sequence, then under very rare circumstances
600 TLBI+DSB completes before a read using the translation being
601 invalidated has been observed by other observers. The
602 workaround repeats the TLBI+DSB operation.
604 config ARM64_ERRATUM_1463225
605 bool "Cortex-A76: Software Step might prevent interrupt recognition"
608 This option adds a workaround for Arm Cortex-A76 erratum 1463225.
610 On the affected Cortex-A76 cores (r0p0 to r3p1), software stepping
611 of a system call instruction (SVC) can prevent recognition of
612 subsequent interrupts when software stepping is disabled in the
613 exception handler of the system call and either kernel debugging
614 is enabled or VHE is in use.
616 Work around the erratum by triggering a dummy step exception
617 when handling a system call from a task that is being stepped
618 in a VHE configuration of the kernel.
622 config ARM64_ERRATUM_1542419
623 bool "Neoverse-N1: workaround mis-ordering of instruction fetches"
626 This option adds a workaround for ARM Neoverse-N1 erratum
629 Affected Neoverse-N1 cores could execute a stale instruction when
630 modified by another CPU. The workaround depends on a firmware
633 Workaround the issue by hiding the DIC feature from EL0. This
634 forces user-space to perform cache maintenance.
638 config CAVIUM_ERRATUM_22375
639 bool "Cavium erratum 22375, 24313"
642 Enable workaround for errata 22375 and 24313.
644 This implements two gicv3-its errata workarounds for ThunderX. Both
645 with a small impact affecting only ITS table allocation.
647 erratum 22375: only alloc 8MB table size
648 erratum 24313: ignore memory access type
650 The fixes are in ITS initialization and basically ignore memory access
651 type and table size provided by the TYPER and BASER registers.
655 config CAVIUM_ERRATUM_23144
656 bool "Cavium erratum 23144: ITS SYNC hang on dual socket system"
660 ITS SYNC command hang for cross node io and collections/cpu mapping.
664 config CAVIUM_ERRATUM_23154
665 bool "Cavium erratum 23154: Access to ICC_IAR1_EL1 is not sync'ed"
668 The gicv3 of ThunderX requires a modified version for
669 reading the IAR status to ensure data synchronization
670 (access to icc_iar1_el1 is not sync'ed before and after).
674 config CAVIUM_ERRATUM_27456
675 bool "Cavium erratum 27456: Broadcast TLBI instructions may cause icache corruption"
678 On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI
679 instructions may cause the icache to become corrupted if it
680 contains data for a non-current ASID. The fix is to
681 invalidate the icache when changing the mm context.
685 config CAVIUM_ERRATUM_30115
686 bool "Cavium erratum 30115: Guest may disable interrupts in host"
689 On ThunderX T88 pass 1.x through 2.2, T81 pass 1.0 through
690 1.2, and T83 Pass 1.0, KVM guest execution may disable
691 interrupts in host. Trapping both GICv3 group-0 and group-1
692 accesses sidesteps the issue.
696 config CAVIUM_TX2_ERRATUM_219
697 bool "Cavium ThunderX2 erratum 219: PRFM between TTBR change and ISB fails"
700 On Cavium ThunderX2, a load, store or prefetch instruction between a
701 TTBR update and the corresponding context synchronizing operation can
702 cause a spurious Data Abort to be delivered to any hardware thread in
705 Work around the issue by avoiding the problematic code sequence and
706 trapping KVM guest TTBRx_EL1 writes to EL2 when SMT is enabled. The
707 trap handler performs the corresponding register access, skips the
708 instruction and ensures context synchronization by virtue of the
713 config FUJITSU_ERRATUM_010001
714 bool "Fujitsu-A64FX erratum E#010001: Undefined fault may occur wrongly"
717 This option adds a workaround for Fujitsu-A64FX erratum E#010001.
718 On some variants of the Fujitsu-A64FX cores ver(1.0, 1.1), memory
719 accesses may cause undefined fault (Data abort, DFSC=0b111111).
720 This fault occurs under a specific hardware condition when a
721 load/store instruction performs an address translation using:
722 case-1 TTBR0_EL1 with TCR_EL1.NFD0 == 1.
723 case-2 TTBR0_EL2 with TCR_EL2.NFD0 == 1.
724 case-3 TTBR1_EL1 with TCR_EL1.NFD1 == 1.
725 case-4 TTBR1_EL2 with TCR_EL2.NFD1 == 1.
727 The workaround is to ensure these bits are clear in TCR_ELx.
728 The workaround only affects the Fujitsu-A64FX.
732 config HISILICON_ERRATUM_161600802
733 bool "Hip07 161600802: Erroneous redistributor VLPI base"
736 The HiSilicon Hip07 SoC uses the wrong redistributor base
737 when issued ITS commands such as VMOVP and VMAPP, and requires
738 a 128kB offset to be applied to the target address in this commands.
742 config QCOM_FALKOR_ERRATUM_1003
743 bool "Falkor E1003: Incorrect translation due to ASID change"
746 On Falkor v1, an incorrect ASID may be cached in the TLB when ASID
747 and BADDR are changed together in TTBRx_EL1. Since we keep the ASID
748 in TTBR1_EL1, this situation only occurs in the entry trampoline and
749 then only for entries in the walk cache, since the leaf translation
750 is unchanged. Work around the erratum by invalidating the walk cache
751 entries for the trampoline before entering the kernel proper.
753 config QCOM_FALKOR_ERRATUM_1009
754 bool "Falkor E1009: Prematurely complete a DSB after a TLBI"
756 select ARM64_WORKAROUND_REPEAT_TLBI
758 On Falkor v1, the CPU may prematurely complete a DSB following a
759 TLBI xxIS invalidate maintenance operation. Repeat the TLBI operation
760 one more time to fix the issue.
764 config QCOM_QDF2400_ERRATUM_0065
765 bool "QDF2400 E0065: Incorrect GITS_TYPER.ITT_Entry_size"
768 On Qualcomm Datacenter Technologies QDF2400 SoC, ITS hardware reports
769 ITE size incorrectly. The GITS_TYPER.ITT_Entry_size field should have
770 been indicated as 16Bytes (0xf), not 8Bytes (0x7).
774 config QCOM_FALKOR_ERRATUM_E1041
775 bool "Falkor E1041: Speculative instruction fetches might cause errant memory access"
778 Falkor CPU may speculatively fetch instructions from an improper
779 memory location when MMU translation is changed from SCTLR_ELn[M]=1
780 to SCTLR_ELn[M]=0. Prefix an ISB instruction to fix the problem.
784 config SOCIONEXT_SYNQUACER_PREITS
785 bool "Socionext Synquacer: Workaround for GICv3 pre-ITS"
788 Socionext Synquacer SoCs implement a separate h/w block to generate
789 MSI doorbell writes with non-zero values for the device ID.
798 default ARM64_4K_PAGES
800 Page size (translation granule) configuration.
802 config ARM64_4K_PAGES
805 This feature enables 4KB pages support.
807 config ARM64_16K_PAGES
810 The system will use 16KB pages support. AArch32 emulation
811 requires applications compiled with 16K (or a multiple of 16K)
814 config ARM64_64K_PAGES
817 This feature enables 64KB pages support (4KB by default)
818 allowing only two levels of page tables and faster TLB
819 look-up. AArch32 emulation requires applications compiled
820 with 64K aligned segments.
825 prompt "Virtual address space size"
826 default ARM64_VA_BITS_39 if ARM64_4K_PAGES
827 default ARM64_VA_BITS_47 if ARM64_16K_PAGES
828 default ARM64_VA_BITS_42 if ARM64_64K_PAGES
830 Allows choosing one of multiple possible virtual address
831 space sizes. The level of translation table is determined by
832 a combination of page size and virtual address space size.
834 config ARM64_VA_BITS_36
835 bool "36-bit" if EXPERT
836 depends on ARM64_16K_PAGES
838 config ARM64_VA_BITS_39
840 depends on ARM64_4K_PAGES
842 config ARM64_VA_BITS_42
844 depends on ARM64_64K_PAGES
846 config ARM64_VA_BITS_47
848 depends on ARM64_16K_PAGES
850 config ARM64_VA_BITS_48
853 config ARM64_VA_BITS_52
855 depends on ARM64_64K_PAGES && (ARM64_PAN || !ARM64_SW_TTBR0_PAN)
857 Enable 52-bit virtual addressing for userspace when explicitly
858 requested via a hint to mmap(). The kernel will also use 52-bit
859 virtual addresses for its own mappings (provided HW support for
860 this feature is available, otherwise it reverts to 48-bit).
862 NOTE: Enabling 52-bit virtual addressing in conjunction with
863 ARMv8.3 Pointer Authentication will result in the PAC being
864 reduced from 7 bits to 3 bits, which may have a significant
865 impact on its susceptibility to brute-force attacks.
867 If unsure, select 48-bit virtual addressing instead.
871 config ARM64_FORCE_52BIT
872 bool "Force 52-bit virtual addresses for userspace"
873 depends on ARM64_VA_BITS_52 && EXPERT
875 For systems with 52-bit userspace VAs enabled, the kernel will attempt
876 to maintain compatibility with older software by providing 48-bit VAs
877 unless a hint is supplied to mmap.
879 This configuration option disables the 48-bit compatibility logic, and
880 forces all userspace addresses to be 52-bit on HW that supports it. One
881 should only enable this configuration option for stress testing userspace
882 memory management code. If unsure say N here.
886 default 36 if ARM64_VA_BITS_36
887 default 39 if ARM64_VA_BITS_39
888 default 42 if ARM64_VA_BITS_42
889 default 47 if ARM64_VA_BITS_47
890 default 48 if ARM64_VA_BITS_48
891 default 52 if ARM64_VA_BITS_52
894 prompt "Physical address space size"
895 default ARM64_PA_BITS_48
897 Choose the maximum physical address range that the kernel will
900 config ARM64_PA_BITS_48
903 config ARM64_PA_BITS_52
904 bool "52-bit (ARMv8.2)"
905 depends on ARM64_64K_PAGES
906 depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN
908 Enable support for a 52-bit physical address space, introduced as
909 part of the ARMv8.2-LPA extension.
911 With this enabled, the kernel will also continue to work on CPUs that
912 do not support ARMv8.2-LPA, but with some added memory overhead (and
913 minor performance overhead).
919 default 48 if ARM64_PA_BITS_48
920 default 52 if ARM64_PA_BITS_52
924 default CPU_LITTLE_ENDIAN
926 Select the endianness of data accesses performed by the CPU. Userspace
927 applications will need to be compiled and linked for the endianness
928 that is selected here.
930 config CPU_BIG_ENDIAN
931 bool "Build big-endian kernel"
933 Say Y if you plan on running a kernel with a big-endian userspace.
935 config CPU_LITTLE_ENDIAN
936 bool "Build little-endian kernel"
938 Say Y if you plan on running a kernel with a little-endian userspace.
939 This is usually the case for distributions targeting arm64.
944 bool "Multi-core scheduler support"
946 Multi-core scheduler support improves the CPU scheduler's decision
947 making when dealing with multi-core CPU chips at a cost of slightly
948 increased overhead in some places. If unsure say N here.
951 bool "SMT scheduler support"
953 Improves the CPU scheduler's decision making when dealing with
954 MultiThreading at a cost of slightly increased overhead in some
955 places. If unsure say N here.
958 int "Maximum number of CPUs (2-4096)"
963 bool "Support for hot-pluggable CPUs"
964 select GENERIC_IRQ_MIGRATION
966 Say Y here to experiment with turning CPUs off and on. CPUs
967 can be controlled through /sys/devices/system/cpu.
969 # Common NUMA Features
971 bool "NUMA Memory Allocation and Scheduler Support"
972 select ACPI_NUMA if ACPI
975 Enable NUMA (Non-Uniform Memory Access) support.
977 The kernel will try to allocate memory used by a CPU on the
978 local memory of the CPU and add some more
979 NUMA awareness to the kernel.
982 int "Maximum NUMA Nodes (as a power of 2)"
985 depends on NEED_MULTIPLE_NODES
987 Specify the maximum number of NUMA Nodes available on the target
988 system. Increases memory reserved to accommodate various tables.
990 config USE_PERCPU_NUMA_NODE_ID
994 config HAVE_SETUP_PER_CPU_AREA
998 config NEED_PER_CPU_EMBED_FIRST_CHUNK
1002 config HOLES_IN_ZONE
1005 source "kernel/Kconfig.hz"
1007 config ARCH_SUPPORTS_DEBUG_PAGEALLOC
1010 config ARCH_SPARSEMEM_ENABLE
1012 select SPARSEMEM_VMEMMAP_ENABLE
1014 config ARCH_SPARSEMEM_DEFAULT
1015 def_bool ARCH_SPARSEMEM_ENABLE
1017 config ARCH_SELECT_MEMORY_MODEL
1018 def_bool ARCH_SPARSEMEM_ENABLE
1020 config ARCH_FLATMEM_ENABLE
1023 config HAVE_ARCH_PFN_VALID
1026 config HW_PERF_EVENTS
1030 config SYS_SUPPORTS_HUGETLBFS
1033 config ARCH_WANT_HUGE_PMD_SHARE
1035 config ARCH_HAS_CACHE_LINE_SIZE
1038 config ARCH_ENABLE_SPLIT_PMD_PTLOCK
1039 def_bool y if PGTABLE_LEVELS > 2
1041 # Supported by clang >= 7.0
1042 config CC_HAVE_SHADOW_CALL_STACK
1043 def_bool $(cc-option, -fsanitize=shadow-call-stack -ffixed-x18)
1046 bool "Enable paravirtualization code"
1048 This changes the kernel so it can modify itself when it is run
1049 under a hypervisor, potentially improving performance significantly
1050 over full virtualization.
1052 config PARAVIRT_TIME_ACCOUNTING
1053 bool "Paravirtual steal time accounting"
1056 Select this option to enable fine granularity task steal time
1057 accounting. Time spent executing other tasks in parallel with
1058 the current vCPU is discounted from the vCPU power. To account for
1059 that, there can be a small performance impact.
1061 If in doubt, say N here.
1064 depends on PM_SLEEP_SMP
1066 bool "kexec system call"
1068 kexec is a system call that implements the ability to shutdown your
1069 current kernel, and to start another kernel. It is like a reboot
1070 but it is independent of the system firmware. And like a reboot
1071 you can start any kernel with it, not just Linux.
1074 bool "kexec file based system call"
1077 This is new version of kexec system call. This system call is
1078 file based and takes file descriptors as system call argument
1079 for kernel and initramfs as opposed to list of segments as
1080 accepted by previous system call.
1083 bool "Verify kernel signature during kexec_file_load() syscall"
1084 depends on KEXEC_FILE
1086 Select this option to verify a signature with loaded kernel
1087 image. If configured, any attempt of loading a image without
1088 valid signature will fail.
1090 In addition to that option, you need to enable signature
1091 verification for the corresponding kernel image type being
1092 loaded in order for this to work.
1094 config KEXEC_IMAGE_VERIFY_SIG
1095 bool "Enable Image signature verification support"
1097 depends on KEXEC_SIG
1098 depends on EFI && SIGNED_PE_FILE_VERIFICATION
1100 Enable Image signature verification support.
1102 comment "Support for PE file signature verification disabled"
1103 depends on KEXEC_SIG
1104 depends on !EFI || !SIGNED_PE_FILE_VERIFICATION
1107 bool "Build kdump crash kernel"
1109 Generate crash dump after being started by kexec. This should
1110 be normally only set in special crash dump kernels which are
1111 loaded in the main kernel with kexec-tools into a specially
1112 reserved region and then later executed after a crash by
1115 For more details see Documentation/admin-guide/kdump/kdump.rst
1122 bool "Xen guest support on ARM64"
1123 depends on ARM64 && OF
1127 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64.
1129 config FORCE_MAX_ZONEORDER
1131 default "14" if (ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE)
1132 default "12" if (ARM64_16K_PAGES && TRANSPARENT_HUGEPAGE)
1135 The kernel memory allocator divides physically contiguous memory
1136 blocks into "zones", where each zone is a power of two number of
1137 pages. This option selects the largest power of two that the kernel
1138 keeps in the memory allocator. If you need to allocate very large
1139 blocks of physically contiguous memory, then you may need to
1140 increase this value.
1142 This config option is actually maximum order plus one. For example,
1143 a value of 11 means that the largest free memory block is 2^10 pages.
1145 We make sure that we can allocate upto a HugePage size for each configuration.
1147 MAX_ORDER = (PMD_SHIFT - PAGE_SHIFT) + 1 => PAGE_SHIFT - 2
1149 However for 4K, we choose a higher default value, 11 as opposed to 10, giving us
1150 4M allocations matching the default size used by generic code.
1152 config UNMAP_KERNEL_AT_EL0
1153 bool "Unmap kernel when running in userspace (aka \"KAISER\")" if EXPERT
1156 Speculation attacks against some high-performance processors can
1157 be used to bypass MMU permission checks and leak kernel data to
1158 userspace. This can be defended against by unmapping the kernel
1159 when running in userspace, mapping it back in on exception entry
1160 via a trampoline page in the vector table.
1164 config RODATA_FULL_DEFAULT_ENABLED
1165 bool "Apply r/o permissions of VM areas also to their linear aliases"
1168 Apply read-only attributes of VM areas to the linear alias of
1169 the backing pages as well. This prevents code or read-only data
1170 from being modified (inadvertently or intentionally) via another
1171 mapping of the same memory page. This additional enhancement can
1172 be turned off at runtime by passing rodata=[off|on] (and turned on
1173 with rodata=full if this option is set to 'n')
1175 This requires the linear region to be mapped down to pages,
1176 which may adversely affect performance in some cases.
1178 config ARM64_SW_TTBR0_PAN
1179 bool "Emulate Privileged Access Never using TTBR0_EL1 switching"
1181 Enabling this option prevents the kernel from accessing
1182 user-space memory directly by pointing TTBR0_EL1 to a reserved
1183 zeroed area and reserved ASID. The user access routines
1184 restore the valid TTBR0_EL1 temporarily.
1186 config ARM64_TAGGED_ADDR_ABI
1187 bool "Enable the tagged user addresses syscall ABI"
1190 When this option is enabled, user applications can opt in to a
1191 relaxed ABI via prctl() allowing tagged addresses to be passed
1192 to system calls as pointer arguments. For details, see
1193 Documentation/arm64/tagged-address-abi.rst.
1196 bool "Kernel support for 32-bit EL0"
1197 depends on ARM64_4K_PAGES || EXPERT
1198 select COMPAT_BINFMT_ELF if BINFMT_ELF
1200 select OLD_SIGSUSPEND3
1201 select COMPAT_OLD_SIGACTION
1203 This option enables support for a 32-bit EL0 running under a 64-bit
1204 kernel at EL1. AArch32-specific components such as system calls,
1205 the user helper functions, VFP support and the ptrace interface are
1206 handled appropriately by the kernel.
1208 If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware
1209 that you will only be able to execute AArch32 binaries that were compiled
1210 with page size aligned segments.
1212 If you want to execute 32-bit userspace applications, say Y.
1216 config KUSER_HELPERS
1217 bool "Enable kuser helpers page for 32-bit applications"
1220 Warning: disabling this option may break 32-bit user programs.
1222 Provide kuser helpers to compat tasks. The kernel provides
1223 helper code to userspace in read only form at a fixed location
1224 to allow userspace to be independent of the CPU type fitted to
1225 the system. This permits binaries to be run on ARMv4 through
1226 to ARMv8 without modification.
1228 See Documentation/arm/kernel_user_helpers.rst for details.
1230 However, the fixed address nature of these helpers can be used
1231 by ROP (return orientated programming) authors when creating
1234 If all of the binaries and libraries which run on your platform
1235 are built specifically for your platform, and make no use of
1236 these helpers, then you can turn this option off to hinder
1237 such exploits. However, in that case, if a binary or library
1238 relying on those helpers is run, it will not function correctly.
1240 Say N here only if you are absolutely certain that you do not
1241 need these helpers; otherwise, the safe option is to say Y.
1244 bool "Enable vDSO for 32-bit applications"
1245 depends on !CPU_BIG_ENDIAN && "$(CROSS_COMPILE_COMPAT)" != ""
1246 select GENERIC_COMPAT_VDSO
1249 Place in the process address space of 32-bit applications an
1250 ELF shared object providing fast implementations of gettimeofday
1253 You must have a 32-bit build of glibc 2.22 or later for programs
1254 to seamlessly take advantage of this.
1256 config THUMB2_COMPAT_VDSO
1257 bool "Compile the 32-bit vDSO for Thumb-2 mode" if EXPERT
1258 depends on COMPAT_VDSO
1261 Compile the compat vDSO with '-mthumb -fomit-frame-pointer' if y,
1262 otherwise with '-marm'.
1264 menuconfig ARMV8_DEPRECATED
1265 bool "Emulate deprecated/obsolete ARMv8 instructions"
1268 Legacy software support may require certain instructions
1269 that have been deprecated or obsoleted in the architecture.
1271 Enable this config to enable selective emulation of these
1278 config SWP_EMULATION
1279 bool "Emulate SWP/SWPB instructions"
1281 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that
1282 they are always undefined. Say Y here to enable software
1283 emulation of these instructions for userspace using LDXR/STXR.
1284 This feature can be controlled at runtime with the abi.swp
1285 sysctl which is disabled by default.
1287 In some older versions of glibc [<=2.8] SWP is used during futex
1288 trylock() operations with the assumption that the code will not
1289 be preempted. This invalid assumption may be more likely to fail
1290 with SWP emulation enabled, leading to deadlock of the user
1293 NOTE: when accessing uncached shared regions, LDXR/STXR rely
1294 on an external transaction monitoring block called a global
1295 monitor to maintain update atomicity. If your system does not
1296 implement a global monitor, this option can cause programs that
1297 perform SWP operations to uncached memory to deadlock.
1301 config CP15_BARRIER_EMULATION
1302 bool "Emulate CP15 Barrier instructions"
1304 The CP15 barrier instructions - CP15ISB, CP15DSB, and
1305 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
1306 strongly recommended to use the ISB, DSB, and DMB
1307 instructions instead.
1309 Say Y here to enable software emulation of these
1310 instructions for AArch32 userspace code. When this option is
1311 enabled, CP15 barrier usage is traced which can help
1312 identify software that needs updating. This feature can be
1313 controlled at runtime with the abi.cp15_barrier sysctl.
1317 config SETEND_EMULATION
1318 bool "Emulate SETEND instruction"
1320 The SETEND instruction alters the data-endianness of the
1321 AArch32 EL0, and is deprecated in ARMv8.
1323 Say Y here to enable software emulation of the instruction
1324 for AArch32 userspace code. This feature can be controlled
1325 at runtime with the abi.setend sysctl.
1327 Note: All the cpus on the system must have mixed endian support at EL0
1328 for this feature to be enabled. If a new CPU - which doesn't support mixed
1329 endian - is hotplugged in after this feature has been enabled, there could
1330 be unexpected results in the applications.
1337 menu "ARMv8.1 architectural features"
1339 config ARM64_HW_AFDBM
1340 bool "Support for hardware updates of the Access and Dirty page flags"
1343 The ARMv8.1 architecture extensions introduce support for
1344 hardware updates of the access and dirty information in page
1345 table entries. When enabled in TCR_EL1 (HA and HD bits) on
1346 capable processors, accesses to pages with PTE_AF cleared will
1347 set this bit instead of raising an access flag fault.
1348 Similarly, writes to read-only pages with the DBM bit set will
1349 clear the read-only bit (AP[2]) instead of raising a
1352 Kernels built with this configuration option enabled continue
1353 to work on pre-ARMv8.1 hardware and the performance impact is
1354 minimal. If unsure, say Y.
1357 bool "Enable support for Privileged Access Never (PAN)"
1360 Privileged Access Never (PAN; part of the ARMv8.1 Extensions)
1361 prevents the kernel or hypervisor from accessing user-space (EL0)
1364 Choosing this option will cause any unprotected (not using
1365 copy_to_user et al) memory access to fail with a permission fault.
1367 The feature is detected at runtime, and will remain as a 'nop'
1368 instruction if the cpu does not implement the feature.
1370 config ARM64_LSE_ATOMICS
1372 default ARM64_USE_LSE_ATOMICS
1373 depends on $(as-instr,.arch_extension lse)
1375 config ARM64_USE_LSE_ATOMICS
1376 bool "Atomic instructions"
1377 depends on JUMP_LABEL
1380 As part of the Large System Extensions, ARMv8.1 introduces new
1381 atomic instructions that are designed specifically to scale in
1384 Say Y here to make use of these instructions for the in-kernel
1385 atomic routines. This incurs a small overhead on CPUs that do
1386 not support these instructions and requires the kernel to be
1387 built with binutils >= 2.25 in order for the new instructions
1391 bool "Enable support for Virtualization Host Extensions (VHE)"
1394 Virtualization Host Extensions (VHE) allow the kernel to run
1395 directly at EL2 (instead of EL1) on processors that support
1396 it. This leads to better performance for KVM, as they reduce
1397 the cost of the world switch.
1399 Selecting this option allows the VHE feature to be detected
1400 at runtime, and does not affect processors that do not
1401 implement this feature.
1405 menu "ARMv8.2 architectural features"
1408 bool "Enable support for User Access Override (UAO)"
1411 User Access Override (UAO; part of the ARMv8.2 Extensions)
1412 causes the 'unprivileged' variant of the load/store instructions to
1413 be overridden to be privileged.
1415 This option changes get_user() and friends to use the 'unprivileged'
1416 variant of the load/store instructions. This ensures that user-space
1417 really did have access to the supplied memory. When addr_limit is
1418 set to kernel memory the UAO bit will be set, allowing privileged
1419 access to kernel memory.
1421 Choosing this option will cause copy_to_user() et al to use user-space
1424 The feature is detected at runtime, the kernel will use the
1425 regular load/store instructions if the cpu does not implement the
1429 bool "Enable support for persistent memory"
1430 select ARCH_HAS_PMEM_API
1431 select ARCH_HAS_UACCESS_FLUSHCACHE
1433 Say Y to enable support for the persistent memory API based on the
1434 ARMv8.2 DCPoP feature.
1436 The feature is detected at runtime, and the kernel will use DC CVAC
1437 operations if DC CVAP is not supported (following the behaviour of
1438 DC CVAP itself if the system does not define a point of persistence).
1440 config ARM64_RAS_EXTN
1441 bool "Enable support for RAS CPU Extensions"
1444 CPUs that support the Reliability, Availability and Serviceability
1445 (RAS) Extensions, part of ARMv8.2 are able to track faults and
1446 errors, classify them and report them to software.
1448 On CPUs with these extensions system software can use additional
1449 barriers to determine if faults are pending and read the
1450 classification from a new set of registers.
1452 Selecting this feature will allow the kernel to use these barriers
1453 and access the new registers if the system supports the extension.
1454 Platform RAS features may additionally depend on firmware support.
1457 bool "Enable support for Common Not Private (CNP) translations"
1459 depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN
1461 Common Not Private (CNP) allows translation table entries to
1462 be shared between different PEs in the same inner shareable
1463 domain, so the hardware can use this fact to optimise the
1464 caching of such entries in the TLB.
1466 Selecting this option allows the CNP feature to be detected
1467 at runtime, and does not affect PEs that do not implement
1472 menu "ARMv8.3 architectural features"
1474 config ARM64_PTR_AUTH
1475 bool "Enable support for pointer authentication"
1477 depends on (CC_HAS_SIGN_RETURN_ADDRESS || CC_HAS_BRANCH_PROT_PAC_RET) && AS_HAS_PAC
1478 # Modern compilers insert a .note.gnu.property section note for PAC
1479 # which is only understood by binutils starting with version 2.33.1.
1480 depends on LD_IS_LLD || LD_VERSION >= 233010000 || (CC_IS_GCC && GCC_VERSION < 90100)
1481 depends on !CC_IS_CLANG || AS_HAS_CFI_NEGATE_RA_STATE
1482 depends on (!FUNCTION_GRAPH_TRACER || DYNAMIC_FTRACE_WITH_REGS)
1484 Pointer authentication (part of the ARMv8.3 Extensions) provides
1485 instructions for signing and authenticating pointers against secret
1486 keys, which can be used to mitigate Return Oriented Programming (ROP)
1489 This option enables these instructions at EL0 (i.e. for userspace).
1490 Choosing this option will cause the kernel to initialise secret keys
1491 for each process at exec() time, with these keys being
1492 context-switched along with the process.
1494 If the compiler supports the -mbranch-protection or
1495 -msign-return-address flag (e.g. GCC 7 or later), then this option
1496 will also cause the kernel itself to be compiled with return address
1497 protection. In this case, and if the target hardware is known to
1498 support pointer authentication, then CONFIG_STACKPROTECTOR can be
1499 disabled with minimal loss of protection.
1501 The feature is detected at runtime. If the feature is not present in
1502 hardware it will not be advertised to userspace/KVM guest nor will it
1505 If the feature is present on the boot CPU but not on a late CPU, then
1506 the late CPU will be parked. Also, if the boot CPU does not have
1507 address auth and the late CPU has then the late CPU will still boot
1508 but with the feature disabled. On such a system, this option should
1511 This feature works with FUNCTION_GRAPH_TRACER option only if
1512 DYNAMIC_FTRACE_WITH_REGS is enabled.
1514 config CC_HAS_BRANCH_PROT_PAC_RET
1515 # GCC 9 or later, clang 8 or later
1516 def_bool $(cc-option,-mbranch-protection=pac-ret+leaf)
1518 config CC_HAS_SIGN_RETURN_ADDRESS
1520 def_bool $(cc-option,-msign-return-address=all)
1523 def_bool $(cc-option,-Wa$(comma)-march=armv8.3-a)
1525 config AS_HAS_CFI_NEGATE_RA_STATE
1526 def_bool $(as-instr,.cfi_startproc\n.cfi_negate_ra_state\n.cfi_endproc\n)
1530 menu "ARMv8.4 architectural features"
1532 config ARM64_AMU_EXTN
1533 bool "Enable support for the Activity Monitors Unit CPU extension"
1536 The activity monitors extension is an optional extension introduced
1537 by the ARMv8.4 CPU architecture. This enables support for version 1
1538 of the activity monitors architecture, AMUv1.
1540 To enable the use of this extension on CPUs that implement it, say Y.
1542 Note that for architectural reasons, firmware _must_ implement AMU
1543 support when running on CPUs that present the activity monitors
1544 extension. The required support is present in:
1545 * Version 1.5 and later of the ARM Trusted Firmware
1547 For kernels that have this configuration enabled but boot with broken
1548 firmware, you may need to say N here until the firmware is fixed.
1549 Otherwise you may experience firmware panics or lockups when
1550 accessing the counter registers. Even if you are not observing these
1551 symptoms, the values returned by the register reads might not
1552 correctly reflect reality. Most commonly, the value read will be 0,
1553 indicating that the counter is not enabled.
1555 config AS_HAS_ARMV8_4
1556 def_bool $(cc-option,-Wa$(comma)-march=armv8.4-a)
1558 config ARM64_TLB_RANGE
1559 bool "Enable support for tlbi range feature"
1561 depends on AS_HAS_ARMV8_4
1563 ARMv8.4-TLBI provides TLBI invalidation instruction that apply to a
1564 range of input addresses.
1566 The feature introduces new assembly instructions, and they were
1567 support when binutils >= 2.30.
1571 menu "ARMv8.5 architectural features"
1574 bool "Branch Target Identification support"
1577 Branch Target Identification (part of the ARMv8.5 Extensions)
1578 provides a mechanism to limit the set of locations to which computed
1579 branch instructions such as BR or BLR can jump.
1581 To make use of BTI on CPUs that support it, say Y.
1583 BTI is intended to provide complementary protection to other control
1584 flow integrity protection mechanisms, such as the Pointer
1585 authentication mechanism provided as part of the ARMv8.3 Extensions.
1586 For this reason, it does not make sense to enable this option without
1587 also enabling support for pointer authentication. Thus, when
1588 enabling this option you should also select ARM64_PTR_AUTH=y.
1590 Userspace binaries must also be specifically compiled to make use of
1591 this mechanism. If you say N here or the hardware does not support
1592 BTI, such binaries can still run, but you get no additional
1593 enforcement of branch destinations.
1595 config ARM64_BTI_KERNEL
1596 bool "Use Branch Target Identification for kernel"
1598 depends on ARM64_BTI
1599 depends on ARM64_PTR_AUTH
1600 depends on CC_HAS_BRANCH_PROT_PAC_RET_BTI
1601 # https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94697
1602 depends on !CC_IS_GCC || GCC_VERSION >= 100100
1603 depends on !(CC_IS_CLANG && GCOV_KERNEL)
1604 depends on (!FUNCTION_GRAPH_TRACER || DYNAMIC_FTRACE_WITH_REGS)
1606 Build the kernel with Branch Target Identification annotations
1607 and enable enforcement of this for kernel code. When this option
1608 is enabled and the system supports BTI all kernel code including
1609 modular code must have BTI enabled.
1611 config CC_HAS_BRANCH_PROT_PAC_RET_BTI
1612 # GCC 9 or later, clang 8 or later
1613 def_bool $(cc-option,-mbranch-protection=pac-ret+leaf+bti)
1616 bool "Enable support for E0PD"
1619 E0PD (part of the ARMv8.5 extensions) allows us to ensure
1620 that EL0 accesses made via TTBR1 always fault in constant time,
1621 providing similar benefits to KASLR as those provided by KPTI, but
1622 with lower overhead and without disrupting legitimate access to
1623 kernel memory such as SPE.
1625 This option enables E0PD for TTBR1 where available.
1628 bool "Enable support for random number generation"
1631 Random number generation (part of the ARMv8.5 Extensions)
1632 provides a high bandwidth, cryptographically secure
1633 hardware random number generator.
1635 config ARM64_AS_HAS_MTE
1636 # Initial support for MTE went in binutils 2.32.0, checked with
1637 # ".arch armv8.5-a+memtag" below. However, this was incomplete
1638 # as a late addition to the final architecture spec (LDGM/STGM)
1639 # is only supported in the newer 2.32.x and 2.33 binutils
1640 # versions, hence the extra "stgm" instruction check below.
1641 def_bool $(as-instr,.arch armv8.5-a+memtag\nstgm xzr$(comma)[x0])
1644 bool "Memory Tagging Extension support"
1646 depends on ARM64_AS_HAS_MTE && ARM64_TAGGED_ADDR_ABI
1647 select ARCH_USES_HIGH_VMA_FLAGS
1649 Memory Tagging (part of the ARMv8.5 Extensions) provides
1650 architectural support for run-time, always-on detection of
1651 various classes of memory error to aid with software debugging
1652 to eliminate vulnerabilities arising from memory-unsafe
1655 This option enables the support for the Memory Tagging
1656 Extension at EL0 (i.e. for userspace).
1658 Selecting this option allows the feature to be detected at
1659 runtime. Any secondary CPU not implementing this feature will
1660 not be allowed a late bring-up.
1662 Userspace binaries that want to use this feature must
1663 explicitly opt in. The mechanism for the userspace is
1666 Documentation/arm64/memory-tagging-extension.rst.
1671 bool "ARM Scalable Vector Extension support"
1673 depends on !KVM || ARM64_VHE
1675 The Scalable Vector Extension (SVE) is an extension to the AArch64
1676 execution state which complements and extends the SIMD functionality
1677 of the base architecture to support much larger vectors and to enable
1678 additional vectorisation opportunities.
1680 To enable use of this extension on CPUs that implement it, say Y.
1682 On CPUs that support the SVE2 extensions, this option will enable
1685 Note that for architectural reasons, firmware _must_ implement SVE
1686 support when running on SVE capable hardware. The required support
1689 * version 1.5 and later of the ARM Trusted Firmware
1690 * the AArch64 boot wrapper since commit 5e1261e08abf
1691 ("bootwrapper: SVE: Enable SVE for EL2 and below").
1693 For other firmware implementations, consult the firmware documentation
1696 If you need the kernel to boot on SVE-capable hardware with broken
1697 firmware, you may need to say N here until you get your firmware
1698 fixed. Otherwise, you may experience firmware panics or lockups when
1699 booting the kernel. If unsure and you are not observing these
1700 symptoms, you should assume that it is safe to say Y.
1702 CPUs that support SVE are architecturally required to support the
1703 Virtualization Host Extensions (VHE), so the kernel makes no
1704 provision for supporting SVE alongside KVM without VHE enabled.
1705 Thus, you will need to enable CONFIG_ARM64_VHE if you want to support
1706 KVM in the same kernel image.
1708 config ARM64_MODULE_PLTS
1709 bool "Use PLTs to allow module memory to spill over into vmalloc area"
1711 select HAVE_MOD_ARCH_SPECIFIC
1713 Allocate PLTs when loading modules so that jumps and calls whose
1714 targets are too far away for their relative offsets to be encoded
1715 in the instructions themselves can be bounced via veneers in the
1716 module's PLT. This allows modules to be allocated in the generic
1717 vmalloc area after the dedicated module memory area has been
1720 When running with address space randomization (KASLR), the module
1721 region itself may be too far away for ordinary relative jumps and
1722 calls, and so in that case, module PLTs are required and cannot be
1725 Specific errata workaround(s) might also force module PLTs to be
1726 enabled (ARM64_ERRATUM_843419).
1728 config ARM64_PSEUDO_NMI
1729 bool "Support for NMI-like interrupts"
1732 Adds support for mimicking Non-Maskable Interrupts through the use of
1733 GIC interrupt priority. This support requires version 3 or later of
1736 This high priority configuration for interrupts needs to be
1737 explicitly enabled by setting the kernel parameter
1738 "irqchip.gicv3_pseudo_nmi" to 1.
1743 config ARM64_DEBUG_PRIORITY_MASKING
1744 bool "Debug interrupt priority masking"
1746 This adds runtime checks to functions enabling/disabling
1747 interrupts when using priority masking. The additional checks verify
1748 the validity of ICC_PMR_EL1 when calling concerned functions.
1754 bool "Build a relocatable kernel image" if EXPERT
1755 select ARCH_HAS_RELR
1758 This builds the kernel as a Position Independent Executable (PIE),
1759 which retains all relocation metadata required to relocate the
1760 kernel binary at runtime to a different virtual address than the
1761 address it was linked at.
1762 Since AArch64 uses the RELA relocation format, this requires a
1763 relocation pass at runtime even if the kernel is loaded at the
1764 same address it was linked at.
1766 config RANDOMIZE_BASE
1767 bool "Randomize the address of the kernel image"
1768 select ARM64_MODULE_PLTS if MODULES
1771 Randomizes the virtual address at which the kernel image is
1772 loaded, as a security feature that deters exploit attempts
1773 relying on knowledge of the location of kernel internals.
1775 It is the bootloader's job to provide entropy, by passing a
1776 random u64 value in /chosen/kaslr-seed at kernel entry.
1778 When booting via the UEFI stub, it will invoke the firmware's
1779 EFI_RNG_PROTOCOL implementation (if available) to supply entropy
1780 to the kernel proper. In addition, it will randomise the physical
1781 location of the kernel Image as well.
1785 config RANDOMIZE_MODULE_REGION_FULL
1786 bool "Randomize the module region over a 4 GB range"
1787 depends on RANDOMIZE_BASE
1790 Randomizes the location of the module region inside a 4 GB window
1791 covering the core kernel. This way, it is less likely for modules
1792 to leak information about the location of core kernel data structures
1793 but it does imply that function calls between modules and the core
1794 kernel will need to be resolved via veneers in the module PLT.
1796 When this option is not set, the module region will be randomized over
1797 a limited range that contains the [_stext, _etext] interval of the
1798 core kernel, so branch relocations are always in range.
1800 config CC_HAVE_STACKPROTECTOR_SYSREG
1801 def_bool $(cc-option,-mstack-protector-guard=sysreg -mstack-protector-guard-reg=sp_el0 -mstack-protector-guard-offset=0)
1803 config STACKPROTECTOR_PER_TASK
1805 depends on STACKPROTECTOR && CC_HAVE_STACKPROTECTOR_SYSREG
1811 config ARM64_ACPI_PARKING_PROTOCOL
1812 bool "Enable support for the ARM64 ACPI parking protocol"
1815 Enable support for the ARM64 ACPI parking protocol. If disabled
1816 the kernel will not allow booting through the ARM64 ACPI parking
1817 protocol even if the corresponding data is present in the ACPI
1821 string "Default kernel command string"
1824 Provide a set of default command-line options at build time by
1825 entering them here. As a minimum, you should specify the the
1826 root device (e.g. root=/dev/nfs).
1828 config CMDLINE_FORCE
1829 bool "Always use the default kernel command string"
1830 depends on CMDLINE != ""
1832 Always use the default kernel command string, even if the boot
1833 loader passes other arguments to the kernel.
1834 This is useful if you cannot or don't want to change the
1835 command-line options your boot loader passes to the kernel.
1841 bool "UEFI runtime support"
1842 depends on OF && !CPU_BIG_ENDIAN
1843 depends on KERNEL_MODE_NEON
1844 select ARCH_SUPPORTS_ACPI
1847 select EFI_PARAMS_FROM_FDT
1848 select EFI_RUNTIME_WRAPPERS
1850 select EFI_GENERIC_STUB
1853 This option provides support for runtime services provided
1854 by UEFI firmware (such as non-volatile variables, realtime
1855 clock, and platform reset). A UEFI stub is also provided to
1856 allow the kernel to be booted as an EFI application. This
1857 is only useful on systems that have UEFI firmware.
1860 bool "Enable support for SMBIOS (DMI) tables"
1864 This enables SMBIOS/DMI feature for systems.
1866 This option is only useful on systems that have UEFI firmware.
1867 However, even with this option, the resultant kernel should
1868 continue to boot on existing non-UEFI platforms.
1872 config SYSVIPC_COMPAT
1874 depends on COMPAT && SYSVIPC
1876 config ARCH_ENABLE_HUGEPAGE_MIGRATION
1878 depends on HUGETLB_PAGE && MIGRATION
1880 config ARCH_ENABLE_THP_MIGRATION
1882 depends on TRANSPARENT_HUGEPAGE
1884 menu "Power management options"
1886 source "kernel/power/Kconfig"
1888 config ARCH_HIBERNATION_POSSIBLE
1892 config ARCH_HIBERNATION_HEADER
1894 depends on HIBERNATION
1896 config ARCH_SUSPEND_POSSIBLE
1901 menu "CPU Power Management"
1903 source "drivers/cpuidle/Kconfig"
1905 source "drivers/cpufreq/Kconfig"
1909 source "drivers/firmware/Kconfig"
1911 source "drivers/acpi/Kconfig"
1913 source "arch/arm64/kvm/Kconfig"
1916 source "arch/arm64/crypto/Kconfig"