arch/arm/mach-omap2/omap_hwmod_44xx_data.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Hardware modules present on the OMAP44xx chips
   4  *
   5  * Copyright (C) 2009-2012 Texas Instruments, Inc.
   6  * Copyright (C) 2009-2010 Nokia Corporation
   7  *
   8  * Paul Walmsley
   9  * Benoit Cousson
  10  *
  11  * This file is automatically generated from the OMAP hardware databases.
  12  * We respectfully ask that any modifications to this file be coordinated
  13  * with the public linux-omap@vger.kernel.org mailing list and the
  14  * authors above to ensure that the autogeneration scripts are kept
  15  * up-to-date with the file contents.
  16  * Note that this file is currently not in sync with autogeneration scripts.
  17  * The above note to be removed, once it is synced up.
  18  */
  19
  20 #include <linux/io.h>
  21
  22 #include "omap_hwmod.h"
  23 #include "omap_hwmod_common_data.h"
  24 #include "cm1_44xx.h"
  25 #include "cm2_44xx.h"
  26 #include "prm44xx.h"
  27 #include "prm-regbits-44xx.h"
  28
  29 /* Base offset for all OMAP4 interrupts external to MPUSS */
  30 #define OMAP44XX_IRQ_GIC_START  32
  31
  32 /*
  33  * IP blocks
  34  */
  35
  36 /*
  37  * 'dmm' class
  38  * instance(s): dmm
  39  */
  40 static struct omap_hwmod_class omap44xx_dmm_hwmod_class = {
  41         .name   = "dmm",
  42 };
  43
  44 /* dmm */
  45 static struct omap_hwmod omap44xx_dmm_hwmod = {
  46         .name           = "dmm",
  47         .class          = &omap44xx_dmm_hwmod_class,
  48         .clkdm_name     = "l3_emif_clkdm",
  49         .prcm = {
  50                 .omap4 = {
  51                         .clkctrl_offs = OMAP4_CM_MEMIF_DMM_CLKCTRL_OFFSET,
  52                         .context_offs = OMAP4_RM_MEMIF_DMM_CONTEXT_OFFSET,
  53                 },
  54         },
  55 };
  56
  57 /*
  58  * 'l3' class
  59  * instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3
  60  */
  61 static struct omap_hwmod_class omap44xx_l3_hwmod_class = {
  62         .name   = "l3",
  63 };
  64
  65 /* l3_instr */
  66 static struct omap_hwmod omap44xx_l3_instr_hwmod = {
  67         .name           = "l3_instr",
  68         .class          = &omap44xx_l3_hwmod_class,
  69         .clkdm_name     = "l3_instr_clkdm",
  70         .prcm = {
  71                 .omap4 = {
  72                         .clkctrl_offs = OMAP4_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET,
  73                         .context_offs = OMAP4_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET,
  74                         .modulemode   = MODULEMODE_HWCTRL,
  75                 },
  76         },
  77 };
  78
  79 /* l3_main_1 */
  80 static struct omap_hwmod omap44xx_l3_main_1_hwmod = {
  81         .name           = "l3_main_1",
  82         .class          = &omap44xx_l3_hwmod_class,
  83         .clkdm_name     = "l3_1_clkdm",
  84         .prcm = {
  85                 .omap4 = {
  86                         .clkctrl_offs = OMAP4_CM_L3_1_L3_1_CLKCTRL_OFFSET,
  87                         .context_offs = OMAP4_RM_L3_1_L3_1_CONTEXT_OFFSET,
  88                 },
  89         },
  90 };
  91
  92 /* l3_main_2 */
  93 static struct omap_hwmod omap44xx_l3_main_2_hwmod = {
  94         .name           = "l3_main_2",
  95         .class          = &omap44xx_l3_hwmod_class,
  96         .clkdm_name     = "l3_2_clkdm",
  97         .prcm = {
  98                 .omap4 = {
  99                         .clkctrl_offs = OMAP4_CM_L3_2_L3_2_CLKCTRL_OFFSET,
 100                         .context_offs = OMAP4_RM_L3_2_L3_2_CONTEXT_OFFSET,
 101                 },
 102         },
 103 };
 104
 105 /* l3_main_3 */
 106 static struct omap_hwmod omap44xx_l3_main_3_hwmod = {
 107         .name           = "l3_main_3",
 108         .class          = &omap44xx_l3_hwmod_class,
 109         .clkdm_name     = "l3_instr_clkdm",
 110         .prcm = {
 111                 .omap4 = {
 112                         .clkctrl_offs = OMAP4_CM_L3INSTR_L3_3_CLKCTRL_OFFSET,
 113                         .context_offs = OMAP4_RM_L3INSTR_L3_3_CONTEXT_OFFSET,
 114                         .modulemode   = MODULEMODE_HWCTRL,
 115                 },
 116         },
 117 };
 118
 119 /*
 120  * 'l4' class
 121  * instance(s): l4_abe, l4_cfg, l4_per, l4_wkup
 122  */
 123 static struct omap_hwmod_class omap44xx_l4_hwmod_class = {
 124         .name   = "l4",
 125 };
 126
 127 /* l4_cfg */
 128 static struct omap_hwmod omap44xx_l4_cfg_hwmod = {
 129         .name           = "l4_cfg",
 130         .class          = &omap44xx_l4_hwmod_class,
 131         .clkdm_name     = "l4_cfg_clkdm",
 132         .prcm = {
 133                 .omap4 = {
 134                         .clkctrl_offs = OMAP4_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET,
 135                         .context_offs = OMAP4_RM_L4CFG_L4_CFG_CONTEXT_OFFSET,
 136                 },
 137         },
 138 };
 139
 140 /* l4_per */
 141 static struct omap_hwmod omap44xx_l4_per_hwmod = {
 142         .name           = "l4_per",
 143         .class          = &omap44xx_l4_hwmod_class,
 144         .clkdm_name     = "l4_per_clkdm",
 145         .prcm = {
 146                 .omap4 = {
 147                         .clkctrl_offs = OMAP4_CM_L4PER_L4PER_CLKCTRL_OFFSET,
 148                         .context_offs = OMAP4_RM_L4PER_L4_PER_CONTEXT_OFFSET,
 149                 },
 150         },
 151 };
 152
 153 /* l4_wkup */
 154 static struct omap_hwmod omap44xx_l4_wkup_hwmod = {
 155         .name           = "l4_wkup",
 156         .class          = &omap44xx_l4_hwmod_class,
 157         .clkdm_name     = "l4_wkup_clkdm",
 158         .prcm = {
 159                 .omap4 = {
 160                         .clkctrl_offs = OMAP4_CM_WKUP_L4WKUP_CLKCTRL_OFFSET,
 161                         .context_offs = OMAP4_RM_WKUP_L4WKUP_CONTEXT_OFFSET,
 162                 },
 163         },
 164 };
 165
 166 /*
 167  * 'mpu_bus' class
 168  * instance(s): mpu_private
 169  */
 170 static struct omap_hwmod_class omap44xx_mpu_bus_hwmod_class = {
 171         .name   = "mpu_bus",
 172 };
 173
 174 /* mpu_private */
 175 static struct omap_hwmod omap44xx_mpu_private_hwmod = {
 176         .name           = "mpu_private",
 177         .class          = &omap44xx_mpu_bus_hwmod_class,
 178         .clkdm_name     = "mpuss_clkdm",
 179         .prcm = {
 180                 .omap4 = {
 181                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 182                 },
 183         },
 184 };
 185
 186 /*
 187  * 'ocp_wp_noc' class
 188  * instance(s): ocp_wp_noc
 189  */
 190 static struct omap_hwmod_class omap44xx_ocp_wp_noc_hwmod_class = {
 191         .name   = "ocp_wp_noc",
 192 };
 193
 194 /* ocp_wp_noc */
 195 static struct omap_hwmod omap44xx_ocp_wp_noc_hwmod = {
 196         .name           = "ocp_wp_noc",
 197         .class          = &omap44xx_ocp_wp_noc_hwmod_class,
 198         .clkdm_name     = "l3_instr_clkdm",
 199         .prcm = {
 200                 .omap4 = {
 201                         .clkctrl_offs = OMAP4_CM_L3INSTR_OCP_WP1_CLKCTRL_OFFSET,
 202                         .context_offs = OMAP4_RM_L3INSTR_OCP_WP1_CONTEXT_OFFSET,
 203                         .modulemode   = MODULEMODE_HWCTRL,
 204                 },
 205         },
 206 };
 207
 208 /*
 209  * Modules omap_hwmod structures
 210  *
 211  * The following IPs are excluded for the moment because:
 212  * - They do not need an explicit SW control using omap_hwmod API.
 213  * - They still need to be validated with the driver
 214  *   properly adapted to omap_hwmod / omap_device
 215  *
 216  * usim
 217  */
 218
 219 /*
 220  * 'ctrl_module' class
 221  * attila core control module + core pad control module + wkup pad control
 222  * module + attila wkup control module
 223  */
 224
 225 static struct omap_hwmod_class_sysconfig omap44xx_ctrl_module_sysc = {
 226         .rev_offs       = 0x0000,
 227         .sysc_offs      = 0x0010,
 228         .sysc_flags     = SYSC_HAS_SIDLEMODE,
 229         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 230                            SIDLE_SMART_WKUP),
 231         .sysc_fields    = &omap_hwmod_sysc_type2,
 232 };
 233
 234 static struct omap_hwmod_class omap44xx_ctrl_module_hwmod_class = {
 235         .name   = "ctrl_module",
 236         .sysc   = &omap44xx_ctrl_module_sysc,
 237 };
 238
 239 /* ctrl_module_core */
 240 static struct omap_hwmod omap44xx_ctrl_module_core_hwmod = {
 241         .name           = "ctrl_module_core",
 242         .class          = &omap44xx_ctrl_module_hwmod_class,
 243         .clkdm_name     = "l4_cfg_clkdm",
 244         .prcm = {
 245                 .omap4 = {
 246                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 247                 },
 248         },
 249 };
 250
 251 /* ctrl_module_pad_core */
 252 static struct omap_hwmod omap44xx_ctrl_module_pad_core_hwmod = {
 253         .name           = "ctrl_module_pad_core",
 254         .class          = &omap44xx_ctrl_module_hwmod_class,
 255         .clkdm_name     = "l4_cfg_clkdm",
 256         .prcm = {
 257                 .omap4 = {
 258                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 259                 },
 260         },
 261 };
 262
 263 /* ctrl_module_wkup */
 264 static struct omap_hwmod omap44xx_ctrl_module_wkup_hwmod = {
 265         .name           = "ctrl_module_wkup",
 266         .class          = &omap44xx_ctrl_module_hwmod_class,
 267         .clkdm_name     = "l4_wkup_clkdm",
 268         .prcm = {
 269                 .omap4 = {
 270                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 271                 },
 272         },
 273 };
 274
 275 /* ctrl_module_pad_wkup */
 276 static struct omap_hwmod omap44xx_ctrl_module_pad_wkup_hwmod = {
 277         .name           = "ctrl_module_pad_wkup",
 278         .class          = &omap44xx_ctrl_module_hwmod_class,
 279         .clkdm_name     = "l4_wkup_clkdm",
 280         .prcm = {
 281                 .omap4 = {
 282                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 283                 },
 284         },
 285 };
 286
 287 /*
 288  * 'debugss' class
 289  * debug and emulation sub system
 290  */
 291
 292 static struct omap_hwmod_class omap44xx_debugss_hwmod_class = {
 293         .name   = "debugss",
 294 };
 295
 296 /* debugss */
 297 static struct omap_hwmod omap44xx_debugss_hwmod = {
 298         .name           = "debugss",
 299         .class          = &omap44xx_debugss_hwmod_class,
 300         .clkdm_name     = "emu_sys_clkdm",
 301         .main_clk       = "trace_clk_div_ck",
 302         .prcm = {
 303                 .omap4 = {
 304                         .clkctrl_offs = OMAP4_CM_EMU_DEBUGSS_CLKCTRL_OFFSET,
 305                         .context_offs = OMAP4_RM_EMU_DEBUGSS_CONTEXT_OFFSET,
 306                 },
 307         },
 308 };
 309
 310 /*
 311  * 'emif' class
 312  * external memory interface no1
 313  */
 314
 315 static struct omap_hwmod_class_sysconfig omap44xx_emif_sysc = {
 316         .rev_offs       = 0x0000,
 317 };
 318
 319 static struct omap_hwmod_class omap44xx_emif_hwmod_class = {
 320         .name   = "emif",
 321         .sysc   = &omap44xx_emif_sysc,
 322 };
 323
 324 /* emif1 */
 325 static struct omap_hwmod omap44xx_emif1_hwmod = {
 326         .name           = "emif1",
 327         .class          = &omap44xx_emif_hwmod_class,
 328         .clkdm_name     = "l3_emif_clkdm",
 329         .flags          = HWMOD_INIT_NO_IDLE,
 330         .main_clk       = "ddrphy_ck",
 331         .prcm = {
 332                 .omap4 = {
 333                         .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_1_CLKCTRL_OFFSET,
 334                         .context_offs = OMAP4_RM_MEMIF_EMIF_1_CONTEXT_OFFSET,
 335                         .modulemode   = MODULEMODE_HWCTRL,
 336                 },
 337         },
 338 };
 339
 340 /* emif2 */
 341 static struct omap_hwmod omap44xx_emif2_hwmod = {
 342         .name           = "emif2",
 343         .class          = &omap44xx_emif_hwmod_class,
 344         .clkdm_name     = "l3_emif_clkdm",
 345         .flags          = HWMOD_INIT_NO_IDLE,
 346         .main_clk       = "ddrphy_ck",
 347         .prcm = {
 348                 .omap4 = {
 349                         .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_2_CLKCTRL_OFFSET,
 350                         .context_offs = OMAP4_RM_MEMIF_EMIF_2_CONTEXT_OFFSET,
 351                         .modulemode   = MODULEMODE_HWCTRL,
 352                 },
 353         },
 354 };
 355
 356 /*
 357  * 'gpmc' class
 358  * general purpose memory controller
 359  */
 360
 361 static struct omap_hwmod_class_sysconfig omap44xx_gpmc_sysc = {
 362         .rev_offs       = 0x0000,
 363         .sysc_offs      = 0x0010,
 364         .syss_offs      = 0x0014,
 365         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
 366                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
 367         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 368         .sysc_fields    = &omap_hwmod_sysc_type1,
 369 };
 370
 371 static struct omap_hwmod_class omap44xx_gpmc_hwmod_class = {
 372         .name   = "gpmc",
 373         .sysc   = &omap44xx_gpmc_sysc,
 374 };
 375
 376 /* gpmc */
 377 static struct omap_hwmod omap44xx_gpmc_hwmod = {
 378         .name           = "gpmc",
 379         .class          = &omap44xx_gpmc_hwmod_class,
 380         .clkdm_name     = "l3_2_clkdm",
 381         /* Skip reset for CONFIG_OMAP_GPMC_DEBUG for bootloader timings */
 382         .flags          = DEBUG_OMAP_GPMC_HWMOD_FLAGS,
 383         .prcm = {
 384                 .omap4 = {
 385                         .clkctrl_offs = OMAP4_CM_L3_2_GPMC_CLKCTRL_OFFSET,
 386                         .context_offs = OMAP4_RM_L3_2_GPMC_CONTEXT_OFFSET,
 387                         .modulemode   = MODULEMODE_HWCTRL,
 388                 },
 389         },
 390 };
 391
 392 /*
 393  * 'iss' class
 394  * external images sensor pixel data processor
 395  */
 396
 397 static struct omap_hwmod_class_sysconfig omap44xx_iss_sysc = {
 398         .rev_offs       = 0x0000,
 399         .sysc_offs      = 0x0010,
 400         /*
 401          * ISS needs 100 OCP clk cycles delay after a softreset before
 402          * accessing sysconfig again.
 403          * The lowest frequency at the moment for L3 bus is 100 MHz, so
 404          * 1usec delay is needed. Add an x2 margin to be safe (2 usecs).
 405          *
 406          * TODO: Indicate errata when available.
 407          */
 408         .srst_udelay    = 2,
 409         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS |
 410                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
 411         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 412                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
 413                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
 414         .sysc_fields    = &omap_hwmod_sysc_type2,
 415 };
 416
 417 static struct omap_hwmod_class omap44xx_iss_hwmod_class = {
 418         .name   = "iss",
 419         .sysc   = &omap44xx_iss_sysc,
 420 };
 421
 422 /* iss */
 423 static struct omap_hwmod_opt_clk iss_opt_clks[] = {
 424         { .role = "ctrlclk", .clk = "iss_ctrlclk" },
 425 };
 426
 427 static struct omap_hwmod omap44xx_iss_hwmod = {
 428         .name           = "iss",
 429         .class          = &omap44xx_iss_hwmod_class,
 430         .clkdm_name     = "iss_clkdm",
 431         .main_clk       = "ducati_clk_mux_ck",
 432         .prcm = {
 433                 .omap4 = {
 434                         .clkctrl_offs = OMAP4_CM_CAM_ISS_CLKCTRL_OFFSET,
 435                         .context_offs = OMAP4_RM_CAM_ISS_CONTEXT_OFFSET,
 436                         .modulemode   = MODULEMODE_SWCTRL,
 437                 },
 438         },
 439         .opt_clks       = iss_opt_clks,
 440         .opt_clks_cnt   = ARRAY_SIZE(iss_opt_clks),
 441 };
 442
 443 /*
 444  * 'iva' class
 445  * multi-standard video encoder/decoder hardware accelerator
 446  */
 447
 448 static struct omap_hwmod_class omap44xx_iva_hwmod_class = {
 449         .name   = "iva",
 450 };
 451
 452 /* iva */
 453 static struct omap_hwmod_rst_info omap44xx_iva_resets[] = {
 454         { .name = "seq0", .rst_shift = 0 },
 455         { .name = "seq1", .rst_shift = 1 },
 456         { .name = "logic", .rst_shift = 2 },
 457 };
 458
 459 static struct omap_hwmod omap44xx_iva_hwmod = {
 460         .name           = "iva",
 461         .class          = &omap44xx_iva_hwmod_class,
 462         .clkdm_name     = "ivahd_clkdm",
 463         .rst_lines      = omap44xx_iva_resets,
 464         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_iva_resets),
 465         .main_clk       = "dpll_iva_m5x2_ck",
 466         .prcm = {
 467                 .omap4 = {
 468                         .clkctrl_offs = OMAP4_CM_IVAHD_IVAHD_CLKCTRL_OFFSET,
 469                         .rstctrl_offs = OMAP4_RM_IVAHD_RSTCTRL_OFFSET,
 470                         .context_offs = OMAP4_RM_IVAHD_IVAHD_CONTEXT_OFFSET,
 471                         .modulemode   = MODULEMODE_HWCTRL,
 472                 },
 473         },
 474 };
 475
 476 /*
 477  * 'mpu' class
 478  * mpu sub-system
 479  */
 480
 481 static struct omap_hwmod_class omap44xx_mpu_hwmod_class = {
 482         .name   = "mpu",
 483 };
 484
 485 /* mpu */
 486 static struct omap_hwmod omap44xx_mpu_hwmod = {
 487         .name           = "mpu",
 488         .class          = &omap44xx_mpu_hwmod_class,
 489         .clkdm_name     = "mpuss_clkdm",
 490         .flags          = HWMOD_INIT_NO_IDLE,
 491         .main_clk       = "dpll_mpu_m2_ck",
 492         .prcm = {
 493                 .omap4 = {
 494                         .clkctrl_offs = OMAP4_CM_MPU_MPU_CLKCTRL_OFFSET,
 495                         .context_offs = OMAP4_RM_MPU_MPU_CONTEXT_OFFSET,
 496                 },
 497         },
 498 };
 499
 500 /*
 501  * 'ocmc_ram' class
 502  * top-level core on-chip ram
 503  */
 504
 505 static struct omap_hwmod_class omap44xx_ocmc_ram_hwmod_class = {
 506         .name   = "ocmc_ram",
 507 };
 508
 509 /* ocmc_ram */
 510 static struct omap_hwmod omap44xx_ocmc_ram_hwmod = {
 511         .name           = "ocmc_ram",
 512         .class          = &omap44xx_ocmc_ram_hwmod_class,
 513         .clkdm_name     = "l3_2_clkdm",
 514         .prcm = {
 515                 .omap4 = {
 516                         .clkctrl_offs = OMAP4_CM_L3_2_OCMC_RAM_CLKCTRL_OFFSET,
 517                         .context_offs = OMAP4_RM_L3_2_OCMC_RAM_CONTEXT_OFFSET,
 518                 },
 519         },
 520 };
 521
 522
 523 /*
 524  * 'prcm' class
 525  * power and reset manager (part of the prcm infrastructure) + clock manager 2
 526  * + clock manager 1 (in always on power domain) + local prm in mpu
 527  */
 528
 529 static struct omap_hwmod_class omap44xx_prcm_hwmod_class = {
 530         .name   = "prcm",
 531 };
 532
 533 /* prcm_mpu */
 534 static struct omap_hwmod omap44xx_prcm_mpu_hwmod = {
 535         .name           = "prcm_mpu",
 536         .class          = &omap44xx_prcm_hwmod_class,
 537         .clkdm_name     = "l4_wkup_clkdm",
 538         .flags          = HWMOD_NO_IDLEST,
 539         .prcm = {
 540                 .omap4 = {
 541                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 542                 },
 543         },
 544 };
 545
 546 /* cm_core_aon */
 547 static struct omap_hwmod omap44xx_cm_core_aon_hwmod = {
 548         .name           = "cm_core_aon",
 549         .class          = &omap44xx_prcm_hwmod_class,
 550         .flags          = HWMOD_NO_IDLEST,
 551         .prcm = {
 552                 .omap4 = {
 553                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 554                 },
 555         },
 556 };
 557
 558 /* cm_core */
 559 static struct omap_hwmod omap44xx_cm_core_hwmod = {
 560         .name           = "cm_core",
 561         .class          = &omap44xx_prcm_hwmod_class,
 562         .flags          = HWMOD_NO_IDLEST,
 563         .prcm = {
 564                 .omap4 = {
 565                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 566                 },
 567         },
 568 };
 569
 570 /* prm */
 571 static struct omap_hwmod_rst_info omap44xx_prm_resets[] = {
 572         { .name = "rst_global_warm_sw", .rst_shift = 0 },
 573         { .name = "rst_global_cold_sw", .rst_shift = 1 },
 574 };
 575
 576 static struct omap_hwmod omap44xx_prm_hwmod = {
 577         .name           = "prm",
 578         .class          = &omap44xx_prcm_hwmod_class,
 579         .rst_lines      = omap44xx_prm_resets,
 580         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_prm_resets),
 581 };
 582
 583 /*
 584  * 'scrm' class
 585  * system clock and reset manager
 586  */
 587
 588 static struct omap_hwmod_class omap44xx_scrm_hwmod_class = {
 589         .name   = "scrm",
 590 };
 591
 592 /* scrm */
 593 static struct omap_hwmod omap44xx_scrm_hwmod = {
 594         .name           = "scrm",
 595         .class          = &omap44xx_scrm_hwmod_class,
 596         .clkdm_name     = "l4_wkup_clkdm",
 597         .prcm = {
 598                 .omap4 = {
 599                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 600                 },
 601         },
 602 };
 603
 604 /*
 605  * 'sl2if' class
 606  * shared level 2 memory interface
 607  */
 608
 609 static struct omap_hwmod_class omap44xx_sl2if_hwmod_class = {
 610         .name   = "sl2if",
 611 };
 612
 613 /* sl2if */
 614 static struct omap_hwmod omap44xx_sl2if_hwmod = {
 615         .name           = "sl2if",
 616         .class          = &omap44xx_sl2if_hwmod_class,
 617         .clkdm_name     = "ivahd_clkdm",
 618         .prcm = {
 619                 .omap4 = {
 620                         .clkctrl_offs = OMAP4_CM_IVAHD_SL2_CLKCTRL_OFFSET,
 621                         .context_offs = OMAP4_RM_IVAHD_SL2_CONTEXT_OFFSET,
 622                         .modulemode   = MODULEMODE_HWCTRL,
 623                 },
 624         },
 625 };
 626
 627 /*
 628  * interfaces
 629  */
 630
 631 /* l3_main_1 -> dmm */
 632 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__dmm = {
 633         .master         = &omap44xx_l3_main_1_hwmod,
 634         .slave          = &omap44xx_dmm_hwmod,
 635         .clk            = "l3_div_ck",
 636         .user           = OCP_USER_SDMA,
 637 };
 638
 639 /* mpu -> dmm */
 640 static struct omap_hwmod_ocp_if omap44xx_mpu__dmm = {
 641         .master         = &omap44xx_mpu_hwmod,
 642         .slave          = &omap44xx_dmm_hwmod,
 643         .clk            = "l3_div_ck",
 644         .user           = OCP_USER_MPU,
 645 };
 646
 647 /* iva -> l3_instr */
 648 static struct omap_hwmod_ocp_if omap44xx_iva__l3_instr = {
 649         .master         = &omap44xx_iva_hwmod,
 650         .slave          = &omap44xx_l3_instr_hwmod,
 651         .clk            = "l3_div_ck",
 652         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 653 };
 654
 655 /* l3_main_3 -> l3_instr */
 656 static struct omap_hwmod_ocp_if omap44xx_l3_main_3__l3_instr = {
 657         .master         = &omap44xx_l3_main_3_hwmod,
 658         .slave          = &omap44xx_l3_instr_hwmod,
 659         .clk            = "l3_div_ck",
 660         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 661 };
 662
 663 /* ocp_wp_noc -> l3_instr */
 664 static struct omap_hwmod_ocp_if omap44xx_ocp_wp_noc__l3_instr = {
 665         .master         = &omap44xx_ocp_wp_noc_hwmod,
 666         .slave          = &omap44xx_l3_instr_hwmod,
 667         .clk            = "l3_div_ck",
 668         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 669 };
 670
 671 /* l3_main_2 -> l3_main_1 */
 672 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_1 = {
 673         .master         = &omap44xx_l3_main_2_hwmod,
 674         .slave          = &omap44xx_l3_main_1_hwmod,
 675         .clk            = "l3_div_ck",
 676         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 677 };
 678
 679 /* l4_cfg -> l3_main_1 */
 680 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_1 = {
 681         .master         = &omap44xx_l4_cfg_hwmod,
 682         .slave          = &omap44xx_l3_main_1_hwmod,
 683         .clk            = "l4_div_ck",
 684         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 685 };
 686
 687 /* mpu -> l3_main_1 */
 688 static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = {
 689         .master         = &omap44xx_mpu_hwmod,
 690         .slave          = &omap44xx_l3_main_1_hwmod,
 691         .clk            = "l3_div_ck",
 692         .user           = OCP_USER_MPU,
 693 };
 694
 695 /* debugss -> l3_main_2 */
 696 static struct omap_hwmod_ocp_if omap44xx_debugss__l3_main_2 = {
 697         .master         = &omap44xx_debugss_hwmod,
 698         .slave          = &omap44xx_l3_main_2_hwmod,
 699         .clk            = "dbgclk_mux_ck",
 700         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 701 };
 702
 703 /* iss -> l3_main_2 */
 704 static struct omap_hwmod_ocp_if omap44xx_iss__l3_main_2 = {
 705         .master         = &omap44xx_iss_hwmod,
 706         .slave          = &omap44xx_l3_main_2_hwmod,
 707         .clk            = "l3_div_ck",
 708         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 709 };
 710
 711 /* iva -> l3_main_2 */
 712 static struct omap_hwmod_ocp_if omap44xx_iva__l3_main_2 = {
 713         .master         = &omap44xx_iva_hwmod,
 714         .slave          = &omap44xx_l3_main_2_hwmod,
 715         .clk            = "l3_div_ck",
 716         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 717 };
 718
 719 /* l3_main_1 -> l3_main_2 */
 720 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2 = {
 721         .master         = &omap44xx_l3_main_1_hwmod,
 722         .slave          = &omap44xx_l3_main_2_hwmod,
 723         .clk            = "l3_div_ck",
 724         .user           = OCP_USER_MPU,
 725 };
 726
 727 /* l4_cfg -> l3_main_2 */
 728 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_2 = {
 729         .master         = &omap44xx_l4_cfg_hwmod,
 730         .slave          = &omap44xx_l3_main_2_hwmod,
 731         .clk            = "l4_div_ck",
 732         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 733 };
 734
 735 /* l3_main_1 -> l3_main_3 */
 736 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_3 = {
 737         .master         = &omap44xx_l3_main_1_hwmod,
 738         .slave          = &omap44xx_l3_main_3_hwmod,
 739         .clk            = "l3_div_ck",
 740         .user           = OCP_USER_MPU,
 741 };
 742
 743 /* l3_main_2 -> l3_main_3 */
 744 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_3 = {
 745         .master         = &omap44xx_l3_main_2_hwmod,
 746         .slave          = &omap44xx_l3_main_3_hwmod,
 747         .clk            = "l3_div_ck",
 748         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 749 };
 750
 751 /* l4_cfg -> l3_main_3 */
 752 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_3 = {
 753         .master         = &omap44xx_l4_cfg_hwmod,
 754         .slave          = &omap44xx_l3_main_3_hwmod,
 755         .clk            = "l4_div_ck",
 756         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 757 };
 758
 759 /* l3_main_1 -> l4_cfg */
 760 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_cfg = {
 761         .master         = &omap44xx_l3_main_1_hwmod,
 762         .slave          = &omap44xx_l4_cfg_hwmod,
 763         .clk            = "l3_div_ck",
 764         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 765 };
 766
 767 /* l3_main_2 -> l4_per */
 768 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l4_per = {
 769         .master         = &omap44xx_l3_main_2_hwmod,
 770         .slave          = &omap44xx_l4_per_hwmod,
 771         .clk            = "l3_div_ck",
 772         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 773 };
 774
 775 /* l4_cfg -> l4_wkup */
 776 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l4_wkup = {
 777         .master         = &omap44xx_l4_cfg_hwmod,
 778         .slave          = &omap44xx_l4_wkup_hwmod,
 779         .clk            = "l4_div_ck",
 780         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 781 };
 782
 783 /* mpu -> mpu_private */
 784 static struct omap_hwmod_ocp_if omap44xx_mpu__mpu_private = {
 785         .master         = &omap44xx_mpu_hwmod,
 786         .slave          = &omap44xx_mpu_private_hwmod,
 787         .clk            = "l3_div_ck",
 788         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 789 };
 790
 791 /* l4_cfg -> ocp_wp_noc */
 792 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp_wp_noc = {
 793         .master         = &omap44xx_l4_cfg_hwmod,
 794         .slave          = &omap44xx_ocp_wp_noc_hwmod,
 795         .clk            = "l4_div_ck",
 796         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 797 };
 798
 799 /* l4_cfg -> ctrl_module_core */
 800 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ctrl_module_core = {
 801         .master         = &omap44xx_l4_cfg_hwmod,
 802         .slave          = &omap44xx_ctrl_module_core_hwmod,
 803         .clk            = "l4_div_ck",
 804         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 805 };
 806
 807 /* l4_cfg -> ctrl_module_pad_core */
 808 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ctrl_module_pad_core = {
 809         .master         = &omap44xx_l4_cfg_hwmod,
 810         .slave          = &omap44xx_ctrl_module_pad_core_hwmod,
 811         .clk            = "l4_div_ck",
 812         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 813 };
 814
 815 /* l4_wkup -> ctrl_module_wkup */
 816 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__ctrl_module_wkup = {
 817         .master         = &omap44xx_l4_wkup_hwmod,
 818         .slave          = &omap44xx_ctrl_module_wkup_hwmod,
 819         .clk            = "l4_wkup_clk_mux_ck",
 820         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 821 };
 822
 823 /* l4_wkup -> ctrl_module_pad_wkup */
 824 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__ctrl_module_pad_wkup = {
 825         .master         = &omap44xx_l4_wkup_hwmod,
 826         .slave          = &omap44xx_ctrl_module_pad_wkup_hwmod,
 827         .clk            = "l4_wkup_clk_mux_ck",
 828         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 829 };
 830
 831 /* l3_instr -> debugss */
 832 static struct omap_hwmod_ocp_if omap44xx_l3_instr__debugss = {
 833         .master         = &omap44xx_l3_instr_hwmod,
 834         .slave          = &omap44xx_debugss_hwmod,
 835         .clk            = "l3_div_ck",
 836         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 837 };
 838
 839 /* l3_main_2 -> gpmc */
 840 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__gpmc = {
 841         .master         = &omap44xx_l3_main_2_hwmod,
 842         .slave          = &omap44xx_gpmc_hwmod,
 843         .clk            = "l3_div_ck",
 844         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 845 };
 846
 847 /* l3_main_2 -> iss */
 848 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iss = {
 849         .master         = &omap44xx_l3_main_2_hwmod,
 850         .slave          = &omap44xx_iss_hwmod,
 851         .clk            = "l3_div_ck",
 852         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 853 };
 854
 855 /* iva -> sl2if */
 856 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_iva__sl2if = {
 857         .master         = &omap44xx_iva_hwmod,
 858         .slave          = &omap44xx_sl2if_hwmod,
 859         .clk            = "dpll_iva_m5x2_ck",
 860         .user           = OCP_USER_IVA,
 861 };
 862
 863 /* l3_main_2 -> iva */
 864 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iva = {
 865         .master         = &omap44xx_l3_main_2_hwmod,
 866         .slave          = &omap44xx_iva_hwmod,
 867         .clk            = "l3_div_ck",
 868         .user           = OCP_USER_MPU,
 869 };
 870
 871 /* l3_main_2 -> ocmc_ram */
 872 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ocmc_ram = {
 873         .master         = &omap44xx_l3_main_2_hwmod,
 874         .slave          = &omap44xx_ocmc_ram_hwmod,
 875         .clk            = "l3_div_ck",
 876         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 877 };
 878
 879 /* mpu_private -> prcm_mpu */
 880 static struct omap_hwmod_ocp_if omap44xx_mpu_private__prcm_mpu = {
 881         .master         = &omap44xx_mpu_private_hwmod,
 882         .slave          = &omap44xx_prcm_mpu_hwmod,
 883         .clk            = "l3_div_ck",
 884         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 885 };
 886
 887 /* l4_wkup -> cm_core_aon */
 888 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__cm_core_aon = {
 889         .master         = &omap44xx_l4_wkup_hwmod,
 890         .slave          = &omap44xx_cm_core_aon_hwmod,
 891         .clk            = "l4_wkup_clk_mux_ck",
 892         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 893 };
 894
 895 /* l4_cfg -> cm_core */
 896 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__cm_core = {
 897         .master         = &omap44xx_l4_cfg_hwmod,
 898         .slave          = &omap44xx_cm_core_hwmod,
 899         .clk            = "l4_div_ck",
 900         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 901 };
 902
 903 /* l4_wkup -> prm */
 904 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__prm = {
 905         .master         = &omap44xx_l4_wkup_hwmod,
 906         .slave          = &omap44xx_prm_hwmod,
 907         .clk            = "l4_wkup_clk_mux_ck",
 908         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 909 };
 910
 911 /* l4_wkup -> scrm */
 912 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__scrm = {
 913         .master         = &omap44xx_l4_wkup_hwmod,
 914         .slave          = &omap44xx_scrm_hwmod,
 915         .clk            = "l4_wkup_clk_mux_ck",
 916         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 917 };
 918
 919 /* l3_main_2 -> sl2if */
 920 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l3_main_2__sl2if = {
 921         .master         = &omap44xx_l3_main_2_hwmod,
 922         .slave          = &omap44xx_sl2if_hwmod,
 923         .clk            = "l3_div_ck",
 924         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 925 };
 926
 927 /* mpu -> emif1 */
 928 static struct omap_hwmod_ocp_if omap44xx_mpu__emif1 = {
 929         .master         = &omap44xx_mpu_hwmod,
 930         .slave          = &omap44xx_emif1_hwmod,
 931         .clk            = "l3_div_ck",
 932         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 933 };
 934
 935 /* mpu -> emif2 */
 936 static struct omap_hwmod_ocp_if omap44xx_mpu__emif2 = {
 937         .master         = &omap44xx_mpu_hwmod,
 938         .slave          = &omap44xx_emif2_hwmod,
 939         .clk            = "l3_div_ck",
 940         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 941 };
 942
 943 static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = {
 944         &omap44xx_l3_main_1__dmm,
 945         &omap44xx_mpu__dmm,
 946         &omap44xx_iva__l3_instr,
 947         &omap44xx_l3_main_3__l3_instr,
 948         &omap44xx_ocp_wp_noc__l3_instr,
 949         &omap44xx_l3_main_2__l3_main_1,
 950         &omap44xx_l4_cfg__l3_main_1,
 951         &omap44xx_mpu__l3_main_1,
 952         &omap44xx_debugss__l3_main_2,
 953         &omap44xx_iss__l3_main_2,
 954         &omap44xx_iva__l3_main_2,
 955         &omap44xx_l3_main_1__l3_main_2,
 956         &omap44xx_l4_cfg__l3_main_2,
 957         &omap44xx_l3_main_1__l3_main_3,
 958         &omap44xx_l3_main_2__l3_main_3,
 959         &omap44xx_l4_cfg__l3_main_3,
 960         &omap44xx_l3_main_1__l4_cfg,
 961         &omap44xx_l3_main_2__l4_per,
 962         &omap44xx_l4_cfg__l4_wkup,
 963         &omap44xx_mpu__mpu_private,
 964         &omap44xx_l4_cfg__ocp_wp_noc,
 965         &omap44xx_l4_cfg__ctrl_module_core,
 966         &omap44xx_l4_cfg__ctrl_module_pad_core,
 967         &omap44xx_l4_wkup__ctrl_module_wkup,
 968         &omap44xx_l4_wkup__ctrl_module_pad_wkup,
 969         &omap44xx_l3_instr__debugss,
 970         &omap44xx_l3_main_2__gpmc,
 971         &omap44xx_l3_main_2__iss,
 972         /* &omap44xx_iva__sl2if, */
 973         &omap44xx_l3_main_2__iva,
 974         &omap44xx_l3_main_2__ocmc_ram,
 975         &omap44xx_mpu_private__prcm_mpu,
 976         &omap44xx_l4_wkup__cm_core_aon,
 977         &omap44xx_l4_cfg__cm_core,
 978         &omap44xx_l4_wkup__prm,
 979         &omap44xx_l4_wkup__scrm,
 980         /* &omap44xx_l3_main_2__sl2if, */
 981         &omap44xx_mpu__emif1,
 982         &omap44xx_mpu__emif2,
 983         NULL,
 984 };
 985
 986 int __init omap44xx_hwmod_init(void)
 987 {
 988         omap_hwmod_init();
 989         return omap_hwmod_register_links(omap44xx_hwmod_ocp_ifs);
 990 }
 991