arch/arm/mach-omap2/clockdomains54xx_data.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * OMAP54XX Clock domains framework
   4  *
   5  * Copyright (C) 2013 Texas Instruments, Inc.
   6  *
   7  * Abhijit Pagare (abhijitpagare@ti.com)
   8  * Benoit Cousson (b-cousson@ti.com)
   9  * Paul Walmsley (paul@pwsan.com)
  10  *
  11  * This file is automatically generated from the OMAP hardware databases.
  12  * We respectfully ask that any modifications to this file be coordinated
  13  * with the public linux-omap@vger.kernel.org mailing list and the
  14  * authors above to ensure that the autogeneration scripts are kept
  15  * up-to-date with the file contents.
  16  */
  17
  18 #include <linux/kernel.h>
  19 #include <linux/io.h>
  20
  21 #include "clockdomain.h"
  22 #include "cm1_54xx.h"
  23 #include "cm2_54xx.h"
  24
  25 #include "cm-regbits-54xx.h"
  26 #include "prm54xx.h"
  27 #include "prcm44xx.h"
  28 #include "prcm_mpu54xx.h"
  29
  30 /* Static Dependencies for OMAP4 Clock Domains */
  31
  32 static struct clkdm_dep c2c_wkup_sleep_deps[] = {
  33         { .clkdm_name = "abe_clkdm" },
  34         { .clkdm_name = "emif_clkdm" },
  35         { .clkdm_name = "iva_clkdm" },
  36         { .clkdm_name = "l3init_clkdm" },
  37         { .clkdm_name = "l3main1_clkdm" },
  38         { .clkdm_name = "l3main2_clkdm" },
  39         { .clkdm_name = "l4cfg_clkdm" },
  40         { .clkdm_name = "l4per_clkdm" },
  41         { NULL },
  42 };
  43
  44 static struct clkdm_dep cam_wkup_sleep_deps[] = {
  45         { .clkdm_name = "emif_clkdm" },
  46         { .clkdm_name = "iva_clkdm" },
  47         { .clkdm_name = "l3main1_clkdm" },
  48         { NULL },
  49 };
  50
  51 static struct clkdm_dep dma_wkup_sleep_deps[] = {
  52         { .clkdm_name = "abe_clkdm" },
  53         { .clkdm_name = "dss_clkdm" },
  54         { .clkdm_name = "emif_clkdm" },
  55         { .clkdm_name = "ipu_clkdm" },
  56         { .clkdm_name = "iva_clkdm" },
  57         { .clkdm_name = "l3init_clkdm" },
  58         { .clkdm_name = "l3main1_clkdm" },
  59         { .clkdm_name = "l4cfg_clkdm" },
  60         { .clkdm_name = "l4per_clkdm" },
  61         { .clkdm_name = "l4sec_clkdm" },
  62         { .clkdm_name = "wkupaon_clkdm" },
  63         { NULL },
  64 };
  65
  66 static struct clkdm_dep dsp_wkup_sleep_deps[] = {
  67         { .clkdm_name = "abe_clkdm" },
  68         { .clkdm_name = "emif_clkdm" },
  69         { .clkdm_name = "iva_clkdm" },
  70         { .clkdm_name = "l3init_clkdm" },
  71         { .clkdm_name = "l3main1_clkdm" },
  72         { .clkdm_name = "l3main2_clkdm" },
  73         { .clkdm_name = "l4cfg_clkdm" },
  74         { .clkdm_name = "l4per_clkdm" },
  75         { .clkdm_name = "wkupaon_clkdm" },
  76         { NULL },
  77 };
  78
  79 static struct clkdm_dep dss_wkup_sleep_deps[] = {
  80         { .clkdm_name = "emif_clkdm" },
  81         { .clkdm_name = "iva_clkdm" },
  82         { .clkdm_name = "l3main2_clkdm" },
  83         { NULL },
  84 };
  85
  86 static struct clkdm_dep gpu_wkup_sleep_deps[] = {
  87         { .clkdm_name = "emif_clkdm" },
  88         { .clkdm_name = "iva_clkdm" },
  89         { .clkdm_name = "l3main1_clkdm" },
  90         { NULL },
  91 };
  92
  93 static struct clkdm_dep ipu_wkup_sleep_deps[] = {
  94         { .clkdm_name = "abe_clkdm" },
  95         { .clkdm_name = "dsp_clkdm" },
  96         { .clkdm_name = "dss_clkdm" },
  97         { .clkdm_name = "emif_clkdm" },
  98         { .clkdm_name = "gpu_clkdm" },
  99         { .clkdm_name = "iva_clkdm" },
 100         { .clkdm_name = "l3init_clkdm" },
 101         { .clkdm_name = "l3main1_clkdm" },
 102         { .clkdm_name = "l3main2_clkdm" },
 103         { .clkdm_name = "l4cfg_clkdm" },
 104         { .clkdm_name = "l4per_clkdm" },
 105         { .clkdm_name = "l4sec_clkdm" },
 106         { .clkdm_name = "wkupaon_clkdm" },
 107         { NULL },
 108 };
 109
 110 static struct clkdm_dep iva_wkup_sleep_deps[] = {
 111         { .clkdm_name = "emif_clkdm" },
 112         { .clkdm_name = "l3main1_clkdm" },
 113         { NULL },
 114 };
 115
 116 static struct clkdm_dep l3init_wkup_sleep_deps[] = {
 117         { .clkdm_name = "abe_clkdm" },
 118         { .clkdm_name = "emif_clkdm" },
 119         { .clkdm_name = "iva_clkdm" },
 120         { .clkdm_name = "l4cfg_clkdm" },
 121         { .clkdm_name = "l4per_clkdm" },
 122         { .clkdm_name = "l4sec_clkdm" },
 123         { .clkdm_name = "wkupaon_clkdm" },
 124         { NULL },
 125 };
 126
 127 static struct clkdm_dep l4sec_wkup_sleep_deps[] = {
 128         { .clkdm_name = "emif_clkdm" },
 129         { .clkdm_name = "l3main1_clkdm" },
 130         { .clkdm_name = "l4per_clkdm" },
 131         { NULL },
 132 };
 133
 134 static struct clkdm_dep mipiext_wkup_sleep_deps[] = {
 135         { .clkdm_name = "abe_clkdm" },
 136         { .clkdm_name = "emif_clkdm" },
 137         { .clkdm_name = "iva_clkdm" },
 138         { .clkdm_name = "l3init_clkdm" },
 139         { .clkdm_name = "l3main1_clkdm" },
 140         { .clkdm_name = "l3main2_clkdm" },
 141         { .clkdm_name = "l4cfg_clkdm" },
 142         { .clkdm_name = "l4per_clkdm" },
 143         { NULL },
 144 };
 145
 146 static struct clkdm_dep mpu_wkup_sleep_deps[] = {
 147         { .clkdm_name = "abe_clkdm" },
 148         { .clkdm_name = "dsp_clkdm" },
 149         { .clkdm_name = "dss_clkdm" },
 150         { .clkdm_name = "emif_clkdm" },
 151         { .clkdm_name = "gpu_clkdm" },
 152         { .clkdm_name = "ipu_clkdm" },
 153         { .clkdm_name = "iva_clkdm" },
 154         { .clkdm_name = "l3init_clkdm" },
 155         { .clkdm_name = "l3main1_clkdm" },
 156         { .clkdm_name = "l3main2_clkdm" },
 157         { .clkdm_name = "l4cfg_clkdm" },
 158         { .clkdm_name = "l4per_clkdm" },
 159         { .clkdm_name = "l4sec_clkdm" },
 160         { .clkdm_name = "wkupaon_clkdm" },
 161         { NULL },
 162 };
 163
 164 static struct clockdomain l4sec_54xx_clkdm = {
 165         .name             = "l4sec_clkdm",
 166         .pwrdm            = { .name = "core_pwrdm" },
 167         .prcm_partition   = OMAP54XX_CM_CORE_PARTITION,
 168         .cm_inst          = OMAP54XX_CM_CORE_CORE_INST,
 169         .clkdm_offs       = OMAP54XX_CM_CORE_CORE_L4SEC_CDOFFS,
 170         .dep_bit          = OMAP54XX_L4SEC_STATDEP_SHIFT,
 171         .wkdep_srcs       = l4sec_wkup_sleep_deps,
 172         .sleepdep_srcs    = l4sec_wkup_sleep_deps,
 173         .flags            = CLKDM_CAN_SWSUP,
 174 };
 175
 176 static struct clockdomain iva_54xx_clkdm = {
 177         .name             = "iva_clkdm",
 178         .pwrdm            = { .name = "iva_pwrdm" },
 179         .prcm_partition   = OMAP54XX_CM_CORE_PARTITION,
 180         .cm_inst          = OMAP54XX_CM_CORE_IVA_INST,
 181         .clkdm_offs       = OMAP54XX_CM_CORE_IVA_IVA_CDOFFS,
 182         .dep_bit          = OMAP54XX_IVA_STATDEP_SHIFT,
 183         .wkdep_srcs       = iva_wkup_sleep_deps,
 184         .sleepdep_srcs    = iva_wkup_sleep_deps,
 185         .flags            = CLKDM_CAN_HWSUP_SWSUP,
 186 };
 187
 188 static struct clockdomain mipiext_54xx_clkdm = {
 189         .name             = "mipiext_clkdm",
 190         .pwrdm            = { .name = "core_pwrdm" },
 191         .prcm_partition   = OMAP54XX_CM_CORE_PARTITION,
 192         .cm_inst          = OMAP54XX_CM_CORE_CORE_INST,
 193         .clkdm_offs       = OMAP54XX_CM_CORE_CORE_MIPIEXT_CDOFFS,
 194         .wkdep_srcs       = mipiext_wkup_sleep_deps,
 195         .sleepdep_srcs    = mipiext_wkup_sleep_deps,
 196         .flags            = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
 197 };
 198
 199 static struct clockdomain l3main2_54xx_clkdm = {
 200         .name             = "l3main2_clkdm",
 201         .pwrdm            = { .name = "core_pwrdm" },
 202         .prcm_partition   = OMAP54XX_CM_CORE_PARTITION,
 203         .cm_inst          = OMAP54XX_CM_CORE_CORE_INST,
 204         .clkdm_offs       = OMAP54XX_CM_CORE_CORE_L3MAIN2_CDOFFS,
 205         .dep_bit          = OMAP54XX_L3MAIN2_STATDEP_SHIFT,
 206         .flags            = CLKDM_CAN_HWSUP,
 207 };
 208
 209 static struct clockdomain l3main1_54xx_clkdm = {
 210         .name             = "l3main1_clkdm",
 211         .pwrdm            = { .name = "core_pwrdm" },
 212         .prcm_partition   = OMAP54XX_CM_CORE_PARTITION,
 213         .cm_inst          = OMAP54XX_CM_CORE_CORE_INST,
 214         .clkdm_offs       = OMAP54XX_CM_CORE_CORE_L3MAIN1_CDOFFS,
 215         .dep_bit          = OMAP54XX_L3MAIN1_STATDEP_SHIFT,
 216         .flags            = CLKDM_CAN_HWSUP,
 217 };
 218
 219 static struct clockdomain custefuse_54xx_clkdm = {
 220         .name             = "custefuse_clkdm",
 221         .pwrdm            = { .name = "custefuse_pwrdm" },
 222         .prcm_partition   = OMAP54XX_CM_CORE_PARTITION,
 223         .cm_inst          = OMAP54XX_CM_CORE_CUSTEFUSE_INST,
 224         .clkdm_offs       = OMAP54XX_CM_CORE_CUSTEFUSE_CUSTEFUSE_CDOFFS,
 225         .flags            = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
 226 };
 227
 228 static struct clockdomain ipu_54xx_clkdm = {
 229         .name             = "ipu_clkdm",
 230         .pwrdm            = { .name = "core_pwrdm" },
 231         .prcm_partition   = OMAP54XX_CM_CORE_PARTITION,
 232         .cm_inst          = OMAP54XX_CM_CORE_CORE_INST,
 233         .clkdm_offs       = OMAP54XX_CM_CORE_CORE_IPU_CDOFFS,
 234         .dep_bit          = OMAP54XX_IPU_STATDEP_SHIFT,
 235         .wkdep_srcs       = ipu_wkup_sleep_deps,
 236         .sleepdep_srcs    = ipu_wkup_sleep_deps,
 237         .flags            = CLKDM_CAN_HWSUP_SWSUP,
 238 };
 239
 240 static struct clockdomain l4cfg_54xx_clkdm = {
 241         .name             = "l4cfg_clkdm",
 242         .pwrdm            = { .name = "core_pwrdm" },
 243         .prcm_partition   = OMAP54XX_CM_CORE_PARTITION,
 244         .cm_inst          = OMAP54XX_CM_CORE_CORE_INST,
 245         .clkdm_offs       = OMAP54XX_CM_CORE_CORE_L4CFG_CDOFFS,
 246         .dep_bit          = OMAP54XX_L4CFG_STATDEP_SHIFT,
 247         .flags            = CLKDM_CAN_HWSUP,
 248 };
 249
 250 static struct clockdomain abe_54xx_clkdm = {
 251         .name             = "abe_clkdm",
 252         .pwrdm            = { .name = "abe_pwrdm" },
 253         .prcm_partition   = OMAP54XX_CM_CORE_AON_PARTITION,
 254         .cm_inst          = OMAP54XX_CM_CORE_AON_ABE_INST,
 255         .clkdm_offs       = OMAP54XX_CM_CORE_AON_ABE_ABE_CDOFFS,
 256         .dep_bit          = OMAP54XX_ABE_STATDEP_SHIFT,
 257         .flags            = CLKDM_CAN_HWSUP_SWSUP,
 258 };
 259
 260 static struct clockdomain dss_54xx_clkdm = {
 261         .name             = "dss_clkdm",
 262         .pwrdm            = { .name = "dss_pwrdm" },
 263         .prcm_partition   = OMAP54XX_CM_CORE_PARTITION,
 264         .cm_inst          = OMAP54XX_CM_CORE_DSS_INST,
 265         .clkdm_offs       = OMAP54XX_CM_CORE_DSS_DSS_CDOFFS,
 266         .dep_bit          = OMAP54XX_DSS_STATDEP_SHIFT,
 267         .wkdep_srcs       = dss_wkup_sleep_deps,
 268         .sleepdep_srcs    = dss_wkup_sleep_deps,
 269         .flags            = CLKDM_CAN_HWSUP_SWSUP,
 270 };
 271
 272 static struct clockdomain dsp_54xx_clkdm = {
 273         .name             = "dsp_clkdm",
 274         .pwrdm            = { .name = "dsp_pwrdm" },
 275         .prcm_partition   = OMAP54XX_CM_CORE_AON_PARTITION,
 276         .cm_inst          = OMAP54XX_CM_CORE_AON_DSP_INST,
 277         .clkdm_offs       = OMAP54XX_CM_CORE_AON_DSP_DSP_CDOFFS,
 278         .dep_bit          = OMAP54XX_DSP_STATDEP_SHIFT,
 279         .wkdep_srcs       = dsp_wkup_sleep_deps,
 280         .sleepdep_srcs    = dsp_wkup_sleep_deps,
 281         .flags            = CLKDM_CAN_HWSUP_SWSUP,
 282 };
 283
 284 static struct clockdomain c2c_54xx_clkdm = {
 285         .name             = "c2c_clkdm",
 286         .pwrdm            = { .name = "core_pwrdm" },
 287         .prcm_partition   = OMAP54XX_CM_CORE_PARTITION,
 288         .cm_inst          = OMAP54XX_CM_CORE_CORE_INST,
 289         .clkdm_offs       = OMAP54XX_CM_CORE_CORE_C2C_CDOFFS,
 290         .wkdep_srcs       = c2c_wkup_sleep_deps,
 291         .sleepdep_srcs    = c2c_wkup_sleep_deps,
 292         .flags            = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
 293 };
 294
 295 static struct clockdomain l4per_54xx_clkdm = {
 296         .name             = "l4per_clkdm",
 297         .pwrdm            = { .name = "core_pwrdm" },
 298         .prcm_partition   = OMAP54XX_CM_CORE_PARTITION,
 299         .cm_inst          = OMAP54XX_CM_CORE_CORE_INST,
 300         .clkdm_offs       = OMAP54XX_CM_CORE_CORE_L4PER_CDOFFS,
 301         .dep_bit          = OMAP54XX_L4PER_STATDEP_SHIFT,
 302         .flags            = CLKDM_CAN_HWSUP_SWSUP,
 303 };
 304
 305 static struct clockdomain gpu_54xx_clkdm = {
 306         .name             = "gpu_clkdm",
 307         .pwrdm            = { .name = "gpu_pwrdm" },
 308         .prcm_partition   = OMAP54XX_CM_CORE_PARTITION,
 309         .cm_inst          = OMAP54XX_CM_CORE_GPU_INST,
 310         .clkdm_offs       = OMAP54XX_CM_CORE_GPU_GPU_CDOFFS,
 311         .dep_bit          = OMAP54XX_GPU_STATDEP_SHIFT,
 312         .wkdep_srcs       = gpu_wkup_sleep_deps,
 313         .sleepdep_srcs    = gpu_wkup_sleep_deps,
 314         .flags            = CLKDM_CAN_HWSUP_SWSUP,
 315 };
 316
 317 static struct clockdomain wkupaon_54xx_clkdm = {
 318         .name             = "wkupaon_clkdm",
 319         .pwrdm            = { .name = "wkupaon_pwrdm" },
 320         .prcm_partition   = OMAP54XX_PRM_PARTITION,
 321         .cm_inst          = OMAP54XX_PRM_WKUPAON_CM_INST,
 322         .clkdm_offs       = OMAP54XX_PRM_WKUPAON_CM_WKUPAON_CDOFFS,
 323         .dep_bit          = OMAP54XX_WKUPAON_STATDEP_SHIFT,
 324         .flags            = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
 325 };
 326
 327 static struct clockdomain mpu0_54xx_clkdm = {
 328         .name             = "mpu0_clkdm",
 329         .pwrdm            = { .name = "cpu0_pwrdm" },
 330         .prcm_partition   = OMAP54XX_PRCM_MPU_PARTITION,
 331         .cm_inst          = OMAP54XX_PRCM_MPU_CM_C0_INST,
 332         .clkdm_offs       = OMAP54XX_PRCM_MPU_CM_C0_CPU0_CDOFFS,
 333         .flags            = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
 334 };
 335
 336 static struct clockdomain mpu1_54xx_clkdm = {
 337         .name             = "mpu1_clkdm",
 338         .pwrdm            = { .name = "cpu1_pwrdm" },
 339         .prcm_partition   = OMAP54XX_PRCM_MPU_PARTITION,
 340         .cm_inst          = OMAP54XX_PRCM_MPU_CM_C1_INST,
 341         .clkdm_offs       = OMAP54XX_PRCM_MPU_CM_C1_CPU1_CDOFFS,
 342         .flags            = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
 343 };
 344
 345 static struct clockdomain coreaon_54xx_clkdm = {
 346         .name             = "coreaon_clkdm",
 347         .pwrdm            = { .name = "coreaon_pwrdm" },
 348         .prcm_partition   = OMAP54XX_CM_CORE_PARTITION,
 349         .cm_inst          = OMAP54XX_CM_CORE_COREAON_INST,
 350         .clkdm_offs       = OMAP54XX_CM_CORE_COREAON_COREAON_CDOFFS,
 351         .flags            = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
 352 };
 353
 354 static struct clockdomain mpu_54xx_clkdm = {
 355         .name             = "mpu_clkdm",
 356         .pwrdm            = { .name = "mpu_pwrdm" },
 357         .prcm_partition   = OMAP54XX_CM_CORE_AON_PARTITION,
 358         .cm_inst          = OMAP54XX_CM_CORE_AON_MPU_INST,
 359         .clkdm_offs       = OMAP54XX_CM_CORE_AON_MPU_MPU_CDOFFS,
 360         .wkdep_srcs       = mpu_wkup_sleep_deps,
 361         .sleepdep_srcs    = mpu_wkup_sleep_deps,
 362         .flags            = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
 363 };
 364
 365 static struct clockdomain l3init_54xx_clkdm = {
 366         .name             = "l3init_clkdm",
 367         .pwrdm            = { .name = "l3init_pwrdm" },
 368         .prcm_partition   = OMAP54XX_CM_CORE_PARTITION,
 369         .cm_inst          = OMAP54XX_CM_CORE_L3INIT_INST,
 370         .clkdm_offs       = OMAP54XX_CM_CORE_L3INIT_L3INIT_CDOFFS,
 371         .dep_bit          = OMAP54XX_L3INIT_STATDEP_SHIFT,
 372         .wkdep_srcs       = l3init_wkup_sleep_deps,
 373         .sleepdep_srcs    = l3init_wkup_sleep_deps,
 374         .flags            = CLKDM_CAN_HWSUP_SWSUP,
 375 };
 376
 377 static struct clockdomain dma_54xx_clkdm = {
 378         .name             = "dma_clkdm",
 379         .pwrdm            = { .name = "core_pwrdm" },
 380         .prcm_partition   = OMAP54XX_CM_CORE_PARTITION,
 381         .cm_inst          = OMAP54XX_CM_CORE_CORE_INST,
 382         .clkdm_offs       = OMAP54XX_CM_CORE_CORE_DMA_CDOFFS,
 383         .wkdep_srcs       = dma_wkup_sleep_deps,
 384         .sleepdep_srcs    = dma_wkup_sleep_deps,
 385         .flags            = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
 386 };
 387
 388 static struct clockdomain l3instr_54xx_clkdm = {
 389         .name             = "l3instr_clkdm",
 390         .pwrdm            = { .name = "core_pwrdm" },
 391         .prcm_partition   = OMAP54XX_CM_CORE_PARTITION,
 392         .cm_inst          = OMAP54XX_CM_CORE_CORE_INST,
 393         .clkdm_offs       = OMAP54XX_CM_CORE_CORE_L3INSTR_CDOFFS,
 394 };
 395
 396 static struct clockdomain emif_54xx_clkdm = {
 397         .name             = "emif_clkdm",
 398         .pwrdm            = { .name = "core_pwrdm" },
 399         .prcm_partition   = OMAP54XX_CM_CORE_PARTITION,
 400         .cm_inst          = OMAP54XX_CM_CORE_CORE_INST,
 401         .clkdm_offs       = OMAP54XX_CM_CORE_CORE_EMIF_CDOFFS,
 402         .dep_bit          = OMAP54XX_EMIF_STATDEP_SHIFT,
 403         .flags            = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
 404 };
 405
 406 static struct clockdomain emu_54xx_clkdm = {
 407         .name             = "emu_clkdm",
 408         .pwrdm            = { .name = "emu_pwrdm" },
 409         .prcm_partition   = OMAP54XX_PRM_PARTITION,
 410         .cm_inst          = OMAP54XX_PRM_EMU_CM_INST,
 411         .clkdm_offs       = OMAP54XX_PRM_EMU_CM_EMU_CDOFFS,
 412         .flags            = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
 413 };
 414
 415 static struct clockdomain cam_54xx_clkdm = {
 416         .name             = "cam_clkdm",
 417         .pwrdm            = { .name = "cam_pwrdm" },
 418         .prcm_partition   = OMAP54XX_CM_CORE_PARTITION,
 419         .cm_inst          = OMAP54XX_CM_CORE_CAM_INST,
 420         .clkdm_offs       = OMAP54XX_CM_CORE_CAM_CAM_CDOFFS,
 421         .wkdep_srcs       = cam_wkup_sleep_deps,
 422         .sleepdep_srcs    = cam_wkup_sleep_deps,
 423         .flags            = CLKDM_CAN_HWSUP_SWSUP,
 424 };
 425
 426 /* As clockdomains are added or removed above, this list must also be changed */
 427 static struct clockdomain *clockdomains_omap54xx[] __initdata = {
 428         &l4sec_54xx_clkdm,
 429         &iva_54xx_clkdm,
 430         &mipiext_54xx_clkdm,
 431         &l3main2_54xx_clkdm,
 432         &l3main1_54xx_clkdm,
 433         &custefuse_54xx_clkdm,
 434         &ipu_54xx_clkdm,
 435         &l4cfg_54xx_clkdm,
 436         &abe_54xx_clkdm,
 437         &dss_54xx_clkdm,
 438         &dsp_54xx_clkdm,
 439         &c2c_54xx_clkdm,
 440         &l4per_54xx_clkdm,
 441         &gpu_54xx_clkdm,
 442         &wkupaon_54xx_clkdm,
 443         &mpu0_54xx_clkdm,
 444         &mpu1_54xx_clkdm,
 445         &coreaon_54xx_clkdm,
 446         &mpu_54xx_clkdm,
 447         &l3init_54xx_clkdm,
 448         &dma_54xx_clkdm,
 449         &l3instr_54xx_clkdm,
 450         &emif_54xx_clkdm,
 451         &emu_54xx_clkdm,
 452         &cam_54xx_clkdm,
 453         NULL
 454 };
 455
 456 void __init omap54xx_clockdomains_init(void)
 457 {
 458         clkdm_register_platform_funcs(&omap4_clkdm_operations);
 459         clkdm_register_clkdms(clockdomains_omap54xx);
 460         clkdm_complete_init();
 461 }