arch/arm/boot/dts/tegra30-ouya.dts

   1 // SPDX-License-Identifier: GPL-2.0
   2 /dts-v1/;
   3
   4 #include <dt-bindings/input/gpio-keys.h>
   5 #include <dt-bindings/input/input.h>
   6 #include <dt-bindings/thermal/thermal.h>
   7
   8 #include "tegra30.dtsi"
   9 #include "tegra30-cpu-opp.dtsi"
  10 #include "tegra30-cpu-opp-microvolt.dtsi"
  11
  12 / {
  13         model = "Ouya Game Console";
  14         compatible = "ouya,ouya", "nvidia,tegra30";
  15
  16         aliases {
  17                 mmc0 = &sdmmc4; /* eMMC */
  18                 mmc1 = &sdmmc3; /* WiFi */
  19                 rtc0 = &pmic;
  20                 rtc1 = "/rtc@7000e000";
  21                 serial0 = &uartd; /* Debug Port */
  22                 serial1 = &uartc; /* Bluetooth */
  23         };
  24
  25         chosen {
  26                 stdout-path = "serial0:115200n8";
  27         };
  28
  29         memory@80000000 {
  30                 reg = <0x80000000 0x40000000>;
  31         };
  32
  33         reserved-memory {
  34                 #address-cells = <1>;
  35                 #size-cells = <1>;
  36                 ranges;
  37
  38                 linux,cma@80000000 {
  39                         compatible = "shared-dma-pool";
  40                         alloc-ranges = <0x80000000 0x30000000>;
  41                         size = <0x10000000>; /* 256MiB */
  42                         linux,cma-default;
  43                         reusable;
  44                 };
  45
  46                 ramoops@bfdf0000 {
  47                         compatible = "ramoops";
  48                         reg = <0xbfdf0000 0x10000>;     /* 64kB */
  49                         console-size = <0x8000>;        /* 32kB */
  50                         record-size = <0x400>;          /*  1kB */
  51                         ecc-size = <16>;
  52                 };
  53
  54                 trustzone@bfe00000 {
  55                         reg = <0xbfe00000 0x200000>;
  56                         no-map;
  57                 };
  58         };
  59
  60         host1x@50000000 {
  61                 hdmi@54280000 {
  62                         status = "okay";
  63                         vdd-supply = <&vdd_vid_reg>;
  64                         pll-supply = <&ldo7_reg>;
  65                         hdmi-supply = <&sys_3v3_reg>;
  66                         nvidia,ddc-i2c-bus = <&hdmi_ddc>;
  67                         nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>;
  68                 };
  69         };
  70
  71         gpio: gpio@6000d000 {
  72                 gpio-ranges = <&pinmux 0 0 248>;
  73                 #reset-cells = <1>;
  74         };
  75
  76         pinmux@70000868 {
  77                 pinctrl-names = "default";
  78                 pinctrl-0 = <&state_default>;
  79                 state_default: pinmux {
  80                         /* located at $state_default below */
  81                 };
  82         };
  83
  84         uartc: serial@70006200 {
  85                 status = "okay";
  86                 compatible = "nvidia,tegra30-hsuart";
  87
  88                 nvidia,adjust-baud-rates = <0 9600 100>,
  89                                            <9600 115200 200>,
  90                                            <1000000 4000000 136>;
  91
  92                 /* Azurewave AW-NH660 BCM4330B1 */
  93                 bluetooth {
  94                         compatible = "brcm,bcm4330-bt";
  95
  96                         max-speed = <4000000>;
  97
  98                         clocks = <&tegra_pmc TEGRA_PMC_CLK_BLINK>;
  99                         clock-names = "txco";
 100
 101                         vbat-supply  = <&sys_3v3_reg>;
 102                         vddio-supply = <&vdd_1v8>;
 103
 104                         shutdown-gpios = <&gpio TEGRA_GPIO(U, 0) GPIO_ACTIVE_HIGH>;
 105                         device-wakeup-gpios = <&gpio TEGRA_GPIO(U, 1) GPIO_ACTIVE_HIGH>;
 106                         host-wakeup-gpios = <&gpio TEGRA_GPIO(U, 6) GPIO_ACTIVE_HIGH>;
 107                 };
 108         };
 109
 110         uartd: serial@70006300 {
 111                 status = "okay";
 112         };
 113
 114         hdmi_ddc: i2c@7000c700 {
 115                 status = "okay";
 116                 clock-frequency = <100000>;
 117         };
 118
 119         i2c@7000d000 {
 120                 status = "okay";
 121                 clock-frequency = <400000>;
 122
 123                 cpu_temp: nct1008@4c {
 124                         compatible = "onnn,nct1008";
 125                         reg = <0x4c>;
 126                         vcc-supply = <&sys_3v3_reg>;
 127                         #thermal-sensor-cells = <1>;
 128 /*
 129  *                      The interrupt is bugged, once triggered it never clears.
 130  *                      interrupt-parent = <&gpio>;
 131  *                      interrupts = <TEGRA_GPIO(CC, 2) IRQ_TYPE_LEVEL_LOW>;
 132  */
 133                 };
 134
 135                 pmic: pmic@2d {
 136                         compatible = "ti,tps65911";
 137                         reg = <0x2d>;
 138
 139                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 140                         #interrupt-cells = <2>;
 141                         interrupt-controller;
 142                         wakeup-source;
 143
 144                         ti,en-gpio-sleep = <0 1 1 1 1 1 0 0 1>;
 145                         ti,system-power-controller;
 146                         ti,sleep-keep-ck32k;
 147                         ti,sleep-enable;
 148
 149                         #gpio-cells = <2>;
 150                         gpio-controller;
 151
 152                         vcc1-supply = <&vdd_5v0_reg>;
 153                         vcc2-supply = <&vdd_5v0_reg>;
 154                         vcc3-supply = <&vdd_1v8>;
 155                         vcc4-supply = <&vdd_5v0_reg>;
 156                         vcc5-supply = <&vdd_5v0_reg>;
 157                         vcc6-supply = <&vdd2_reg>;
 158                         vcc7-supply = <&vdd_5v0_reg>;
 159                         vccio-supply = <&vdd_5v0_reg>;
 160
 161                         regulators {
 162                                 vdd1_reg: vdd1 {
 163                                         regulator-name = "vddio_ddr_1v2";
 164                                         regulator-min-microvolt = <1200000>;
 165                                         regulator-max-microvolt = <1200000>;
 166                                         regulator-always-on;
 167                                 };
 168
 169                                 vdd2_reg: vdd2 {
 170                                         regulator-name = "vdd_1v5_gen";
 171                                         regulator-min-microvolt = <1500000>;
 172                                         regulator-max-microvolt = <1500000>;
 173                                         regulator-always-on;
 174                                 };
 175
 176                                 vdd_cpu: vddctrl {
 177                                         regulator-name = "vdd_cpu,vdd_sys";
 178                                         regulator-min-microvolt = <800000>;
 179                                         regulator-max-microvolt = <1270000>;
 180                                         regulator-coupled-with = <&vdd_core>;
 181                                         regulator-coupled-max-spread = <300000>;
 182                                         regulator-max-step-microvolt = <100000>;
 183                                         regulator-always-on;
 184
 185                                         nvidia,tegra-cpu-regulator;
 186                                 };
 187
 188                                 vdd_1v8: vio {
 189                                         regulator-name = "vdd_1v8_gen";
 190                                         regulator-min-microvolt = <1800000>;
 191                                         regulator-max-microvolt = <1800000>;
 192                                         regulator-always-on;
 193                                 };
 194
 195                                 ldo1_reg: ldo1 {
 196                                         regulator-name = "vdd_pexa,vdd_pexb";
 197                                         regulator-min-microvolt = <1050000>;
 198                                         regulator-max-microvolt = <1050000>;
 199                                         regulator-always-on;
 200                                 };
 201
 202                                 ldo2_reg: ldo2 {
 203                                         regulator-name = "vdd_sata,avdd_plle";
 204                                         regulator-min-microvolt = <1050000>;
 205                                         regulator-max-microvolt = <1050000>;
 206                                         regulator-always-on;
 207                                 };
 208
 209                                 /* LDO3 is not connected to anything */
 210
 211                                 ldo4_reg: ldo4 {
 212                                         regulator-name = "vdd_rtc";
 213                                         regulator-min-microvolt = <1200000>;
 214                                         regulator-max-microvolt = <1200000>;
 215                                         regulator-always-on;
 216                                 };
 217
 218                                 ldo5_reg: ldo5 {
 219                                         regulator-name = "vddio_sdmmc,avdd_vdac";
 220                                         regulator-min-microvolt = <1800000>;
 221                                         regulator-max-microvolt = <3300000>;
 222                                         regulator-always-on;
 223                                 };
 224
 225                                 ldo6_reg: ldo6 {
 226                                         regulator-name = "avdd_dsi_csi,pwrdet_mipi";
 227                                         regulator-min-microvolt = <1200000>;
 228                                         regulator-max-microvolt = <1200000>;
 229                                         regulator-always-on;
 230                                 };
 231
 232                                 ldo7_reg: ldo7 {
 233                                         regulator-name = "vdd_pllm,x,u,a_p_c_s";
 234                                         regulator-min-microvolt = <1200000>;
 235                                         regulator-max-microvolt = <1200000>;
 236                                         regulator-always-on;
 237                                 };
 238
 239                                 ldo8_reg: ldo8 {
 240                                         regulator-name = "vdd_ddr_hs";
 241                                         regulator-min-microvolt = <1000000>;
 242                                         regulator-max-microvolt = <1000000>;
 243                                         regulator-always-on;
 244                                 };
 245                         };
 246                 };
 247
 248                 vdd_core: tps62361@60 {
 249                         compatible = "ti,tps62361";
 250                         reg = <0x60>;
 251
 252                         regulator-name = "vdd_core";
 253                         regulator-min-microvolt = <950000>;
 254                         regulator-max-microvolt = <1350000>;
 255                         regulator-coupled-with = <&vdd_cpu>;
 256                         regulator-coupled-max-spread = <300000>;
 257                         regulator-max-step-microvolt = <100000>;
 258                         regulator-boot-on;
 259                         regulator-always-on;
 260                         ti,vsel0-state-high;
 261                         ti,vsel1-state-high;
 262                         ti,enable-vout-discharge;
 263
 264                         nvidia,tegra-core-regulator;
 265                 };
 266         };
 267
 268         pmc@7000e400 {
 269                 status = "okay";
 270                 nvidia,invert-interrupt;
 271                 nvidia,suspend-mode = <1>;
 272                 nvidia,cpu-pwr-good-time = <2000>;
 273                 nvidia,cpu-pwr-off-time = <200>;
 274                 nvidia,core-pwr-good-time = <3845 3845>;
 275                 nvidia,core-pwr-off-time = <458>;
 276                 nvidia,core-power-req-active-high;
 277                 nvidia,sys-clock-req-active-high;
 278         };
 279
 280         mc_timings: memory-controller@7000f000 {
 281                 /* timings located at &mc_timings below */
 282         };
 283
 284         emc_timings: memory-controller@7000f400 {
 285                 /* timings located at &emc_timings below */
 286         };
 287
 288         hda@70030000 {
 289                 status = "okay";
 290         };
 291
 292         wifi_pwrseq: wifi_pwrseq {
 293                 compatible = "mmc-pwrseq-simple";
 294
 295                 clocks = <&tegra_pmc TEGRA_PMC_CLK_BLINK>;
 296                 clock-names = "ext_clock";
 297
 298                 reset-gpios = <&gpio TEGRA_GPIO(D, 3) GPIO_ACTIVE_LOW>;
 299                 post-power-on-delay-ms = <300>;
 300                 power-off-delay-us = <300>;
 301         };
 302
 303         sdmmc3: mmc@78000400 {
 304                 status = "okay";
 305
 306                 #address-cells = <1>;
 307                 #size-cells = <0>;
 308
 309                 assigned-clocks = <&tegra_car TEGRA30_CLK_SDMMC3>;
 310                 assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_C>;
 311                 assigned-clock-rates = <50000000>;
 312
 313                 max-frequency = <50000000>;
 314                 keep-power-in-suspend;
 315
 316                 bus-width = <4>;
 317                 non-removable;
 318
 319                 mmc-pwrseq = <&wifi_pwrseq>;
 320                 vmmc-supply = <&sdmmc_3v3_reg>;
 321                 vqmmc-supply = <&vdd_1v8>;
 322
 323                 /* Azurewave AW-NH660 BCM4330 */
 324                 brcmf: wifi@1 {
 325                         reg = <1>;
 326                         compatible = "brcm,bcm4329-fmac";
 327                         interrupt-parent = <&gpio>;
 328                         interrupts = <TEGRA_GPIO(O, 4) IRQ_TYPE_LEVEL_HIGH>;
 329                         interrupt-names = "host-wake";
 330                 };
 331         };
 332
 333         sdmmc4: mmc@78000600 {
 334                 status = "okay";
 335
 336                 keep-power-in-suspend;
 337                 bus-width = <8>;
 338                 non-removable;
 339                 vmmc-supply = <&sys_3v3_reg>;
 340                 vqmmc-supply = <&vdd_1v8>;
 341                 nvidia,default-tap = <0x0F>;
 342                 max-frequency = <25500000>;
 343         };
 344
 345         usb@7d000000 {
 346                 compatible = "nvidia,tegra30-udc";
 347                 status = "okay";
 348         };
 349
 350         usb-phy@7d000000 {
 351                 status = "okay";
 352                 dr_mode = "peripheral";
 353         };
 354
 355         usb@7d004000 {
 356                 status = "okay";
 357                 #address-cells = <1>;
 358                 #size-cells = <0>;
 359
 360                 smsc@2 { /* SMSC 10/100T Ethernet Controller */
 361                         compatible = "usb424,9e00";
 362                         reg = <2>;
 363                         local-mac-address = [00 11 22 33 44 55];
 364                 };
 365         };
 366
 367         usb-phy@7d004000 {
 368                 vbus-supply = <&vdd_smsc>;
 369                 status = "okay";
 370         };
 371
 372         usb@7d008000 {
 373                 status = "okay";
 374         };
 375
 376         usb-phy@7d008000 {
 377                 vbus-supply = <&usb3_vbus_reg>;
 378                 status = "okay";
 379         };
 380
 381         /* PMIC has a built-in 32KHz oscillator which is used by PMC */
 382         clk32k_in: clock {
 383                 compatible = "fixed-clock";
 384                 #clock-cells = <0>;
 385                 clock-frequency = <32768>;
 386                 clock-output-names = "pmic-oscillator";
 387         };
 388
 389         cpus {
 390                 cpu0: cpu@0 {
 391                         operating-points-v2 = <&cpu0_opp_table>;
 392                         cpu-supply = <&vdd_cpu>;
 393                         #cooling-cells = <2>;
 394                 };
 395
 396                 cpu1: cpu@1 {
 397                         operating-points-v2 = <&cpu0_opp_table>;
 398                         cpu-supply = <&vdd_cpu>;
 399                         #cooling-cells = <2>;
 400                 };
 401
 402                 cpu2: cpu@2 {
 403                         operating-points-v2 = <&cpu0_opp_table>;
 404                         cpu-supply = <&vdd_cpu>;
 405                         #cooling-cells = <2>;
 406                 };
 407
 408                 cpu3: cpu@3 {
 409                         operating-points-v2 = <&cpu0_opp_table>;
 410                         cpu-supply = <&vdd_cpu>;
 411                         #cooling-cells = <2>;
 412                 };
 413         };
 414
 415         firmware {
 416                 trusted-foundations {
 417                         compatible = "tlm,trusted-foundations";
 418                         tlm,version-major = <0x0>;
 419                         tlm,version-minor = <0x0>;
 420                 };
 421         };
 422
 423         fan: gpio_fan {
 424                 compatible = "gpio-fan";
 425                 gpios = <&gpio TEGRA_GPIO(J, 2) GPIO_ACTIVE_HIGH>;
 426                 gpio-fan,speed-map = <0    0
 427                                       4500 1>;
 428                 #cooling-cells = <2>;
 429         };
 430
 431         thermal-zones {
 432                 cpu_thermal: cpu-thermal {
 433                         polling-delay = <5000>;
 434                         polling-delay-passive = <5000>;
 435
 436                         thermal-sensors = <&cpu_temp 1>;
 437
 438                         trips {
 439                                 cpu_alert0: cpu-alert0 {
 440                                         temperature = <50000>;
 441                                         hysteresis = <10000>;
 442                                         type = "active";
 443                                 };
 444                                 cpu_alert1: cpu-alert1 {
 445                                         temperature = <70000>;
 446                                         hysteresis = <5000>;
 447                                         type = "passive";
 448                                 };
 449                                 cpu_crit: cpu-crit {
 450                                         temperature = <90000>;
 451                                         hysteresis = <2000>;
 452                                         type = "critical";
 453                                 };
 454                         };
 455
 456                         cooling-maps {
 457                                 map0 {
 458                                         trip = <&cpu_alert0>;
 459                                         cooling-device = <&fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 460                                 };
 461                                 map1 {
 462                                         trip = <&cpu_alert1>;
 463                                         cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 464                                                          <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 465                                                          <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 466                                                          <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 467                                                          <&actmon THERMAL_NO_LIMIT
 468                                                                   THERMAL_NO_LIMIT>;
 469                                 };
 470                         };
 471                 };
 472         };
 473
 474         vdd_12v_in: vdd_12v_in {
 475                 compatible = "regulator-fixed";
 476                 regulator-name = "vdd_12v_in";
 477                 regulator-min-microvolt = <12000000>;
 478                 regulator-max-microvolt = <12000000>;
 479                 regulator-always-on;
 480         };
 481
 482         sdmmc_3v3_reg: sdmmc_3v3_reg {
 483                 compatible = "regulator-fixed";
 484                 regulator-name = "sdmmc_3v3";
 485                 regulator-min-microvolt = <3300000>;
 486                 regulator-max-microvolt = <3300000>;
 487                 enable-active-high;
 488                 regulator-always-on;
 489                 gpio = <&gpio TEGRA_GPIO(D, 4) GPIO_ACTIVE_HIGH>;
 490                 vin-supply = <&sys_3v3_reg>;
 491         };
 492
 493         vdd_fuse_3v3_reg: vdd_fuse_3v3_reg {
 494                 compatible = "regulator-fixed";
 495                 regulator-name = "vdd_fuse_3v3";
 496                 regulator-min-microvolt = <3300000>;
 497                 regulator-max-microvolt = <3300000>;
 498                 enable-active-high;
 499                 gpio = <&gpio TEGRA_GPIO(L, 6) GPIO_ACTIVE_HIGH>;
 500                 vin-supply = <&sys_3v3_reg>;
 501                 regulator-always-on;
 502         };
 503
 504         vdd_vid_reg: vdd_vid_reg {
 505                 compatible = "regulator-fixed";
 506                 regulator-name = "vddio_vid";
 507                 regulator-min-microvolt = <5000000>;
 508                 regulator-max-microvolt = <5000000>;
 509                 enable-active-high;
 510                 gpio = <&gpio TEGRA_GPIO(T, 0) GPIO_ACTIVE_HIGH>;
 511                 vin-supply = <&vdd_5v0_reg>;
 512                 regulator-boot-on;
 513         };
 514
 515         ddr_reg: ddr_reg {
 516                 compatible = "regulator-fixed";
 517                 regulator-name = "vdd_ddr";
 518                 regulator-min-microvolt = <1500000>;
 519                 regulator-max-microvolt = <1500000>;
 520                 regulator-always-on;
 521                 enable-active-high;
 522                 gpio = <&pmic 7 GPIO_ACTIVE_HIGH>;
 523                 regulator-boot-on;
 524                 vin-supply = <&vdd_12v_in>;
 525         };
 526
 527         sys_3v3_reg: sys_3v3_reg {
 528                 compatible = "regulator-fixed";
 529                 regulator-name = "sys_3v3";
 530                 regulator-min-microvolt = <3300000>;
 531                 regulator-max-microvolt = <3300000>;
 532                 enable-active-high;
 533                 gpio = <&pmic 6 GPIO_ACTIVE_HIGH>;
 534                 regulator-always-on;
 535                 regulator-boot-on;
 536                 vin-supply = <&vdd_12v_in>;
 537         };
 538
 539         vdd_5v0_reg: vdd_5v0_reg {
 540                 compatible = "regulator-fixed";
 541                 regulator-name = "vdd_5v0";
 542                 regulator-min-microvolt = <5000000>;
 543                 regulator-max-microvolt = <5000000>;
 544                 enable-active-high;
 545                 gpio = <&pmic 0 GPIO_ACTIVE_HIGH>;
 546                 regulator-always-on;
 547                 regulator-boot-on;
 548                 vin-supply = <&vdd_12v_in>;
 549         };
 550
 551         vdd_smsc: vdd_smsc {
 552                 compatible = "regulator-fixed";
 553                 regulator-name = "vdd_smsc";
 554                 enable-active-high;
 555                 gpio = <&gpio TEGRA_GPIO(DD, 5) GPIO_ACTIVE_HIGH>;
 556         };
 557
 558         usb3_vbus_reg: usb3_vbus_reg {
 559                 compatible = "regulator-fixed";
 560                 regulator-name = "usb3_vbus";
 561                 regulator-min-microvolt = <5000000>;
 562                 regulator-max-microvolt = <5000000>;
 563                 enable-active-high;
 564                 gpio = <&gpio TEGRA_GPIO(DD, 4) GPIO_ACTIVE_HIGH>;
 565                 vin-supply = <&vdd_5v0_reg>;
 566         };
 567
 568         gpio-keys {
 569                 compatible = "gpio-keys";
 570
 571                 power {
 572                         gpios = <&gpio TEGRA_GPIO(V, 0) GPIO_ACTIVE_LOW>;
 573                         debounce-interval = <10>;
 574                         linux,code = <KEY_POWER>;
 575                         wakeup-event-action = <EV_ACT_ASSERTED>;
 576                         wakeup-source;
 577                 };
 578         };
 579
 580
 581         leds {
 582                 compatible = "gpio-leds";
 583
 584                 led-power {
 585                         label = "power-led";
 586                         gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>;
 587                         default-state = "on";
 588                         linux,default-trigger = "heartbeat";
 589                         retain-state-suspended;
 590                 };
 591         };
 592 };
 593 &mc_timings {
 594         emc-timings-0 {
 595                 nvidia,ram-code = <0>; /* Samsung RAM */
 596                 timing-25500000 {
 597                         clock-frequency = <25500000>;
 598                         nvidia,emem-configuration = <
 599                                 0x00030003 /* MC_EMEM_ARB_CFG */
 600                                 0xc0000010 /* MC_EMEM_ARB_OUTSTANDING_REQ */
 601                                 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */
 602                                 0x00000001 /* MC_EMEM_ARB_TIMING_RP */
 603                                 0x00000002 /* MC_EMEM_ARB_TIMING_RC */
 604                                 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */
 605                                 0x00000001 /* MC_EMEM_ARB_TIMING_FAW */
 606                                 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */
 607                                 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */
 608                                 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */
 609                                 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */
 610                                 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */
 611                                 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */
 612                                 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */
 613                                 0x06020102 /* MC_EMEM_ARB_DA_TURNS */
 614                                 0x000a0502 /* MC_EMEM_ARB_DA_COVERS */
 615                                 0x75830303 /* MC_EMEM_ARB_MISC0 */
 616                                 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */
 617                         >;
 618                 };
 619                 timing-51000000 {
 620                         clock-frequency = <51000000>;
 621                         nvidia,emem-configuration = <
 622                                 0x00010003 /* MC_EMEM_ARB_CFG */
 623                                 0xc0000010 /* MC_EMEM_ARB_OUTSTANDING_REQ */
 624                                 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */
 625                                 0x00000001 /* MC_EMEM_ARB_TIMING_RP */
 626                                 0x00000002 /* MC_EMEM_ARB_TIMING_RC */
 627                                 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */
 628                                 0x00000001 /* MC_EMEM_ARB_TIMING_FAW */
 629                                 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */
 630                                 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */
 631                                 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */
 632                                 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */
 633                                 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */
 634                                 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */
 635                                 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */
 636                                 0x06020102 /* MC_EMEM_ARB_DA_TURNS */
 637                                 0x000a0502 /* MC_EMEM_ARB_DA_COVERS */
 638                                 0x74630303 /* MC_EMEM_ARB_MISC0 */
 639                                 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */
 640                         >;
 641                 };
 642                 timing-102000000 {
 643                         clock-frequency = <102000000>;
 644                         nvidia,emem-configuration = <
 645                                 0x00000003 /* MC_EMEM_ARB_CFG */
 646                                 0xc0000018 /* MC_EMEM_ARB_OUTSTANDING_REQ */
 647                                 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */
 648                                 0x00000001 /* MC_EMEM_ARB_TIMING_RP */
 649                                 0x00000003 /* MC_EMEM_ARB_TIMING_RC */
 650                                 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */
 651                                 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */
 652                                 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */
 653                                 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */
 654                                 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */
 655                                 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */
 656                                 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */
 657                                 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */
 658                                 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */
 659                                 0x06020102 /* MC_EMEM_ARB_DA_TURNS */
 660                                 0x000a0503 /* MC_EMEM_ARB_DA_COVERS */
 661                                 0x73c30504 /* MC_EMEM_ARB_MISC0 */
 662                                 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */
 663                         >;
 664                 };
 665                 timing-204000000 {
 666                         clock-frequency = <204000000>;
 667                         nvidia,emem-configuration = <
 668                                 0x00000006 /* MC_EMEM_ARB_CFG */
 669                                 0xc0000025 /* MC_EMEM_ARB_OUTSTANDING_REQ */
 670                                 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */
 671                                 0x00000001 /* MC_EMEM_ARB_TIMING_RP */
 672                                 0x00000005 /* MC_EMEM_ARB_TIMING_RC */
 673                                 0x00000002 /* MC_EMEM_ARB_TIMING_RAS */
 674                                 0x00000004 /* MC_EMEM_ARB_TIMING_FAW */
 675                                 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */
 676                                 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */
 677                                 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */
 678                                 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */
 679                                 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */
 680                                 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */
 681                                 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */
 682                                 0x06020102 /* MC_EMEM_ARB_DA_TURNS */
 683                                 0x000a0505 /* MC_EMEM_ARB_DA_COVERS */
 684                                 0x73840a06 /* MC_EMEM_ARB_MISC0 */
 685                                 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */
 686                         >;
 687                 };
 688                 timing-400000000 {
 689                         clock-frequency = <400000000>;
 690                         nvidia,emem-configuration = <
 691                                 0x0000000c /* MC_EMEM_ARB_CFG */
 692                                 0xc0000048 /* MC_EMEM_ARB_OUTSTANDING_REQ */
 693                                 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */
 694                                 0x00000002 /* MC_EMEM_ARB_TIMING_RP */
 695                                 0x00000009 /* MC_EMEM_ARB_TIMING_RC */
 696                                 0x00000005 /* MC_EMEM_ARB_TIMING_RAS */
 697                                 0x00000007 /* MC_EMEM_ARB_TIMING_FAW */
 698                                 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */
 699                                 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */
 700                                 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */
 701                                 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */
 702                                 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */
 703                                 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */
 704                                 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */
 705                                 0x06030202 /* MC_EMEM_ARB_DA_TURNS */
 706                                 0x000d0709 /* MC_EMEM_ARB_DA_COVERS */
 707                                 0x7086120a /* MC_EMEM_ARB_MISC0 */
 708                                 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */
 709                         >;
 710                 };
 711                 timing-800000000 {
 712                         clock-frequency = <800000000>;
 713                         nvidia,emem-configuration = <
 714                                 0x00000018 /* MC_EMEM_ARB_CFG */
 715                                 0xc0000090 /* MC_EMEM_ARB_OUTSTANDING_REQ */
 716                                 0x00000004 /* MC_EMEM_ARB_TIMING_RCD */
 717                                 0x00000005 /* MC_EMEM_ARB_TIMING_RP */
 718                                 0x00000013 /* MC_EMEM_ARB_TIMING_RC */
 719                                 0x0000000c /* MC_EMEM_ARB_TIMING_RAS */
 720                                 0x0000000f /* MC_EMEM_ARB_TIMING_FAW */
 721                                 0x00000002 /* MC_EMEM_ARB_TIMING_RRD */
 722                                 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */
 723                                 0x0000000c /* MC_EMEM_ARB_TIMING_WAP2PRE */
 724                                 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */
 725                                 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */
 726                                 0x00000004 /* MC_EMEM_ARB_TIMING_R2W */
 727                                 0x00000008 /* MC_EMEM_ARB_TIMING_W2R */
 728                                 0x08040202 /* MC_EMEM_ARB_DA_TURNS */
 729                                 0x00160d13 /* MC_EMEM_ARB_DA_COVERS */
 730                                 0x712c2414 /* MC_EMEM_ARB_MISC0 */
 731                                 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */
 732                         >;
 733                 };
 734         };
 735         emc-timings-1 {
 736                 nvidia,ram-code = <1>; /* Hynix M RAM */
 737                 timing-25500000 {
 738                         clock-frequency = <25500000>;
 739                         nvidia,emem-configuration = <
 740                                 0x00030003 /* MC_EMEM_ARB_CFG */
 741                                 0xc0000010 /* MC_EMEM_ARB_OUTSTANDING_REQ */
 742                                 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */
 743                                 0x00000001 /* MC_EMEM_ARB_TIMING_RP */
 744                                 0x00000002 /* MC_EMEM_ARB_TIMING_RC */
 745                                 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */
 746                                 0x00000001 /* MC_EMEM_ARB_TIMING_FAW */
 747                                 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */
 748                                 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */
 749                                 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */
 750                                 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */
 751                                 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */
 752                                 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */
 753                                 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */
 754                                 0x06020102 /* MC_EMEM_ARB_DA_TURNS */
 755                                 0x000a0502 /* MC_EMEM_ARB_DA_COVERS */
 756                                 0x75830303 /* MC_EMEM_ARB_MISC0 */
 757                                 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */
 758                         >;
 759                 };
 760                 timing-51000000 {
 761                         clock-frequency = <51000000>;
 762                         nvidia,emem-configuration = <
 763                                 0x00010003 /* MC_EMEM_ARB_CFG */
 764                                 0xc0000010 /* MC_EMEM_ARB_OUTSTANDING_REQ */
 765                                 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */
 766                                 0x00000001 /* MC_EMEM_ARB_TIMING_RP */
 767                                 0x00000002 /* MC_EMEM_ARB_TIMING_RC */
 768                                 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */
 769                                 0x00000001 /* MC_EMEM_ARB_TIMING_FAW */
 770                                 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */
 771                                 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */
 772                                 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */
 773                                 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */
 774                                 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */
 775                                 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */
 776                                 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */
 777                                 0x06020102 /* MC_EMEM_ARB_DA_TURNS */
 778                                 0x000a0502 /* MC_EMEM_ARB_DA_COVERS */
 779                                 0x74630303 /* MC_EMEM_ARB_MISC0 */
 780                                 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */
 781                         >;
 782                 };
 783                 timing-102000000 {
 784                         clock-frequency = <102000000>;
 785                         nvidia,emem-configuration = <
 786                                 0x00000003 /* MC_EMEM_ARB_CFG */
 787                                 0xc0000018 /* MC_EMEM_ARB_OUTSTANDING_REQ */
 788                                 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */
 789                                 0x00000001 /* MC_EMEM_ARB_TIMING_RP */
 790                                 0x00000003 /* MC_EMEM_ARB_TIMING_RC */
 791                                 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */
 792                                 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */
 793                                 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */
 794                                 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */
 795                                 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */
 796                                 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */
 797                                 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */
 798                                 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */
 799                                 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */
 800                                 0x06020102 /* MC_EMEM_ARB_DA_TURNS */
 801                                 0x000a0503 /* MC_EMEM_ARB_DA_COVERS */
 802                                 0x73c30504 /* MC_EMEM_ARB_MISC0 */
 803                                 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */
 804                         >;
 805                 };
 806                 timing-204000000 {
 807                         clock-frequency = <204000000>;
 808                         nvidia,emem-configuration = <
 809                                 0x00000006 /* MC_EMEM_ARB_CFG */
 810                                 0xc0000025 /* MC_EMEM_ARB_OUTSTANDING_REQ */
 811                                 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */
 812                                 0x00000001 /* MC_EMEM_ARB_TIMING_RP */
 813                                 0x00000005 /* MC_EMEM_ARB_TIMING_RC */
 814                                 0x00000002 /* MC_EMEM_ARB_TIMING_RAS */
 815                                 0x00000004 /* MC_EMEM_ARB_TIMING_FAW */
 816                                 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */
 817                                 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */
 818                                 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */
 819                                 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */
 820                                 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */
 821                                 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */
 822                                 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */
 823                                 0x06020102 /* MC_EMEM_ARB_DA_TURNS */
 824                                 0x000a0505 /* MC_EMEM_ARB_DA_COVERS */
 825                                 0x73840a06 /* MC_EMEM_ARB_MISC0 */
 826                                 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */
 827                         >;
 828                 };
 829                 timing-400000000 {
 830                         clock-frequency = <400000000>;
 831                         nvidia,emem-configuration = <
 832                                 0x0000000c /* MC_EMEM_ARB_CFG */
 833                                 0xc0000048 /* MC_EMEM_ARB_OUTSTANDING_REQ */
 834                                 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */
 835                                 0x00000002 /* MC_EMEM_ARB_TIMING_RP */
 836                                 0x00000009 /* MC_EMEM_ARB_TIMING_RC */
 837                                 0x00000005 /* MC_EMEM_ARB_TIMING_RAS */
 838                                 0x00000007 /* MC_EMEM_ARB_TIMING_FAW */
 839                                 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */
 840                                 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */
 841                                 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */
 842                                 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */
 843                                 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */
 844                                 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */
 845                                 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */
 846                                 0x06030202 /* MC_EMEM_ARB_DA_TURNS */
 847                                 0x000d0709 /* MC_EMEM_ARB_DA_COVERS */
 848                                 0x7086120a /* MC_EMEM_ARB_MISC0 */
 849                                 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */
 850                         >;
 851                 };
 852                 timing-800000000 {
 853                         clock-frequency = <800000000>;
 854                         nvidia,emem-configuration = <
 855                                 0x00000018 /* MC_EMEM_ARB_CFG */
 856                                 0xc0000090 /* MC_EMEM_ARB_OUTSTANDING_REQ */
 857                                 0x00000004 /* MC_EMEM_ARB_TIMING_RCD */
 858                                 0x00000005 /* MC_EMEM_ARB_TIMING_RP */
 859                                 0x00000013 /* MC_EMEM_ARB_TIMING_RC */
 860                                 0x0000000c /* MC_EMEM_ARB_TIMING_RAS */
 861                                 0x0000000f /* MC_EMEM_ARB_TIMING_FAW */
 862                                 0x00000002 /* MC_EMEM_ARB_TIMING_RRD */
 863                                 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */
 864                                 0x0000000c /* MC_EMEM_ARB_TIMING_WAP2PRE */
 865                                 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */
 866                                 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */
 867                                 0x00000004 /* MC_EMEM_ARB_TIMING_R2W */
 868                                 0x00000008 /* MC_EMEM_ARB_TIMING_W2R */
 869                                 0x08040202 /* MC_EMEM_ARB_DA_TURNS */
 870                                 0x00160d13 /* MC_EMEM_ARB_DA_COVERS */
 871                                 0x712c2414 /* MC_EMEM_ARB_MISC0 */
 872                                 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */
 873                         >;
 874                 };
 875         };
 876         emc-timings-2 {
 877                 nvidia,ram-code = <2>; /* Hynix A RAM */
 878                 timing-25500000 {
 879                         clock-frequency = <25500000>;
 880                         nvidia,emem-configuration = <
 881                                 0x00030003 /* MC_EMEM_ARB_CFG */
 882                                 0xc0000010 /* MC_EMEM_ARB_OUTSTANDING_REQ */
 883                                 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */
 884                                 0x00000001 /* MC_EMEM_ARB_TIMING_RP */
 885                                 0x00000002 /* MC_EMEM_ARB_TIMING_RC */
 886                                 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */
 887                                 0x00000001 /* MC_EMEM_ARB_TIMING_FAW */
 888                                 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */
 889                                 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */
 890                                 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */
 891                                 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */
 892                                 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */
 893                                 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */
 894                                 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */
 895                                 0x06020102 /* MC_EMEM_ARB_DA_TURNS */
 896                                 0x000a0502 /* MC_EMEM_ARB_DA_COVERS */
 897                                 0x75e30303 /* MC_EMEM_ARB_MISC0 */
 898                                 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */
 899                         >;
 900                 };
 901                 timing-51000000 {
 902                         clock-frequency = <51000000>;
 903                         nvidia,emem-configuration = <
 904                                 0x00010003 /* MC_EMEM_ARB_CFG */
 905                                 0xc0000010 /* MC_EMEM_ARB_OUTSTANDING_REQ */
 906                                 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */
 907                                 0x00000001 /* MC_EMEM_ARB_TIMING_RP */
 908                                 0x00000002 /* MC_EMEM_ARB_TIMING_RC */
 909                                 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */
 910                                 0x00000001 /* MC_EMEM_ARB_TIMING_FAW */
 911                                 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */
 912                                 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */
 913                                 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */
 914                                 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */
 915                                 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */
 916                                 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */
 917                                 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */
 918                                 0x06020102 /* MC_EMEM_ARB_DA_TURNS */
 919                                 0x000a0502 /* MC_EMEM_ARB_DA_COVERS */
 920                                 0x74e30303 /* MC_EMEM_ARB_MISC0 */
 921                                 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */
 922                         >;
 923                 };
 924                 timing-102000000 {
 925                         clock-frequency = <102000000>;
 926                         nvidia,emem-configuration = <
 927                                 0x00000003 /* MC_EMEM_ARB_CFG */
 928                                 0xc0000018 /* MC_EMEM_ARB_OUTSTANDING_REQ */
 929                                 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */
 930                                 0x00000001 /* MC_EMEM_ARB_TIMING_RP */
 931                                 0x00000003 /* MC_EMEM_ARB_TIMING_RC */
 932                                 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */
 933                                 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */
 934                                 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */
 935                                 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */
 936                                 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */
 937                                 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */
 938                                 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */
 939                                 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */
 940                                 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */
 941                                 0x06020102 /* MC_EMEM_ARB_DA_TURNS */
 942                                 0x000a0503 /* MC_EMEM_ARB_DA_COVERS */
 943                                 0x74430504 /* MC_EMEM_ARB_MISC0 */
 944                                 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */
 945                         >;
 946                 };
 947                 timing-204000000 {
 948                         clock-frequency = <204000000>;
 949                         nvidia,emem-configuration = <
 950                                 0x00000006 /* MC_EMEM_ARB_CFG */
 951                                 0xc0000025 /* MC_EMEM_ARB_OUTSTANDING_REQ */
 952                                 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */
 953                                 0x00000001 /* MC_EMEM_ARB_TIMING_RP */
 954                                 0x00000005 /* MC_EMEM_ARB_TIMING_RC */
 955                                 0x00000002 /* MC_EMEM_ARB_TIMING_RAS */
 956                                 0x00000004 /* MC_EMEM_ARB_TIMING_FAW */
 957                                 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */
 958                                 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */
 959                                 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */
 960                                 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */
 961                                 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */
 962                                 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */
 963                                 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */
 964                                 0x06020102 /* MC_EMEM_ARB_DA_TURNS */
 965                                 0x000a0505 /* MC_EMEM_ARB_DA_COVERS */
 966                                 0x74040a06 /* MC_EMEM_ARB_MISC0 */
 967                                 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */
 968                         >;
 969                 };
 970                 timing-400000000 {
 971                         clock-frequency = <400000000>;
 972                         nvidia,emem-configuration = <
 973                                 0x0000000c /* MC_EMEM_ARB_CFG */
 974                                 0xc0000048 /* MC_EMEM_ARB_OUTSTANDING_REQ */
 975                                 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */
 976                                 0x00000002 /* MC_EMEM_ARB_TIMING_RP */
 977                                 0x00000009 /* MC_EMEM_ARB_TIMING_RC */
 978                                 0x00000005 /* MC_EMEM_ARB_TIMING_RAS */
 979                                 0x00000007 /* MC_EMEM_ARB_TIMING_FAW */
 980                                 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */
 981                                 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */
 982                                 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */
 983                                 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */
 984                                 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */
 985                                 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */
 986                                 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */
 987                                 0x06030202 /* MC_EMEM_ARB_DA_TURNS */
 988                                 0x000d0709 /* MC_EMEM_ARB_DA_COVERS */
 989                                 0x7086120a /* MC_EMEM_ARB_MISC0 */
 990                                 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */
 991                         >;
 992                 };
 993                 timing-800000000 {
 994                         clock-frequency = <800000000>;
 995                         nvidia,emem-configuration = <
 996                                 0x00000018 /* MC_EMEM_ARB_CFG */
 997                                 0xc0000090 /* MC_EMEM_ARB_OUTSTANDING_REQ */
 998                                 0x00000004 /* MC_EMEM_ARB_TIMING_RCD */
 999                                 0x00000005 /* MC_EMEM_ARB_TIMING_RP */
1000                                 0x00000013 /* MC_EMEM_ARB_TIMING_RC */
1001                                 0x0000000c /* MC_EMEM_ARB_TIMING_RAS */
1002                                 0x0000000f /* MC_EMEM_ARB_TIMING_FAW */
1003                                 0x00000002 /* MC_EMEM_ARB_TIMING_RRD */
1004                                 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */
1005                                 0x0000000c /* MC_EMEM_ARB_TIMING_WAP2PRE */
1006                                 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */
1007                                 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */
1008                                 0x00000004 /* MC_EMEM_ARB_TIMING_R2W */
1009                                 0x00000008 /* MC_EMEM_ARB_TIMING_W2R */
1010                                 0x08040202 /* MC_EMEM_ARB_DA_TURNS */
1011                                 0x00160d13 /* MC_EMEM_ARB_DA_COVERS */
1012                                 0x712c2414 /* MC_EMEM_ARB_MISC0 */
1013                                 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */
1014                         >;
1015                 };
1016         };
1017 };
1018 &emc_timings {
1019         emc-timings-0 {
1020                 nvidia,ram-code = <0>;  /* Samsung RAM */
1021                 timing-25500000 {
1022                         clock-frequency = <25500000>;
1023                         nvidia,emc-auto-cal-interval = <0x001fffff>;
1024                         nvidia,emc-mode-1 = <0x80100003>;
1025                         nvidia,emc-mode-2 = <0x80200008>;
1026                         nvidia,emc-mode-reset = <0x80001221>;
1027                         nvidia,emc-zcal-cnt-long = <0x00000040>;
1028                         nvidia,emc-cfg-periodic-qrst;
1029                         nvidia,emc-cfg-dyn-self-ref;
1030                         nvidia,emc-configuration = <
1031                                 0x00000001 /* EMC_RC */
1032                                 0x00000006 /* EMC_RFC */
1033                                 0x00000000 /* EMC_RAS */
1034                                 0x00000000 /* EMC_RP */
1035                                 0x00000002 /* EMC_R2W */
1036                                 0x0000000a /* EMC_W2R */
1037                                 0x00000005 /* EMC_R2P */
1038                                 0x0000000b /* EMC_W2P */
1039                                 0x00000000 /* EMC_RD_RCD */
1040                                 0x00000000 /* EMC_WR_RCD */
1041                                 0x00000003 /* EMC_RRD */
1042                                 0x00000001 /* EMC_REXT */
1043                                 0x00000000 /* EMC_WEXT */
1044                                 0x00000005 /* EMC_WDV */
1045                                 0x00000005 /* EMC_QUSE */
1046                                 0x00000004 /* EMC_QRST */
1047                                 0x0000000a /* EMC_QSAFE */
1048                                 0x0000000b /* EMC_RDV */
1049                                 0x000000c0 /* EMC_REFRESH */
1050                                 0x00000000 /* EMC_BURST_REFRESH_NUM */
1051                                 0x00000030 /* EMC_PRE_REFRESH_REQ_CNT */
1052                                 0x00000002 /* EMC_PDEX2WR */
1053                                 0x00000002 /* EMC_PDEX2RD */
1054                                 0x00000001 /* EMC_PCHG2PDEN */
1055                                 0x00000000 /* EMC_ACT2PDEN */
1056                                 0x00000007 /* EMC_AR2PDEN */
1057                                 0x0000000f /* EMC_RW2PDEN */
1058                                 0x00000007 /* EMC_TXSR */
1059                                 0x00000007 /* EMC_TXSRDLL */
1060                                 0x00000004 /* EMC_TCKE */
1061                                 0x00000002 /* EMC_TFAW */
1062                                 0x00000000 /* EMC_TRPAB */
1063                                 0x00000004 /* EMC_TCLKSTABLE */
1064                                 0x00000005 /* EMC_TCLKSTOP */
1065                                 0x000000c7 /* EMC_TREFBW */
1066                                 0x00000006 /* EMC_QUSE_EXTRA */
1067                                 0x00000004 /* EMC_FBIO_CFG6 */
1068                                 0x00000000 /* EMC_ODT_WRITE */
1069                                 0x00000000 /* EMC_ODT_READ */
1070                                 0x00004288 /* EMC_FBIO_CFG5 */
1071                                 0x007800a4 /* EMC_CFG_DIG_DLL */
1072                                 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */
1073                                 0x000fc000 /* EMC_DLL_XFORM_DQS0 */
1074                                 0x000fc000 /* EMC_DLL_XFORM_DQS1 */
1075                                 0x000fc000 /* EMC_DLL_XFORM_DQS2 */
1076                                 0x000fc000 /* EMC_DLL_XFORM_DQS3 */
1077                                 0x000fc000 /* EMC_DLL_XFORM_DQS4 */
1078                                 0x000fc000 /* EMC_DLL_XFORM_DQS5 */
1079                                 0x000fc000 /* EMC_DLL_XFORM_DQS6 */
1080                                 0x000fc000 /* EMC_DLL_XFORM_DQS7 */
1081                                 0x00000000 /* EMC_DLL_XFORM_QUSE0 */
1082                                 0x00000000 /* EMC_DLL_XFORM_QUSE1 */
1083                                 0x00000000 /* EMC_DLL_XFORM_QUSE2 */
1084                                 0x00000000 /* EMC_DLL_XFORM_QUSE3 */
1085                                 0x00000000 /* EMC_DLL_XFORM_QUSE4 */
1086                                 0x00000000 /* EMC_DLL_XFORM_QUSE5 */
1087                                 0x00000000 /* EMC_DLL_XFORM_QUSE6 */
1088                                 0x00000000 /* EMC_DLL_XFORM_QUSE7 */
1089                                 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */
1090                                 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */
1091                                 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */
1092                                 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */
1093                                 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */
1094                                 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */
1095                                 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */
1096                                 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */
1097                                 0x000fc000 /* EMC_DLL_XFORM_DQ0 */
1098                                 0x000fc000 /* EMC_DLL_XFORM_DQ1 */
1099                                 0x000fc000 /* EMC_DLL_XFORM_DQ2 */
1100                                 0x000fc000 /* EMC_DLL_XFORM_DQ3 */
1101                                 0x000002a0 /* EMC_XM2CMDPADCTRL */
1102                                 0x0800211c /* EMC_XM2DQSPADCTRL2 */
1103                                 0x00000000 /* EMC_XM2DQPADCTRL2 */
1104                                 0x77fff884 /* EMC_XM2CLKPADCTRL */
1105                                 0x01f1f108 /* EMC_XM2COMPPADCTRL */
1106                                 0x05057404 /* EMC_XM2VTTGENPADCTRL */
1107                                 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */
1108                                 0x08000168 /* EMC_XM2QUSEPADCTRL */
1109                                 0x08000000 /* EMC_XM2DQSPADCTRL3 */
1110                                 0x00000802 /* EMC_CTT_TERM_CTRL */
1111                                 0x00000000 /* EMC_ZCAL_INTERVAL */
1112                                 0x00000040 /* EMC_ZCAL_WAIT_CNT */
1113                                 0x000c000c /* EMC_MRS_WAIT_CNT */
1114                                 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */
1115                                 0x00000000 /* EMC_CTT */
1116                                 0x00000000 /* EMC_CTT_DURATION */
1117                                 0x80000287 /* EMC_DYN_SELF_REF_CONTROL */
1118                                 0xe8000000 /* EMC_FBIO_SPARE */
1119                                 0xff00ff00 /* EMC_CFG_RSV */
1120                         >;
1121                 };
1122                 timing-51000000 {
1123                         clock-frequency = <51000000>;
1124                         nvidia,emc-auto-cal-interval = <0x001fffff>;
1125                         nvidia,emc-mode-1 = <0x80100003>;
1126                         nvidia,emc-mode-2 = <0x80200008>;
1127                         nvidia,emc-mode-reset = <0x80001221>;
1128                         nvidia,emc-zcal-cnt-long = <0x00000040>;
1129                         nvidia,emc-cfg-periodic-qrst;
1130                         nvidia,emc-cfg-dyn-self-ref;
1131                         nvidia,emc-configuration = <
1132                                 0x00000002 /* EMC_RC */
1133                                 0x0000000d /* EMC_RFC */
1134                                 0x00000001 /* EMC_RAS */
1135                                 0x00000000 /* EMC_RP */
1136                                 0x00000002 /* EMC_R2W */
1137                                 0x0000000a /* EMC_W2R */
1138                                 0x00000005 /* EMC_R2P */
1139                                 0x0000000b /* EMC_W2P */
1140                                 0x00000000 /* EMC_RD_RCD */
1141                                 0x00000000 /* EMC_WR_RCD */
1142                                 0x00000003 /* EMC_RRD */
1143                                 0x00000001 /* EMC_REXT */
1144                                 0x00000000 /* EMC_WEXT */
1145                                 0x00000005 /* EMC_WDV */
1146                                 0x00000005 /* EMC_QUSE */
1147                                 0x00000004 /* EMC_QRST */
1148                                 0x0000000a /* EMC_QSAFE */
1149                                 0x0000000b /* EMC_RDV */
1150                                 0x00000181 /* EMC_REFRESH */
1151                                 0x00000000 /* EMC_BURST_REFRESH_NUM */
1152                                 0x00000060 /* EMC_PRE_REFRESH_REQ_CNT */
1153                                 0x00000002 /* EMC_PDEX2WR */
1154                                 0x00000002 /* EMC_PDEX2RD */
1155                                 0x00000001 /* EMC_PCHG2PDEN */
1156                                 0x00000000 /* EMC_ACT2PDEN */
1157                                 0x00000007 /* EMC_AR2PDEN */
1158                                 0x0000000f /* EMC_RW2PDEN */
1159                                 0x0000000e /* EMC_TXSR */
1160                                 0x0000000e /* EMC_TXSRDLL */
1161                                 0x00000004 /* EMC_TCKE */
1162                                 0x00000003 /* EMC_TFAW */
1163                                 0x00000000 /* EMC_TRPAB */
1164                                 0x00000004 /* EMC_TCLKSTABLE */
1165                                 0x00000005 /* EMC_TCLKSTOP */
1166                                 0x0000018e /* EMC_TREFBW */
1167                                 0x00000006 /* EMC_QUSE_EXTRA */
1168                                 0x00000004 /* EMC_FBIO_CFG6 */
1169                                 0x00000000 /* EMC_ODT_WRITE */
1170                                 0x00000000 /* EMC_ODT_READ */
1171                                 0x00004288 /* EMC_FBIO_CFG5 */
1172                                 0x007800a4 /* EMC_CFG_DIG_DLL */
1173                                 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */
1174                                 0x000fc000 /* EMC_DLL_XFORM_DQS0 */
1175                                 0x000fc000 /* EMC_DLL_XFORM_DQS1 */
1176                                 0x000fc000 /* EMC_DLL_XFORM_DQS2 */
1177                                 0x000fc000 /* EMC_DLL_XFORM_DQS3 */
1178                                 0x000fc000 /* EMC_DLL_XFORM_DQS4 */
1179                                 0x000fc000 /* EMC_DLL_XFORM_DQS5 */
1180                                 0x000fc000 /* EMC_DLL_XFORM_DQS6 */
1181                                 0x000fc000 /* EMC_DLL_XFORM_DQS7 */
1182                                 0x00000000 /* EMC_DLL_XFORM_QUSE0 */
1183                                 0x00000000 /* EMC_DLL_XFORM_QUSE1 */
1184                                 0x00000000 /* EMC_DLL_XFORM_QUSE2 */
1185                                 0x00000000 /* EMC_DLL_XFORM_QUSE3 */
1186                                 0x00000000 /* EMC_DLL_XFORM_QUSE4 */
1187                                 0x00000000 /* EMC_DLL_XFORM_QUSE5 */
1188                                 0x00000000 /* EMC_DLL_XFORM_QUSE6 */
1189                                 0x00000000 /* EMC_DLL_XFORM_QUSE7 */
1190                                 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */
1191                                 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */
1192                                 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */
1193                                 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */
1194                                 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */
1195                                 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */
1196                                 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */
1197                                 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */
1198                                 0x000fc000 /* EMC_DLL_XFORM_DQ0 */
1199                                 0x000fc000 /* EMC_DLL_XFORM_DQ1 */
1200                                 0x000fc000 /* EMC_DLL_XFORM_DQ2 */
1201                                 0x000fc000 /* EMC_DLL_XFORM_DQ3 */
1202                                 0x000002a0 /* EMC_XM2CMDPADCTRL */
1203                                 0x0800211c /* EMC_XM2DQSPADCTRL2 */
1204                                 0x00000000 /* EMC_XM2DQPADCTRL2 */
1205                                 0x77fff884 /* EMC_XM2CLKPADCTRL */
1206                                 0x01f1f108 /* EMC_XM2COMPPADCTRL */
1207                                 0x05057404 /* EMC_XM2VTTGENPADCTRL */
1208                                 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */
1209                                 0x08000168 /* EMC_XM2QUSEPADCTRL */
1210                                 0x08000000 /* EMC_XM2DQSPADCTRL3 */
1211                                 0x00000802 /* EMC_CTT_TERM_CTRL */
1212                                 0x00000000 /* EMC_ZCAL_INTERVAL */
1213                                 0x00000040 /* EMC_ZCAL_WAIT_CNT */
1214                                 0x000c000c /* EMC_MRS_WAIT_CNT */
1215                                 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */
1216                                 0x00000000 /* EMC_CTT */
1217                                 0x00000000 /* EMC_CTT_DURATION */
1218                                 0x8000040b /* EMC_DYN_SELF_REF_CONTROL */
1219                                 0xe8000000 /* EMC_FBIO_SPARE */
1220                                 0xff00ff00 /* EMC_CFG_RSV */
1221                         >;
1222                 };
1223                 timing-102000000 {
1224                         clock-frequency = <102000000>;
1225                         nvidia,emc-auto-cal-interval = <0x001fffff>;
1226                         nvidia,emc-mode-1 = <0x80100003>;
1227                         nvidia,emc-mode-2 = <0x80200008>;
1228                         nvidia,emc-mode-reset = <0x80001221>;
1229                         nvidia,emc-zcal-cnt-long = <0x00000040>;
1230                         nvidia,emc-cfg-periodic-qrst;
1231                         nvidia,emc-cfg-dyn-self-ref;
1232                         nvidia,emc-configuration = <
1233                                 0x00000004 /* EMC_RC */
1234                                 0x0000001a /* EMC_RFC */
1235                                 0x00000003 /* EMC_RAS */
1236                                 0x00000001 /* EMC_RP */
1237                                 0x00000002 /* EMC_R2W */
1238                                 0x0000000a /* EMC_W2R */
1239                                 0x00000005 /* EMC_R2P */
1240                                 0x0000000b /* EMC_W2P */
1241                                 0x00000001 /* EMC_RD_RCD */
1242                                 0x00000001 /* EMC_WR_RCD */
1243                                 0x00000003 /* EMC_RRD */
1244                                 0x00000001 /* EMC_REXT */
1245                                 0x00000000 /* EMC_WEXT */
1246                                 0x00000005 /* EMC_WDV */
1247                                 0x00000005 /* EMC_QUSE */
1248                                 0x00000004 /* EMC_QRST */
1249                                 0x0000000a /* EMC_QSAFE */
1250                                 0x0000000b /* EMC_RDV */
1251                                 0x00000303 /* EMC_REFRESH */
1252                                 0x00000000 /* EMC_BURST_REFRESH_NUM */
1253                                 0x000000c0 /* EMC_PRE_REFRESH_REQ_CNT */
1254                                 0x00000002 /* EMC_PDEX2WR */
1255                                 0x00000002 /* EMC_PDEX2RD */
1256                                 0x00000001 /* EMC_PCHG2PDEN */
1257                                 0x00000000 /* EMC_ACT2PDEN */
1258                                 0x00000007 /* EMC_AR2PDEN */
1259                                 0x0000000f /* EMC_RW2PDEN */
1260                                 0x0000001c /* EMC_TXSR */
1261                                 0x0000001c /* EMC_TXSRDLL */
1262                                 0x00000004 /* EMC_TCKE */
1263                                 0x00000005 /* EMC_TFAW */
1264                                 0x00000000 /* EMC_TRPAB */
1265                                 0x00000004 /* EMC_TCLKSTABLE */
1266                                 0x00000005 /* EMC_TCLKSTOP */
1267                                 0x0000031c /* EMC_TREFBW */
1268                                 0x00000006 /* EMC_QUSE_EXTRA */
1269                                 0x00000004 /* EMC_FBIO_CFG6 */
1270                                 0x00000000 /* EMC_ODT_WRITE */
1271                                 0x00000000 /* EMC_ODT_READ */
1272                                 0x00004288 /* EMC_FBIO_CFG5 */
1273                                 0x007800a4 /* EMC_CFG_DIG_DLL */
1274                                 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */
1275                                 0x000fc000 /* EMC_DLL_XFORM_DQS0 */
1276                                 0x000fc000 /* EMC_DLL_XFORM_DQS1 */
1277                                 0x000fc000 /* EMC_DLL_XFORM_DQS2 */
1278                                 0x000fc000 /* EMC_DLL_XFORM_DQS3 */
1279                                 0x000fc000 /* EMC_DLL_XFORM_DQS4 */
1280                                 0x000fc000 /* EMC_DLL_XFORM_DQS5 */
1281                                 0x000fc000 /* EMC_DLL_XFORM_DQS6 */
1282                                 0x000fc000 /* EMC_DLL_XFORM_DQS7 */
1283                                 0x00000000 /* EMC_DLL_XFORM_QUSE0 */
1284                                 0x00000000 /* EMC_DLL_XFORM_QUSE1 */
1285                                 0x00000000 /* EMC_DLL_XFORM_QUSE2 */
1286                                 0x00000000 /* EMC_DLL_XFORM_QUSE3 */
1287                                 0x00000000 /* EMC_DLL_XFORM_QUSE4 */
1288                                 0x00000000 /* EMC_DLL_XFORM_QUSE5 */
1289                                 0x00000000 /* EMC_DLL_XFORM_QUSE6 */
1290                                 0x00000000 /* EMC_DLL_XFORM_QUSE7 */
1291                                 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */
1292                                 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */
1293                                 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */
1294                                 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */
1295                                 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */
1296                                 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */
1297                                 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */
1298                                 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */
1299                                 0x000fc000 /* EMC_DLL_XFORM_DQ0 */
1300                                 0x000fc000 /* EMC_DLL_XFORM_DQ1 */
1301                                 0x000fc000 /* EMC_DLL_XFORM_DQ2 */
1302                                 0x000fc000 /* EMC_DLL_XFORM_DQ3 */
1303                                 0x000002a0 /* EMC_XM2CMDPADCTRL */
1304                                 0x0800211c /* EMC_XM2DQSPADCTRL2 */
1305                                 0x00000000 /* EMC_XM2DQPADCTRL2 */
1306                                 0x77fff884 /* EMC_XM2CLKPADCTRL */
1307                                 0x01f1f108 /* EMC_XM2COMPPADCTRL */
1308                                 0x05057404 /* EMC_XM2VTTGENPADCTRL */
1309                                 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */
1310                                 0x08000168 /* EMC_XM2QUSEPADCTRL */
1311                                 0x08000000 /* EMC_XM2DQSPADCTRL3 */
1312                                 0x00000802 /* EMC_CTT_TERM_CTRL */
1313                                 0x00000000 /* EMC_ZCAL_INTERVAL */
1314                                 0x00000040 /* EMC_ZCAL_WAIT_CNT */
1315                                 0x000c000c /* EMC_MRS_WAIT_CNT */
1316                                 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */
1317                                 0x00000000 /* EMC_CTT */
1318                                 0x00000000 /* EMC_CTT_DURATION */
1319                                 0x80000713 /* EMC_DYN_SELF_REF_CONTROL */
1320                                 0xe8000000 /* EMC_FBIO_SPARE */
1321                                 0xff00ff00 /* EMC_CFG_RSV */
1322                         >;
1323                 };
1324                 timing-204000000 {
1325                         clock-frequency = <204000000>;
1326                         nvidia,emc-auto-cal-interval = <0x001fffff>;
1327                         nvidia,emc-mode-1 = <0x80100003>;
1328                         nvidia,emc-mode-2 = <0x80200008>;
1329                         nvidia,emc-mode-reset = <0x80001221>;
1330                         nvidia,emc-zcal-cnt-long = <0x00000040>;
1331                         nvidia,emc-cfg-periodic-qrst;
1332                         nvidia,emc-cfg-dyn-self-ref;
1333                         nvidia,emc-configuration = <
1334                                 0x00000009 /* EMC_RC */
1335                                 0x00000035 /* EMC_RFC */
1336                                 0x00000007 /* EMC_RAS */
1337                                 0x00000002 /* EMC_RP */
1338                                 0x00000002 /* EMC_R2W */
1339                                 0x0000000a /* EMC_W2R */
1340                                 0x00000005 /* EMC_R2P */
1341                                 0x0000000b /* EMC_W2P */
1342                                 0x00000002 /* EMC_RD_RCD */
1343                                 0x00000002 /* EMC_WR_RCD */
1344                                 0x00000003 /* EMC_RRD */
1345                                 0x00000001 /* EMC_REXT */
1346                                 0x00000000 /* EMC_WEXT */
1347                                 0x00000005 /* EMC_WDV */
1348                                 0x00000005 /* EMC_QUSE */
1349                                 0x00000004 /* EMC_QRST */
1350                                 0x0000000a /* EMC_QSAFE */
1351                                 0x0000000b /* EMC_RDV */
1352                                 0x00000607 /* EMC_REFRESH */
1353                                 0x00000000 /* EMC_BURST_REFRESH_NUM */
1354                                 0x00000181 /* EMC_PRE_REFRESH_REQ_CNT */
1355                                 0x00000002 /* EMC_PDEX2WR */
1356                                 0x00000002 /* EMC_PDEX2RD */
1357                                 0x00000001 /* EMC_PCHG2PDEN */
1358                                 0x00000000 /* EMC_ACT2PDEN */
1359                                 0x00000007 /* EMC_AR2PDEN */
1360                                 0x0000000f /* EMC_RW2PDEN */
1361                                 0x00000038 /* EMC_TXSR */
1362                                 0x00000038 /* EMC_TXSRDLL */
1363                                 0x00000004 /* EMC_TCKE */
1364                                 0x00000009 /* EMC_TFAW */
1365                                 0x00000000 /* EMC_TRPAB */
1366                                 0x00000004 /* EMC_TCLKSTABLE */
1367                                 0x00000005 /* EMC_TCLKSTOP */
1368                                 0x00000638 /* EMC_TREFBW */
1369                                 0x00000006 /* EMC_QUSE_EXTRA */
1370                                 0x00000006 /* EMC_FBIO_CFG6 */
1371                                 0x00000000 /* EMC_ODT_WRITE */
1372                                 0x00000000 /* EMC_ODT_READ */
1373                                 0x00004288 /* EMC_FBIO_CFG5 */
1374                                 0x004400a4 /* EMC_CFG_DIG_DLL */
1375                                 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */
1376                                 0x00080000 /* EMC_DLL_XFORM_DQS0 */
1377                                 0x00080000 /* EMC_DLL_XFORM_DQS1 */
1378                                 0x00080000 /* EMC_DLL_XFORM_DQS2 */
1379                                 0x00080000 /* EMC_DLL_XFORM_DQS3 */
1380                                 0x00080000 /* EMC_DLL_XFORM_DQS4 */
1381                                 0x00080000 /* EMC_DLL_XFORM_DQS5 */
1382                                 0x00080000 /* EMC_DLL_XFORM_DQS6 */
1383                                 0x00080000 /* EMC_DLL_XFORM_DQS7 */
1384                                 0x00000000 /* EMC_DLL_XFORM_QUSE0 */
1385                                 0x00000000 /* EMC_DLL_XFORM_QUSE1 */
1386                                 0x00000000 /* EMC_DLL_XFORM_QUSE2 */
1387                                 0x00000000 /* EMC_DLL_XFORM_QUSE3 */
1388                                 0x00000000 /* EMC_DLL_XFORM_QUSE4 */
1389                                 0x00000000 /* EMC_DLL_XFORM_QUSE5 */
1390                                 0x00000000 /* EMC_DLL_XFORM_QUSE6 */
1391                                 0x00000000 /* EMC_DLL_XFORM_QUSE7 */
1392                                 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */
1393                                 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */
1394                                 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */
1395                                 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */
1396                                 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */
1397                                 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */
1398                                 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */
1399                                 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */
1400                                 0x00080000 /* EMC_DLL_XFORM_DQ0 */
1401                                 0x00080000 /* EMC_DLL_XFORM_DQ1 */
1402                                 0x00080000 /* EMC_DLL_XFORM_DQ2 */
1403                                 0x00080000 /* EMC_DLL_XFORM_DQ3 */
1404                                 0x000002a0 /* EMC_XM2CMDPADCTRL */
1405                                 0x0800211c /* EMC_XM2DQSPADCTRL2 */
1406                                 0x00000000 /* EMC_XM2DQPADCTRL2 */
1407                                 0x77fff884 /* EMC_XM2CLKPADCTRL */
1408                                 0x01f1f108 /* EMC_XM2COMPPADCTRL */
1409                                 0x05057404 /* EMC_XM2VTTGENPADCTRL */
1410                                 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */
1411                                 0x08000168 /* EMC_XM2QUSEPADCTRL */
1412                                 0x08000000 /* EMC_XM2DQSPADCTRL3 */
1413                                 0x00000802 /* EMC_CTT_TERM_CTRL */
1414                                 0x00020000 /* EMC_ZCAL_INTERVAL */
1415                                 0x00000100 /* EMC_ZCAL_WAIT_CNT */
1416                                 0x000c000c /* EMC_MRS_WAIT_CNT */
1417                                 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */
1418                                 0x00000000 /* EMC_CTT */
1419                                 0x00000000 /* EMC_CTT_DURATION */
1420                                 0x80000d22 /* EMC_DYN_SELF_REF_CONTROL */
1421                                 0xe8000000 /* EMC_FBIO_SPARE */
1422                                 0xff00ff00 /* EMC_CFG_RSV */
1423                         >;
1424                 };
1425                 timing-400000000 {
1426                         clock-frequency = <400000000>;
1427                         nvidia,emc-auto-cal-interval = <0x001fffff>;
1428                         nvidia,emc-mode-1 = <0x80100002>;
1429                         nvidia,emc-mode-2 = <0x80200000>;
1430                         nvidia,emc-mode-reset = <0x80000521>;
1431                         nvidia,emc-zcal-cnt-long = <0x00000040>;
1432                         nvidia,emc-configuration = <
1433                                 0x00000012 /* EMC_RC */
1434                                 0x00000066 /* EMC_RFC */
1435                                 0x0000000c /* EMC_RAS */
1436                                 0x00000004 /* EMC_RP */
1437                                 0x00000003 /* EMC_R2W */
1438                                 0x00000008 /* EMC_W2R */
1439                                 0x00000002 /* EMC_R2P */
1440                                 0x0000000a /* EMC_W2P */
1441                                 0x00000004 /* EMC_RD_RCD */
1442                                 0x00000004 /* EMC_WR_RCD */
1443                                 0x00000002 /* EMC_RRD */
1444                                 0x00000001 /* EMC_REXT */
1445                                 0x00000000 /* EMC_WEXT */
1446                                 0x00000004 /* EMC_WDV */
1447                                 0x00000006 /* EMC_QUSE */
1448                                 0x00000004 /* EMC_QRST */
1449                                 0x0000000a /* EMC_QSAFE */
1450                                 0x0000000c /* EMC_RDV */
1451                                 0x00000bf0 /* EMC_REFRESH */
1452                                 0x00000000 /* EMC_BURST_REFRESH_NUM */
1453                                 0x000002fc /* EMC_PRE_REFRESH_REQ_CNT */
1454                                 0x00000001 /* EMC_PDEX2WR */
1455                                 0x00000008 /* EMC_PDEX2RD */
1456                                 0x00000001 /* EMC_PCHG2PDEN */
1457                                 0x00000000 /* EMC_ACT2PDEN */
1458                                 0x00000008 /* EMC_AR2PDEN */
1459                                 0x0000000f /* EMC_RW2PDEN */
1460                                 0x0000006c /* EMC_TXSR */
1461                                 0x00000200 /* EMC_TXSRDLL */
1462                                 0x00000004 /* EMC_TCKE */
1463                                 0x00000010 /* EMC_TFAW */
1464                                 0x00000000 /* EMC_TRPAB */
1465                                 0x00000004 /* EMC_TCLKSTABLE */
1466                                 0x00000005 /* EMC_TCLKSTOP */
1467                                 0x00000c30 /* EMC_TREFBW */
1468                                 0x00000000 /* EMC_QUSE_EXTRA */
1469                                 0x00000004 /* EMC_FBIO_CFG6 */
1470                                 0x00000000 /* EMC_ODT_WRITE */
1471                                 0x00000000 /* EMC_ODT_READ */
1472                                 0x00007088 /* EMC_FBIO_CFG5 */
1473                                 0x001d0084 /* EMC_CFG_DIG_DLL */
1474                                 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */
1475                                 0x0003c000 /* EMC_DLL_XFORM_DQS0 */
1476                                 0x0003c000 /* EMC_DLL_XFORM_DQS1 */
1477                                 0x0003c000 /* EMC_DLL_XFORM_DQS2 */
1478                                 0x0003c000 /* EMC_DLL_XFORM_DQS3 */
1479                                 0x0003c000 /* EMC_DLL_XFORM_DQS4 */
1480                                 0x0003c000 /* EMC_DLL_XFORM_DQS5 */
1481                                 0x0003c000 /* EMC_DLL_XFORM_DQS6 */
1482                                 0x0003c000 /* EMC_DLL_XFORM_DQS7 */
1483                                 0x00000000 /* EMC_DLL_XFORM_QUSE0 */
1484                                 0x00000000 /* EMC_DLL_XFORM_QUSE1 */
1485                                 0x00000000 /* EMC_DLL_XFORM_QUSE2 */
1486                                 0x00000000 /* EMC_DLL_XFORM_QUSE3 */
1487                                 0x00000000 /* EMC_DLL_XFORM_QUSE4 */
1488                                 0x00000000 /* EMC_DLL_XFORM_QUSE5 */
1489                                 0x00000000 /* EMC_DLL_XFORM_QUSE6 */
1490                                 0x00000000 /* EMC_DLL_XFORM_QUSE7 */
1491                                 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */
1492                                 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */
1493                                 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */
1494                                 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */
1495                                 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */
1496                                 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */
1497                                 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */
1498                                 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */
1499                                 0x00048000 /* EMC_DLL_XFORM_DQ0 */
1500                                 0x00048000 /* EMC_DLL_XFORM_DQ1 */
1501                                 0x00048000 /* EMC_DLL_XFORM_DQ2 */
1502                                 0x00048000 /* EMC_DLL_XFORM_DQ3 */
1503                                 0x000002a0 /* EMC_XM2CMDPADCTRL */
1504                                 0x0800013d /* EMC_XM2DQSPADCTRL2 */
1505                                 0x00000000 /* EMC_XM2DQPADCTRL2 */
1506                                 0x77fff884 /* EMC_XM2CLKPADCTRL */
1507                                 0x01f1f508 /* EMC_XM2COMPPADCTRL */
1508                                 0x05057404 /* EMC_XM2VTTGENPADCTRL */
1509                                 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */
1510                                 0x080001e8 /* EMC_XM2QUSEPADCTRL */
1511                                 0x08000021 /* EMC_XM2DQSPADCTRL3 */
1512                                 0x00000802 /* EMC_CTT_TERM_CTRL */
1513                                 0x00020000 /* EMC_ZCAL_INTERVAL */
1514                                 0x00000100 /* EMC_ZCAL_WAIT_CNT */
1515                                 0x0158000c /* EMC_MRS_WAIT_CNT */
1516                                 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */
1517                                 0x00000000 /* EMC_CTT */
1518                                 0x00000000 /* EMC_CTT_DURATION */
1519                                 0x800018c8 /* EMC_DYN_SELF_REF_CONTROL */
1520                                 0xe8000000 /* EMC_FBIO_SPARE */
1521                                 0xff00ff89 /* EMC_CFG_RSV */
1522                         >;
1523                 };
1524                 timing-800000000 {
1525                         clock-frequency = <800000000>;
1526                         nvidia,emc-auto-cal-interval = <0x001fffff>;
1527                         nvidia,emc-mode-1 = <0x80100002>;
1528                         nvidia,emc-mode-2 = <0x80200018>;
1529                         nvidia,emc-mode-reset = <0x80000d71>;
1530                         nvidia,emc-zcal-cnt-long = <0x00000040>;
1531                         nvidia,emc-cfg-periodic-qrst;
1532                         nvidia,emc-configuration = <
1533                                 0x00000025 /* EMC_RC */
1534                                 0x000000ce /* EMC_RFC */
1535                                 0x0000001a /* EMC_RAS */
1536                                 0x00000009 /* EMC_RP */
1537                                 0x00000005 /* EMC_R2W */
1538                                 0x0000000d /* EMC_W2R */
1539                                 0x00000004 /* EMC_R2P */
1540                                 0x00000013 /* EMC_W2P */
1541                                 0x00000009 /* EMC_RD_RCD */
1542                                 0x00000009 /* EMC_WR_RCD */
1543                                 0x00000004 /* EMC_RRD */
1544                                 0x00000001 /* EMC_REXT */
1545                                 0x00000000 /* EMC_WEXT */
1546                                 0x00000007 /* EMC_WDV */
1547                                 0x0000000a /* EMC_QUSE */
1548                                 0x00000009 /* EMC_QRST */
1549                                 0x0000000b /* EMC_QSAFE */
1550                                 0x00000011 /* EMC_RDV */
1551                                 0x00001820 /* EMC_REFRESH */
1552                                 0x00000000 /* EMC_BURST_REFRESH_NUM */
1553                                 0x00000608 /* EMC_PRE_REFRESH_REQ_CNT */
1554                                 0x00000003 /* EMC_PDEX2WR */
1555                                 0x00000012 /* EMC_PDEX2RD */
1556                                 0x00000001 /* EMC_PCHG2PDEN */
1557                                 0x00000000 /* EMC_ACT2PDEN */
1558                                 0x0000000f /* EMC_AR2PDEN */
1559                                 0x00000018 /* EMC_RW2PDEN */
1560                                 0x000000d8 /* EMC_TXSR */
1561                                 0x00000200 /* EMC_TXSRDLL */
1562                                 0x00000005 /* EMC_TCKE */
1563                                 0x00000020 /* EMC_TFAW */
1564                                 0x00000000 /* EMC_TRPAB */
1565                                 0x00000007 /* EMC_TCLKSTABLE */
1566                                 0x00000008 /* EMC_TCLKSTOP */
1567                                 0x00001860 /* EMC_TREFBW */
1568                                 0x0000000b /* EMC_QUSE_EXTRA */
1569                                 0x00000006 /* EMC_FBIO_CFG6 */
1570                                 0x00000000 /* EMC_ODT_WRITE */
1571                                 0x00000000 /* EMC_ODT_READ */
1572                                 0x00005088 /* EMC_FBIO_CFG5 */
1573                                 0xf0070191 /* EMC_CFG_DIG_DLL */
1574                                 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */
1575                                 0x0000800a /* EMC_DLL_XFORM_DQS0 */
1576                                 0x0000000a /* EMC_DLL_XFORM_DQS1 */
1577                                 0x0000000a /* EMC_DLL_XFORM_DQS2 */
1578                                 0x0000000a /* EMC_DLL_XFORM_DQS3 */
1579                                 0x0000000a /* EMC_DLL_XFORM_DQS4 */
1580                                 0x0000000a /* EMC_DLL_XFORM_DQS5 */
1581                                 0x0000000a /* EMC_DLL_XFORM_DQS6 */
1582                                 0x0000000a /* EMC_DLL_XFORM_DQS7 */
1583                                 0x00018000 /* EMC_DLL_XFORM_QUSE0 */
1584                                 0x00018000 /* EMC_DLL_XFORM_QUSE1 */
1585                                 0x00018000 /* EMC_DLL_XFORM_QUSE2 */
1586                                 0x00018000 /* EMC_DLL_XFORM_QUSE3 */
1587                                 0x00018000 /* EMC_DLL_XFORM_QUSE4 */
1588                                 0x00018000 /* EMC_DLL_XFORM_QUSE5 */
1589                                 0x00018000 /* EMC_DLL_XFORM_QUSE6 */
1590                                 0x00018000 /* EMC_DLL_XFORM_QUSE7 */
1591                                 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */
1592                                 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */
1593                                 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */
1594                                 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */
1595                                 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */
1596                                 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */
1597                                 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */
1598                                 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */
1599                                 0x0000000a /* EMC_DLL_XFORM_DQ0 */
1600                                 0x0000000a /* EMC_DLL_XFORM_DQ1 */
1601                                 0x0000000a /* EMC_DLL_XFORM_DQ2 */
1602                                 0x0000000a /* EMC_DLL_XFORM_DQ3 */
1603                                 0x000002a0 /* EMC_XM2CMDPADCTRL */
1604                                 0x0600013d /* EMC_XM2DQSPADCTRL2 */
1605                                 0x22220000 /* EMC_XM2DQPADCTRL2 */
1606                                 0x77fff884 /* EMC_XM2CLKPADCTRL */
1607                                 0x01f1f501 /* EMC_XM2COMPPADCTRL */
1608                                 0x07077404 /* EMC_XM2VTTGENPADCTRL */
1609                                 0x54000000 /* EMC_XM2VTTGENPADCTRL2 */
1610                                 0x080001e8 /* EMC_XM2QUSEPADCTRL */
1611                                 0x08000021 /* EMC_XM2DQSPADCTRL3 */
1612                                 0x00000802 /* EMC_CTT_TERM_CTRL */
1613                                 0x00020000 /* EMC_ZCAL_INTERVAL */
1614                                 0x00000100 /* EMC_ZCAL_WAIT_CNT */
1615                                 0x00f0000c /* EMC_MRS_WAIT_CNT */
1616                                 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */
1617                                 0x00000000 /* EMC_CTT */
1618                                 0x00000000 /* EMC_CTT_DURATION */
1619                                 0x8000308c /* EMC_DYN_SELF_REF_CONTROL */
1620                                 0xe8000000 /* EMC_FBIO_SPARE */
1621                                 0xff00ff49 /* EMC_CFG_RSV */
1622                         >;
1623                 };
1624         };
1625         emc-timings-1 {
1626                 nvidia,ram-code = <1>;  /* Hynix M RAM */
1627                 timing-25500000 {
1628                         clock-frequency = <25500000>;
1629                         nvidia,emc-auto-cal-interval = <0x001fffff>;
1630                         nvidia,emc-mode-1 = <0x80100003>;
1631                         nvidia,emc-mode-2 = <0x80200008>;
1632                         nvidia,emc-mode-reset = <0x80001221>;
1633                         nvidia,emc-zcal-cnt-long = <0x00000040>;
1634                         nvidia,emc-cfg-periodic-qrst;
1635                         nvidia,emc-cfg-dyn-self-ref;
1636                         nvidia,emc-configuration = <
1637                                 0x00000001 /* EMC_RC */
1638                                 0x00000006 /* EMC_RFC */
1639                                 0x00000000 /* EMC_RAS */
1640                                 0x00000000 /* EMC_RP */
1641                                 0x00000002 /* EMC_R2W */
1642                                 0x0000000a /* EMC_W2R */
1643                                 0x00000005 /* EMC_R2P */
1644                                 0x0000000b /* EMC_W2P */
1645                                 0x00000000 /* EMC_RD_RCD */
1646                                 0x00000000 /* EMC_WR_RCD */
1647                                 0x00000003 /* EMC_RRD */
1648                                 0x00000001 /* EMC_REXT */
1649                                 0x00000000 /* EMC_WEXT */
1650                                 0x00000005 /* EMC_WDV */
1651                                 0x00000005 /* EMC_QUSE */
1652                                 0x00000004 /* EMC_QRST */
1653                                 0x0000000a /* EMC_QSAFE */
1654                                 0x0000000b /* EMC_RDV */
1655                                 0x000000c0 /* EMC_REFRESH */
1656                                 0x00000000 /* EMC_BURST_REFRESH_NUM */
1657                                 0x00000030 /* EMC_PRE_REFRESH_REQ_CNT */
1658                                 0x00000002 /* EMC_PDEX2WR */
1659                                 0x00000002 /* EMC_PDEX2RD */
1660                                 0x00000001 /* EMC_PCHG2PDEN */
1661                                 0x00000000 /* EMC_ACT2PDEN */
1662                                 0x00000007 /* EMC_AR2PDEN */
1663                                 0x0000000f /* EMC_RW2PDEN */
1664                                 0x00000007 /* EMC_TXSR */
1665                                 0x00000007 /* EMC_TXSRDLL */
1666                                 0x00000004 /* EMC_TCKE */
1667                                 0x00000002 /* EMC_TFAW */
1668                                 0x00000000 /* EMC_TRPAB */
1669                                 0x00000004 /* EMC_TCLKSTABLE */
1670                                 0x00000005 /* EMC_TCLKSTOP */
1671                                 0x000000c7 /* EMC_TREFBW */
1672                                 0x00000006 /* EMC_QUSE_EXTRA */
1673                                 0x00000004 /* EMC_FBIO_CFG6 */
1674                                 0x00000000 /* EMC_ODT_WRITE */
1675                                 0x00000000 /* EMC_ODT_READ */
1676                                 0x00004288 /* EMC_FBIO_CFG5 */
1677                                 0x007800a4 /* EMC_CFG_DIG_DLL */
1678                                 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */
1679                                 0x000fc000 /* EMC_DLL_XFORM_DQS0 */
1680                                 0x000fc000 /* EMC_DLL_XFORM_DQS1 */
1681                                 0x000fc000 /* EMC_DLL_XFORM_DQS2 */
1682                                 0x000fc000 /* EMC_DLL_XFORM_DQS3 */
1683                                 0x000fc000 /* EMC_DLL_XFORM_DQS4 */
1684                                 0x000fc000 /* EMC_DLL_XFORM_DQS5 */
1685                                 0x000fc000 /* EMC_DLL_XFORM_DQS6 */
1686                                 0x000fc000 /* EMC_DLL_XFORM_DQS7 */
1687                                 0x00000000 /* EMC_DLL_XFORM_QUSE0 */
1688                                 0x00000000 /* EMC_DLL_XFORM_QUSE1 */
1689                                 0x00000000 /* EMC_DLL_XFORM_QUSE2 */
1690                                 0x00000000 /* EMC_DLL_XFORM_QUSE3 */
1691                                 0x00000000 /* EMC_DLL_XFORM_QUSE4 */
1692                                 0x00000000 /* EMC_DLL_XFORM_QUSE5 */
1693                                 0x00000000 /* EMC_DLL_XFORM_QUSE6 */
1694                                 0x00000000 /* EMC_DLL_XFORM_QUSE7 */
1695                                 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */
1696                                 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */
1697                                 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */
1698                                 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */
1699                                 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */
1700                                 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */
1701                                 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */
1702                                 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */
1703                                 0x000fc000 /* EMC_DLL_XFORM_DQ0 */
1704                                 0x000fc000 /* EMC_DLL_XFORM_DQ1 */
1705                                 0x000fc000 /* EMC_DLL_XFORM_DQ2 */
1706                                 0x000fc000 /* EMC_DLL_XFORM_DQ3 */
1707                                 0x000002a0 /* EMC_XM2CMDPADCTRL */
1708                                 0x0800211c /* EMC_XM2DQSPADCTRL2 */
1709                                 0x00000000 /* EMC_XM2DQPADCTRL2 */
1710                                 0x77fff884 /* EMC_XM2CLKPADCTRL */
1711                                 0x01f1f108 /* EMC_XM2COMPPADCTRL */
1712                                 0x05057404 /* EMC_XM2VTTGENPADCTRL */
1713                                 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */
1714                                 0x08000168 /* EMC_XM2QUSEPADCTRL */
1715                                 0x08000000 /* EMC_XM2DQSPADCTRL3 */
1716                                 0x00000802 /* EMC_CTT_TERM_CTRL */
1717                                 0x00000000 /* EMC_ZCAL_INTERVAL */
1718                                 0x00000040 /* EMC_ZCAL_WAIT_CNT */
1719                                 0x000c000c /* EMC_MRS_WAIT_CNT */
1720                                 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */
1721                                 0x00000000 /* EMC_CTT */
1722                                 0x00000000 /* EMC_CTT_DURATION */
1723                                 0x80000287 /* EMC_DYN_SELF_REF_CONTROL */
1724                                 0xe8000000 /* EMC_FBIO_SPARE */
1725                                 0xff00ff00 /* EMC_CFG_RSV */
1726                         >;
1727                 };
1728                 timing-51000000 {
1729                         clock-frequency = <51000000>;
1730                         nvidia,emc-auto-cal-interval = <0x001fffff>;
1731                         nvidia,emc-mode-1 = <0x80100003>;
1732                         nvidia,emc-mode-2 = <0x80200008>;
1733                         nvidia,emc-mode-reset = <0x80001221>;
1734                         nvidia,emc-zcal-cnt-long = <0x00000040>;
1735                         nvidia,emc-cfg-periodic-qrst;
1736                         nvidia,emc-cfg-dyn-self-ref;
1737                         nvidia,emc-configuration = <
1738                                 0x00000002 /* EMC_RC */
1739                                 0x0000000d /* EMC_RFC */
1740                                 0x00000001 /* EMC_RAS */
1741                                 0x00000000 /* EMC_RP */
1742                                 0x00000002 /* EMC_R2W */
1743                                 0x0000000a /* EMC_W2R */
1744                                 0x00000005 /* EMC_R2P */
1745                                 0x0000000b /* EMC_W2P */
1746                                 0x00000000 /* EMC_RD_RCD */
1747                                 0x00000000 /* EMC_WR_RCD */
1748                                 0x00000003 /* EMC_RRD */
1749                                 0x00000001 /* EMC_REXT */
1750                                 0x00000000 /* EMC_WEXT */
1751                                 0x00000005 /* EMC_WDV */
1752                                 0x00000005 /* EMC_QUSE */
1753                                 0x00000004 /* EMC_QRST */
1754                                 0x0000000a /* EMC_QSAFE */
1755                                 0x0000000b /* EMC_RDV */
1756                                 0x00000181 /* EMC_REFRESH */
1757                                 0x00000000 /* EMC_BURST_REFRESH_NUM */
1758                                 0x00000060 /* EMC_PRE_REFRESH_REQ_CNT */
1759                                 0x00000002 /* EMC_PDEX2WR */
1760                                 0x00000002 /* EMC_PDEX2RD */
1761                                 0x00000001 /* EMC_PCHG2PDEN */
1762                                 0x00000000 /* EMC_ACT2PDEN */
1763                                 0x00000007 /* EMC_AR2PDEN */
1764                                 0x0000000f /* EMC_RW2PDEN */
1765                                 0x0000000e /* EMC_TXSR */
1766                                 0x0000000e /* EMC_TXSRDLL */
1767                                 0x00000004 /* EMC_TCKE */
1768                                 0x00000003 /* EMC_TFAW */
1769                                 0x00000000 /* EMC_TRPAB */
1770                                 0x00000004 /* EMC_TCLKSTABLE */
1771                                 0x00000005 /* EMC_TCLKSTOP */
1772                                 0x0000018e /* EMC_TREFBW */
1773                                 0x00000006 /* EMC_QUSE_EXTRA */
1774                                 0x00000004 /* EMC_FBIO_CFG6 */
1775                                 0x00000000 /* EMC_ODT_WRITE */
1776                                 0x00000000 /* EMC_ODT_READ */
1777                                 0x00004288 /* EMC_FBIO_CFG5 */
1778                                 0x007800a4 /* EMC_CFG_DIG_DLL */
1779                                 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */
1780                                 0x000fc000 /* EMC_DLL_XFORM_DQS0 */
1781                                 0x000fc000 /* EMC_DLL_XFORM_DQS1 */
1782                                 0x000fc000 /* EMC_DLL_XFORM_DQS2 */
1783                                 0x000fc000 /* EMC_DLL_XFORM_DQS3 */
1784                                 0x000fc000 /* EMC_DLL_XFORM_DQS4 */
1785                                 0x000fc000 /* EMC_DLL_XFORM_DQS5 */
1786                                 0x000fc000 /* EMC_DLL_XFORM_DQS6 */
1787                                 0x000fc000 /* EMC_DLL_XFORM_DQS7 */
1788                                 0x00000000 /* EMC_DLL_XFORM_QUSE0 */
1789                                 0x00000000 /* EMC_DLL_XFORM_QUSE1 */
1790                                 0x00000000 /* EMC_DLL_XFORM_QUSE2 */
1791                                 0x00000000 /* EMC_DLL_XFORM_QUSE3 */
1792                                 0x00000000 /* EMC_DLL_XFORM_QUSE4 */
1793                                 0x00000000 /* EMC_DLL_XFORM_QUSE5 */
1794                                 0x00000000 /* EMC_DLL_XFORM_QUSE6 */
1795                                 0x00000000 /* EMC_DLL_XFORM_QUSE7 */
1796                                 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */
1797                                 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */
1798                                 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */
1799                                 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */
1800                                 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */
1801                                 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */
1802                                 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */
1803                                 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */
1804                                 0x000fc000 /* EMC_DLL_XFORM_DQ0 */
1805                                 0x000fc000 /* EMC_DLL_XFORM_DQ1 */
1806                                 0x000fc000 /* EMC_DLL_XFORM_DQ2 */
1807                                 0x000fc000 /* EMC_DLL_XFORM_DQ3 */
1808                                 0x000002a0 /* EMC_XM2CMDPADCTRL */
1809                                 0x0800211c /* EMC_XM2DQSPADCTRL2 */
1810                                 0x00000000 /* EMC_XM2DQPADCTRL2 */
1811                                 0x77fff884 /* EMC_XM2CLKPADCTRL */
1812                                 0x01f1f108 /* EMC_XM2COMPPADCTRL */
1813                                 0x05057404 /* EMC_XM2VTTGENPADCTRL */
1814                                 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */
1815                                 0x08000168 /* EMC_XM2QUSEPADCTRL */
1816                                 0x08000000 /* EMC_XM2DQSPADCTRL3 */
1817                                 0x00000802 /* EMC_CTT_TERM_CTRL */
1818                                 0x00000000 /* EMC_ZCAL_INTERVAL */
1819                                 0x00000040 /* EMC_ZCAL_WAIT_CNT */
1820                                 0x000c000c /* EMC_MRS_WAIT_CNT */
1821                                 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */
1822                                 0x00000000 /* EMC_CTT */
1823                                 0x00000000 /* EMC_CTT_DURATION */
1824                                 0x8000040b /* EMC_DYN_SELF_REF_CONTROL */
1825                                 0xe8000000 /* EMC_FBIO_SPARE */
1826                                 0xff00ff00 /* EMC_CFG_RSV */
1827                         >;
1828                 };
1829                 timing-102000000 {
1830                         clock-frequency = <102000000>;
1831                         nvidia,emc-auto-cal-interval = <0x001fffff>;
1832                         nvidia,emc-mode-1 = <0x80100003>;
1833                         nvidia,emc-mode-2 = <0x80200008>;
1834                         nvidia,emc-mode-reset = <0x80001221>;
1835                         nvidia,emc-zcal-cnt-long = <0x00000040>;
1836                         nvidia,emc-cfg-periodic-qrst;
1837                         nvidia,emc-cfg-dyn-self-ref;
1838                         nvidia,emc-configuration = <
1839                                 0x00000004 /* EMC_RC */
1840                                 0x0000001a /* EMC_RFC */
1841                                 0x00000003 /* EMC_RAS */
1842                                 0x00000001 /* EMC_RP */
1843                                 0x00000002 /* EMC_R2W */
1844                                 0x0000000a /* EMC_W2R */
1845                                 0x00000005 /* EMC_R2P */
1846                                 0x0000000b /* EMC_W2P */
1847                                 0x00000001 /* EMC_RD_RCD */
1848                                 0x00000001 /* EMC_WR_RCD */
1849                                 0x00000003 /* EMC_RRD */
1850                                 0x00000001 /* EMC_REXT */
1851                                 0x00000000 /* EMC_WEXT */
1852                                 0x00000005 /* EMC_WDV */
1853                                 0x00000005 /* EMC_QUSE */
1854                                 0x00000004 /* EMC_QRST */
1855                                 0x0000000a /* EMC_QSAFE */
1856                                 0x0000000b /* EMC_RDV */
1857                                 0x00000303 /* EMC_REFRESH */
1858                                 0x00000000 /* EMC_BURST_REFRESH_NUM */
1859                                 0x000000c0 /* EMC_PRE_REFRESH_REQ_CNT */
1860                                 0x00000002 /* EMC_PDEX2WR */
1861                                 0x00000002 /* EMC_PDEX2RD */
1862                                 0x00000001 /* EMC_PCHG2PDEN */
1863                                 0x00000000 /* EMC_ACT2PDEN */
1864                                 0x00000007 /* EMC_AR2PDEN */
1865                                 0x0000000f /* EMC_RW2PDEN */
1866                                 0x0000001c /* EMC_TXSR */
1867                                 0x0000001c /* EMC_TXSRDLL */
1868                                 0x00000004 /* EMC_TCKE */
1869                                 0x00000005 /* EMC_TFAW */
1870                                 0x00000000 /* EMC_TRPAB */
1871                                 0x00000004 /* EMC_TCLKSTABLE */
1872                                 0x00000005 /* EMC_TCLKSTOP */
1873                                 0x0000031c /* EMC_TREFBW */
1874                                 0x00000006 /* EMC_QUSE_EXTRA */
1875                                 0x00000004 /* EMC_FBIO_CFG6 */
1876                                 0x00000000 /* EMC_ODT_WRITE */
1877                                 0x00000000 /* EMC_ODT_READ */
1878                                 0x00004288 /* EMC_FBIO_CFG5 */
1879                                 0x007800a4 /* EMC_CFG_DIG_DLL */
1880                                 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */
1881                                 0x000fc000 /* EMC_DLL_XFORM_DQS0 */
1882                                 0x000fc000 /* EMC_DLL_XFORM_DQS1 */
1883                                 0x000fc000 /* EMC_DLL_XFORM_DQS2 */
1884                                 0x000fc000 /* EMC_DLL_XFORM_DQS3 */
1885                                 0x000fc000 /* EMC_DLL_XFORM_DQS4 */
1886                                 0x000fc000 /* EMC_DLL_XFORM_DQS5 */
1887                                 0x000fc000 /* EMC_DLL_XFORM_DQS6 */
1888                                 0x000fc000 /* EMC_DLL_XFORM_DQS7 */
1889                                 0x00000000 /* EMC_DLL_XFORM_QUSE0 */
1890                                 0x00000000 /* EMC_DLL_XFORM_QUSE1 */
1891                                 0x00000000 /* EMC_DLL_XFORM_QUSE2 */
1892                                 0x00000000 /* EMC_DLL_XFORM_QUSE3 */
1893                                 0x00000000 /* EMC_DLL_XFORM_QUSE4 */
1894                                 0x00000000 /* EMC_DLL_XFORM_QUSE5 */
1895                                 0x00000000 /* EMC_DLL_XFORM_QUSE6 */
1896                                 0x00000000 /* EMC_DLL_XFORM_QUSE7 */
1897                                 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */
1898                                 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */
1899                                 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */
1900                                 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */
1901                                 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */
1902                                 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */
1903                                 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */
1904                                 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */
1905                                 0x000fc000 /* EMC_DLL_XFORM_DQ0 */
1906                                 0x000fc000 /* EMC_DLL_XFORM_DQ1 */
1907                                 0x000fc000 /* EMC_DLL_XFORM_DQ2 */
1908                                 0x000fc000 /* EMC_DLL_XFORM_DQ3 */
1909                                 0x000002a0 /* EMC_XM2CMDPADCTRL */
1910                                 0x0800211c /* EMC_XM2DQSPADCTRL2 */
1911                                 0x00000000 /* EMC_XM2DQPADCTRL2 */
1912                                 0x77fff884 /* EMC_XM2CLKPADCTRL */
1913                                 0x01f1f108 /* EMC_XM2COMPPADCTRL */
1914                                 0x05057404 /* EMC_XM2VTTGENPADCTRL */
1915                                 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */
1916                                 0x08000168 /* EMC_XM2QUSEPADCTRL */
1917                                 0x08000000 /* EMC_XM2DQSPADCTRL3 */
1918                                 0x00000802 /* EMC_CTT_TERM_CTRL */
1919                                 0x00000000 /* EMC_ZCAL_INTERVAL */
1920                                 0x00000040 /* EMC_ZCAL_WAIT_CNT */
1921                                 0x000c000c /* EMC_MRS_WAIT_CNT */
1922                                 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */
1923                                 0x00000000 /* EMC_CTT */
1924                                 0x00000000 /* EMC_CTT_DURATION */
1925                                 0x80000713 /* EMC_DYN_SELF_REF_CONTROL */
1926                                 0xe8000000 /* EMC_FBIO_SPARE */
1927                                 0xff00ff00 /* EMC_CFG_RSV */
1928                         >;
1929                 };
1930                 timing-204000000 {
1931                         clock-frequency = <204000000>;
1932                         nvidia,emc-auto-cal-interval = <0x001fffff>;
1933                         nvidia,emc-mode-1 = <0x80100003>;
1934                         nvidia,emc-mode-2 = <0x80200008>;
1935                         nvidia,emc-mode-reset = <0x80001221>;
1936                         nvidia,emc-zcal-cnt-long = <0x00000040>;
1937                         nvidia,emc-cfg-periodic-qrst;
1938                         nvidia,emc-cfg-dyn-self-ref;
1939                         nvidia,emc-configuration = <
1940                                 0x00000009 /* EMC_RC */
1941                                 0x00000035 /* EMC_RFC */
1942                                 0x00000007 /* EMC_RAS */
1943                                 0x00000002 /* EMC_RP */
1944                                 0x00000002 /* EMC_R2W */
1945                                 0x0000000a /* EMC_W2R */
1946                                 0x00000005 /* EMC_R2P */
1947                                 0x0000000b /* EMC_W2P */
1948                                 0x00000002 /* EMC_RD_RCD */
1949                                 0x00000002 /* EMC_WR_RCD */
1950                                 0x00000003 /* EMC_RRD */
1951                                 0x00000001 /* EMC_REXT */
1952                                 0x00000000 /* EMC_WEXT */
1953                                 0x00000005 /* EMC_WDV */
1954                                 0x00000005 /* EMC_QUSE */
1955                                 0x00000004 /* EMC_QRST */
1956                                 0x0000000a /* EMC_QSAFE */
1957                                 0x0000000b /* EMC_RDV */
1958                                 0x00000607 /* EMC_REFRESH */
1959                                 0x00000000 /* EMC_BURST_REFRESH_NUM */
1960                                 0x00000181 /* EMC_PRE_REFRESH_REQ_CNT */
1961                                 0x00000002 /* EMC_PDEX2WR */
1962                                 0x00000002 /* EMC_PDEX2RD */
1963                                 0x00000001 /* EMC_PCHG2PDEN */
1964                                 0x00000000 /* EMC_ACT2PDEN */
1965                                 0x00000007 /* EMC_AR2PDEN */
1966                                 0x0000000f /* EMC_RW2PDEN */
1967                                 0x00000038 /* EMC_TXSR */
1968                                 0x00000038 /* EMC_TXSRDLL */
1969                                 0x00000004 /* EMC_TCKE */
1970                                 0x00000009 /* EMC_TFAW */
1971                                 0x00000000 /* EMC_TRPAB */
1972                                 0x00000004 /* EMC_TCLKSTABLE */
1973                                 0x00000005 /* EMC_TCLKSTOP */
1974                                 0x00000638 /* EMC_TREFBW */
1975                                 0x00000006 /* EMC_QUSE_EXTRA */
1976                                 0x00000006 /* EMC_FBIO_CFG6 */
1977                                 0x00000000 /* EMC_ODT_WRITE */
1978                                 0x00000000 /* EMC_ODT_READ */
1979                                 0x00004288 /* EMC_FBIO_CFG5 */
1980                                 0x004400a4 /* EMC_CFG_DIG_DLL */
1981                                 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */
1982                                 0x00080000 /* EMC_DLL_XFORM_DQS0 */
1983                                 0x00080000 /* EMC_DLL_XFORM_DQS1 */
1984                                 0x00080000 /* EMC_DLL_XFORM_DQS2 */
1985                                 0x00080000 /* EMC_DLL_XFORM_DQS3 */
1986                                 0x00080000 /* EMC_DLL_XFORM_DQS4 */
1987                                 0x00080000 /* EMC_DLL_XFORM_DQS5 */
1988                                 0x00080000 /* EMC_DLL_XFORM_DQS6 */
1989                                 0x00080000 /* EMC_DLL_XFORM_DQS7 */
1990                                 0x00000000 /* EMC_DLL_XFORM_QUSE0 */
1991                                 0x00000000 /* EMC_DLL_XFORM_QUSE1 */
1992                                 0x00000000 /* EMC_DLL_XFORM_QUSE2 */
1993                                 0x00000000 /* EMC_DLL_XFORM_QUSE3 */
1994                                 0x00000000 /* EMC_DLL_XFORM_QUSE4 */
1995                                 0x00000000 /* EMC_DLL_XFORM_QUSE5 */
1996                                 0x00000000 /* EMC_DLL_XFORM_QUSE6 */
1997                                 0x00000000 /* EMC_DLL_XFORM_QUSE7 */
1998                                 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */
1999                                 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */
2000                                 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */
2001                                 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */
2002                                 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */
2003                                 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */
2004                                 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */
2005                                 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */
2006                                 0x00080000 /* EMC_DLL_XFORM_DQ0 */
2007                                 0x00080000 /* EMC_DLL_XFORM_DQ1 */
2008                                 0x00080000 /* EMC_DLL_XFORM_DQ2 */
2009                                 0x00080000 /* EMC_DLL_XFORM_DQ3 */
2010                                 0x000002a0 /* EMC_XM2CMDPADCTRL */
2011                                 0x0800211c /* EMC_XM2DQSPADCTRL2 */
2012                                 0x00000000 /* EMC_XM2DQPADCTRL2 */
2013                                 0x77fff884 /* EMC_XM2CLKPADCTRL */
2014                                 0x01f1f108 /* EMC_XM2COMPPADCTRL */
2015                                 0x05057404 /* EMC_XM2VTTGENPADCTRL */
2016                                 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */
2017                                 0x08000168 /* EMC_XM2QUSEPADCTRL */
2018                                 0x08000000 /* EMC_XM2DQSPADCTRL3 */
2019                                 0x00000802 /* EMC_CTT_TERM_CTRL */
2020                                 0x00020000 /* EMC_ZCAL_INTERVAL */
2021                                 0x00000100 /* EMC_ZCAL_WAIT_CNT */
2022                                 0x000c000c /* EMC_MRS_WAIT_CNT */
2023                                 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */
2024                                 0x00000000 /* EMC_CTT */
2025                                 0x00000000 /* EMC_CTT_DURATION */
2026                                 0x80000d22 /* EMC_DYN_SELF_REF_CONTROL */
2027                                 0xe8000000 /* EMC_FBIO_SPARE */
2028                                 0xff00ff00 /* EMC_CFG_RSV */
2029                         >;
2030                 };
2031                 timing-400000000 {
2032                         clock-frequency = <400000000>;
2033                         nvidia,emc-auto-cal-interval = <0x001fffff>;
2034                         nvidia,emc-mode-1 = <0x80100002>;
2035                         nvidia,emc-mode-2 = <0x80200000>;
2036                         nvidia,emc-mode-reset = <0x80000521>;
2037                         nvidia,emc-zcal-cnt-long = <0x00000040>;
2038                         nvidia,emc-configuration = <
2039                                 0x00000012 /* EMC_RC */
2040                                 0x00000066 /* EMC_RFC */
2041                                 0x0000000c /* EMC_RAS */
2042                                 0x00000004 /* EMC_RP */
2043                                 0x00000003 /* EMC_R2W */
2044                                 0x00000008 /* EMC_W2R */
2045                                 0x00000002 /* EMC_R2P */
2046                                 0x0000000a /* EMC_W2P */
2047                                 0x00000004 /* EMC_RD_RCD */
2048                                 0x00000004 /* EMC_WR_RCD */
2049                                 0x00000002 /* EMC_RRD */
2050                                 0x00000001 /* EMC_REXT */
2051                                 0x00000000 /* EMC_WEXT */
2052                                 0x00000004 /* EMC_WDV */
2053                                 0x00000006 /* EMC_QUSE */
2054                                 0x00000004 /* EMC_QRST */
2055                                 0x0000000a /* EMC_QSAFE */
2056                                 0x0000000c /* EMC_RDV */
2057                                 0x00000bf0 /* EMC_REFRESH */
2058                                 0x00000000 /* EMC_BURST_REFRESH_NUM */
2059                                 0x000002fc /* EMC_PRE_REFRESH_REQ_CNT */
2060                                 0x00000001 /* EMC_PDEX2WR */
2061                                 0x00000008 /* EMC_PDEX2RD */
2062                                 0x00000001 /* EMC_PCHG2PDEN */
2063                                 0x00000000 /* EMC_ACT2PDEN */
2064                                 0x00000008 /* EMC_AR2PDEN */
2065                                 0x0000000f /* EMC_RW2PDEN */
2066                                 0x0000006c /* EMC_TXSR */
2067                                 0x00000200 /* EMC_TXSRDLL */
2068                                 0x00000004 /* EMC_TCKE */
2069                                 0x00000010 /* EMC_TFAW */
2070                                 0x00000000 /* EMC_TRPAB */
2071                                 0x00000004 /* EMC_TCLKSTABLE */
2072                                 0x00000005 /* EMC_TCLKSTOP */
2073                                 0x00000c30 /* EMC_TREFBW */
2074                                 0x00000000 /* EMC_QUSE_EXTRA */
2075                                 0x00000004 /* EMC_FBIO_CFG6 */
2076                                 0x00000000 /* EMC_ODT_WRITE */
2077                                 0x00000000 /* EMC_ODT_READ */
2078                                 0x00007088 /* EMC_FBIO_CFG5 */
2079                                 0x001d0084 /* EMC_CFG_DIG_DLL */
2080                                 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */
2081                                 0x0003c000 /* EMC_DLL_XFORM_DQS0 */
2082                                 0x0003c000 /* EMC_DLL_XFORM_DQS1 */
2083                                 0x0003c000 /* EMC_DLL_XFORM_DQS2 */
2084                                 0x0003c000 /* EMC_DLL_XFORM_DQS3 */
2085                                 0x0003c000 /* EMC_DLL_XFORM_DQS4 */
2086                                 0x0003c000 /* EMC_DLL_XFORM_DQS5 */
2087                                 0x0003c000 /* EMC_DLL_XFORM_DQS6 */
2088                                 0x0003c000 /* EMC_DLL_XFORM_DQS7 */
2089                                 0x00000000 /* EMC_DLL_XFORM_QUSE0 */
2090                                 0x00000000 /* EMC_DLL_XFORM_QUSE1 */
2091                                 0x00000000 /* EMC_DLL_XFORM_QUSE2 */
2092                                 0x00000000 /* EMC_DLL_XFORM_QUSE3 */
2093                                 0x00000000 /* EMC_DLL_XFORM_QUSE4 */
2094                                 0x00000000 /* EMC_DLL_XFORM_QUSE5 */
2095                                 0x00000000 /* EMC_DLL_XFORM_QUSE6 */
2096                                 0x00000000 /* EMC_DLL_XFORM_QUSE7 */
2097                                 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */
2098                                 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */
2099                                 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */
2100                                 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */
2101                                 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */
2102                                 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */
2103                                 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */
2104                                 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */
2105                                 0x00048000 /* EMC_DLL_XFORM_DQ0 */
2106                                 0x00048000 /* EMC_DLL_XFORM_DQ1 */
2107                                 0x00048000 /* EMC_DLL_XFORM_DQ2 */
2108                                 0x00048000 /* EMC_DLL_XFORM_DQ3 */
2109                                 0x000002a0 /* EMC_XM2CMDPADCTRL */
2110                                 0x0800013d /* EMC_XM2DQSPADCTRL2 */
2111                                 0x00000000 /* EMC_XM2DQPADCTRL2 */
2112                                 0x77fff884 /* EMC_XM2CLKPADCTRL */
2113                                 0x01f1f508 /* EMC_XM2COMPPADCTRL */
2114                                 0x05057404 /* EMC_XM2VTTGENPADCTRL */
2115                                 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */
2116                                 0x080001e8 /* EMC_XM2QUSEPADCTRL */
2117                                 0x08000021 /* EMC_XM2DQSPADCTRL3 */
2118                                 0x00000802 /* EMC_CTT_TERM_CTRL */
2119                                 0x00020000 /* EMC_ZCAL_INTERVAL */
2120                                 0x00000100 /* EMC_ZCAL_WAIT_CNT */
2121                                 0x0158000c /* EMC_MRS_WAIT_CNT */
2122                                 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */
2123                                 0x00000000 /* EMC_CTT */
2124                                 0x00000000 /* EMC_CTT_DURATION */
2125                                 0x800018c8 /* EMC_DYN_SELF_REF_CONTROL */
2126                                 0xe8000000 /* EMC_FBIO_SPARE */
2127                                 0xff00ff89 /* EMC_CFG_RSV */
2128                         >;
2129                 };
2130                 timing-800000000 {
2131                         clock-frequency = <800000000>;
2132                         nvidia,emc-auto-cal-interval = <0x001fffff>;
2133                         nvidia,emc-mode-1 = <0x80100002>;
2134                         nvidia,emc-mode-2 = <0x80200018>;
2135                         nvidia,emc-mode-reset = <0x80000d71>;
2136                         nvidia,emc-zcal-cnt-long = <0x00000040>;
2137                         nvidia,emc-cfg-periodic-qrst;
2138                         nvidia,emc-configuration = <
2139                                 0x00000025 /* EMC_RC */
2140                                 0x000000ce /* EMC_RFC */
2141                                 0x0000001a /* EMC_RAS */
2142                                 0x00000009 /* EMC_RP */
2143                                 0x00000005 /* EMC_R2W */
2144                                 0x0000000d /* EMC_W2R */
2145                                 0x00000004 /* EMC_R2P */
2146                                 0x00000013 /* EMC_W2P */
2147                                 0x00000009 /* EMC_RD_RCD */
2148                                 0x00000009 /* EMC_WR_RCD */
2149                                 0x00000004 /* EMC_RRD */
2150                                 0x00000001 /* EMC_REXT */
2151                                 0x00000000 /* EMC_WEXT */
2152                                 0x00000007 /* EMC_WDV */
2153                                 0x0000000a /* EMC_QUSE */
2154                                 0x00000009 /* EMC_QRST */
2155                                 0x0000000b /* EMC_QSAFE */
2156                                 0x00000011 /* EMC_RDV */
2157                                 0x00001820 /* EMC_REFRESH */
2158                                 0x00000000 /* EMC_BURST_REFRESH_NUM */
2159                                 0x00000608 /* EMC_PRE_REFRESH_REQ_CNT */
2160                                 0x00000003 /* EMC_PDEX2WR */
2161                                 0x00000012 /* EMC_PDEX2RD */
2162                                 0x00000001 /* EMC_PCHG2PDEN */
2163                                 0x00000000 /* EMC_ACT2PDEN */
2164                                 0x0000000f /* EMC_AR2PDEN */
2165                                 0x00000018 /* EMC_RW2PDEN */
2166                                 0x000000d8 /* EMC_TXSR */
2167                                 0x00000200 /* EMC_TXSRDLL */
2168                                 0x00000005 /* EMC_TCKE */
2169                                 0x00000020 /* EMC_TFAW */
2170                                 0x00000000 /* EMC_TRPAB */
2171                                 0x00000007 /* EMC_TCLKSTABLE */
2172                                 0x00000008 /* EMC_TCLKSTOP */
2173                                 0x00001860 /* EMC_TREFBW */
2174                                 0x0000000b /* EMC_QUSE_EXTRA */
2175                                 0x00000006 /* EMC_FBIO_CFG6 */
2176                                 0x00000000 /* EMC_ODT_WRITE */
2177                                 0x00000000 /* EMC_ODT_READ */
2178                                 0x00005088 /* EMC_FBIO_CFG5 */
2179                                 0xf0070191 /* EMC_CFG_DIG_DLL */
2180                                 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */
2181                                 0x0000800a /* EMC_DLL_XFORM_DQS0 */
2182                                 0x0000000a /* EMC_DLL_XFORM_DQS1 */
2183                                 0x0000000a /* EMC_DLL_XFORM_DQS2 */
2184                                 0x0000000a /* EMC_DLL_XFORM_DQS3 */
2185                                 0x0000000a /* EMC_DLL_XFORM_DQS4 */
2186                                 0x0000000a /* EMC_DLL_XFORM_DQS5 */
2187                                 0x0000000a /* EMC_DLL_XFORM_DQS6 */
2188                                 0x0000000a /* EMC_DLL_XFORM_DQS7 */
2189                                 0x00018000 /* EMC_DLL_XFORM_QUSE0 */
2190                                 0x00018000 /* EMC_DLL_XFORM_QUSE1 */
2191                                 0x00018000 /* EMC_DLL_XFORM_QUSE2 */
2192                                 0x00018000 /* EMC_DLL_XFORM_QUSE3 */
2193                                 0x00018000 /* EMC_DLL_XFORM_QUSE4 */
2194                                 0x00018000 /* EMC_DLL_XFORM_QUSE5 */
2195                                 0x00018000 /* EMC_DLL_XFORM_QUSE6 */
2196                                 0x00018000 /* EMC_DLL_XFORM_QUSE7 */
2197                                 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */
2198                                 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */
2199                                 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */
2200                                 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */
2201                                 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */
2202                                 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */
2203                                 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */
2204                                 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */
2205                                 0x0000000a /* EMC_DLL_XFORM_DQ0 */
2206                                 0x0000000a /* EMC_DLL_XFORM_DQ1 */
2207                                 0x0000000a /* EMC_DLL_XFORM_DQ2 */
2208                                 0x0000000a /* EMC_DLL_XFORM_DQ3 */
2209                                 0x000002a0 /* EMC_XM2CMDPADCTRL */
2210                                 0x0600013d /* EMC_XM2DQSPADCTRL2 */
2211                                 0x22220000 /* EMC_XM2DQPADCTRL2 */
2212                                 0x77fff884 /* EMC_XM2CLKPADCTRL */
2213                                 0x01f1f501 /* EMC_XM2COMPPADCTRL */
2214                                 0x07077404 /* EMC_XM2VTTGENPADCTRL */
2215                                 0x54000000 /* EMC_XM2VTTGENPADCTRL2 */
2216                                 0x080001e8 /* EMC_XM2QUSEPADCTRL */
2217                                 0x08000021 /* EMC_XM2DQSPADCTRL3 */
2218                                 0x00000802 /* EMC_CTT_TERM_CTRL */
2219                                 0x00020000 /* EMC_ZCAL_INTERVAL */
2220                                 0x00000100 /* EMC_ZCAL_WAIT_CNT */
2221                                 0x00f0000c /* EMC_MRS_WAIT_CNT */
2222                                 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */
2223                                 0x00000000 /* EMC_CTT */
2224                                 0x00000000 /* EMC_CTT_DURATION */
2225                                 0x8000308c /* EMC_DYN_SELF_REF_CONTROL */
2226                                 0xe8000000 /* EMC_FBIO_SPARE */
2227                                 0xff00ff49 /* EMC_CFG_RSV */
2228                         >;
2229                 };
2230         };
2231         emc-timings-2 {
2232                 nvidia,ram-code = <2>;  /* Hynix A RAM */
2233                 timing-25500000 {
2234                         clock-frequency = <25500000>;
2235                         nvidia,emc-auto-cal-interval = <0x001fffff>;
2236                         nvidia,emc-mode-1 = <0x80100003>;
2237                         nvidia,emc-mode-2 = <0x80200008>;
2238                         nvidia,emc-mode-reset = <0x80001221>;
2239                         nvidia,emc-zcal-cnt-long = <0x00000040>;
2240                         nvidia,emc-cfg-periodic-qrst;
2241                         nvidia,emc-cfg-dyn-self-ref;
2242                         nvidia,emc-configuration = <
2243                                 0x00000001 /* EMC_RC */
2244                                 0x00000007 /* EMC_RFC */
2245                                 0x00000000 /* EMC_RAS */
2246                                 0x00000000 /* EMC_RP */
2247                                 0x00000002 /* EMC_R2W */
2248                                 0x0000000a /* EMC_W2R */
2249                                 0x00000005 /* EMC_R2P */
2250                                 0x0000000b /* EMC_W2P */
2251                                 0x00000000 /* EMC_RD_RCD */
2252                                 0x00000000 /* EMC_WR_RCD */
2253                                 0x00000003 /* EMC_RRD */
2254                                 0x00000001 /* EMC_REXT */
2255                                 0x00000000 /* EMC_WEXT */
2256                                 0x00000005 /* EMC_WDV */
2257                                 0x00000005 /* EMC_QUSE */
2258                                 0x00000004 /* EMC_QRST */
2259                                 0x0000000a /* EMC_QSAFE */
2260                                 0x0000000b /* EMC_RDV */
2261                                 0x000000c0 /* EMC_REFRESH */
2262                                 0x00000000 /* EMC_BURST_REFRESH_NUM */
2263                                 0x00000030 /* EMC_PRE_REFRESH_REQ_CNT */
2264                                 0x00000002 /* EMC_PDEX2WR */
2265                                 0x00000002 /* EMC_PDEX2RD */
2266                                 0x00000001 /* EMC_PCHG2PDEN */
2267                                 0x00000000 /* EMC_ACT2PDEN */
2268                                 0x00000007 /* EMC_AR2PDEN */
2269                                 0x0000000f /* EMC_RW2PDEN */
2270                                 0x00000008 /* EMC_TXSR */
2271                                 0x00000008 /* EMC_TXSRDLL */
2272                                 0x00000004 /* EMC_TCKE */
2273                                 0x00000002 /* EMC_TFAW */
2274                                 0x00000000 /* EMC_TRPAB */
2275                                 0x00000004 /* EMC_TCLKSTABLE */
2276                                 0x00000005 /* EMC_TCLKSTOP */
2277                                 0x000000c7 /* EMC_TREFBW */
2278                                 0x00000006 /* EMC_QUSE_EXTRA */
2279                                 0x00000004 /* EMC_FBIO_CFG6 */
2280                                 0x00000000 /* EMC_ODT_WRITE */
2281                                 0x00000000 /* EMC_ODT_READ */
2282                                 0x00004288 /* EMC_FBIO_CFG5 */
2283                                 0x007800a4 /* EMC_CFG_DIG_DLL */
2284                                 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */
2285                                 0x000fc000 /* EMC_DLL_XFORM_DQS0 */
2286                                 0x000fc000 /* EMC_DLL_XFORM_DQS1 */
2287                                 0x000fc000 /* EMC_DLL_XFORM_DQS2 */
2288                                 0x000fc000 /* EMC_DLL_XFORM_DQS3 */
2289                                 0x000fc000 /* EMC_DLL_XFORM_DQS4 */
2290                                 0x000fc000 /* EMC_DLL_XFORM_DQS5 */
2291                                 0x000fc000 /* EMC_DLL_XFORM_DQS6 */
2292                                 0x000fc000 /* EMC_DLL_XFORM_DQS7 */
2293                                 0x00000000 /* EMC_DLL_XFORM_QUSE0 */
2294                                 0x00000000 /* EMC_DLL_XFORM_QUSE1 */
2295                                 0x00000000 /* EMC_DLL_XFORM_QUSE2 */
2296                                 0x00000000 /* EMC_DLL_XFORM_QUSE3 */
2297                                 0x00000000 /* EMC_DLL_XFORM_QUSE4 */
2298                                 0x00000000 /* EMC_DLL_XFORM_QUSE5 */
2299                                 0x00000000 /* EMC_DLL_XFORM_QUSE6 */
2300                                 0x00000000 /* EMC_DLL_XFORM_QUSE7 */
2301                                 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */
2302                                 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */
2303                                 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */
2304                                 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */
2305                                 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */
2306                                 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */
2307                                 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */
2308                                 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */
2309                                 0x000fc000 /* EMC_DLL_XFORM_DQ0 */
2310                                 0x000fc000 /* EMC_DLL_XFORM_DQ1 */
2311                                 0x000fc000 /* EMC_DLL_XFORM_DQ2 */
2312                                 0x000fc000 /* EMC_DLL_XFORM_DQ3 */
2313                                 0x000002a0 /* EMC_XM2CMDPADCTRL */
2314                                 0x0800211c /* EMC_XM2DQSPADCTRL2 */
2315                                 0x00000000 /* EMC_XM2DQPADCTRL2 */
2316                                 0x77fff884 /* EMC_XM2CLKPADCTRL */
2317                                 0x01f1f108 /* EMC_XM2COMPPADCTRL */
2318                                 0x05057404 /* EMC_XM2VTTGENPADCTRL */
2319                                 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */
2320                                 0x08000168 /* EMC_XM2QUSEPADCTRL */
2321                                 0x08000000 /* EMC_XM2DQSPADCTRL3 */
2322                                 0x00000802 /* EMC_CTT_TERM_CTRL */
2323                                 0x00000000 /* EMC_ZCAL_INTERVAL */
2324                                 0x00000040 /* EMC_ZCAL_WAIT_CNT */
2325                                 0x000c000c /* EMC_MRS_WAIT_CNT */
2326                                 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */
2327                                 0x00000000 /* EMC_CTT */
2328                                 0x00000000 /* EMC_CTT_DURATION */
2329                                 0x80000287 /* EMC_DYN_SELF_REF_CONTROL */
2330                                 0xe8000000 /* EMC_FBIO_SPARE */
2331                                 0xff00ff00 /* EMC_CFG_RSV */
2332                         >;
2333                 };
2334                 timing-51000000 {
2335                         clock-frequency = <51000000>;
2336                         nvidia,emc-auto-cal-interval = <0x001fffff>;
2337                         nvidia,emc-mode-1 = <0x80100003>;
2338                         nvidia,emc-mode-2 = <0x80200008>;
2339                         nvidia,emc-mode-reset = <0x80001221>;
2340                         nvidia,emc-zcal-cnt-long = <0x00000040>;
2341                         nvidia,emc-cfg-periodic-qrst;
2342                         nvidia,emc-cfg-dyn-self-ref;
2343                         nvidia,emc-configuration = <
2344                                 0x00000002 /* EMC_RC */
2345                                 0x0000000f /* EMC_RFC */
2346                                 0x00000001 /* EMC_RAS */
2347                                 0x00000000 /* EMC_RP */
2348                                 0x00000002 /* EMC_R2W */
2349                                 0x0000000a /* EMC_W2R */
2350                                 0x00000005 /* EMC_R2P */
2351                                 0x0000000b /* EMC_W2P */
2352                                 0x00000000 /* EMC_RD_RCD */
2353                                 0x00000000 /* EMC_WR_RCD */
2354                                 0x00000003 /* EMC_RRD */
2355                                 0x00000001 /* EMC_REXT */
2356                                 0x00000000 /* EMC_WEXT */
2357                                 0x00000005 /* EMC_WDV */
2358                                 0x00000005 /* EMC_QUSE */
2359                                 0x00000004 /* EMC_QRST */
2360                                 0x0000000a /* EMC_QSAFE */
2361                                 0x0000000b /* EMC_RDV */
2362                                 0x00000181 /* EMC_REFRESH */
2363                                 0x00000000 /* EMC_BURST_REFRESH_NUM */
2364                                 0x00000060 /* EMC_PRE_REFRESH_REQ_CNT */
2365                                 0x00000002 /* EMC_PDEX2WR */
2366                                 0x00000002 /* EMC_PDEX2RD */
2367                                 0x00000001 /* EMC_PCHG2PDEN */
2368                                 0x00000000 /* EMC_ACT2PDEN */
2369                                 0x00000007 /* EMC_AR2PDEN */
2370                                 0x0000000f /* EMC_RW2PDEN */
2371                                 0x00000010 /* EMC_TXSR */
2372                                 0x00000010 /* EMC_TXSRDLL */
2373                                 0x00000004 /* EMC_TCKE */
2374                                 0x00000003 /* EMC_TFAW */
2375                                 0x00000000 /* EMC_TRPAB */
2376                                 0x00000004 /* EMC_TCLKSTABLE */
2377                                 0x00000005 /* EMC_TCLKSTOP */
2378                                 0x0000018e /* EMC_TREFBW */
2379                                 0x00000006 /* EMC_QUSE_EXTRA */
2380                                 0x00000004 /* EMC_FBIO_CFG6 */
2381                                 0x00000000 /* EMC_ODT_WRITE */
2382                                 0x00000000 /* EMC_ODT_READ */
2383                                 0x00004288 /* EMC_FBIO_CFG5 */
2384                                 0x007800a4 /* EMC_CFG_DIG_DLL */
2385                                 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */
2386                                 0x000fc000 /* EMC_DLL_XFORM_DQS0 */
2387                                 0x000fc000 /* EMC_DLL_XFORM_DQS1 */
2388                                 0x000fc000 /* EMC_DLL_XFORM_DQS2 */
2389                                 0x000fc000 /* EMC_DLL_XFORM_DQS3 */
2390                                 0x000fc000 /* EMC_DLL_XFORM_DQS4 */
2391                                 0x000fc000 /* EMC_DLL_XFORM_DQS5 */
2392                                 0x000fc000 /* EMC_DLL_XFORM_DQS6 */
2393                                 0x000fc000 /* EMC_DLL_XFORM_DQS7 */
2394                                 0x00000000 /* EMC_DLL_XFORM_QUSE0 */
2395                                 0x00000000 /* EMC_DLL_XFORM_QUSE1 */
2396                                 0x00000000 /* EMC_DLL_XFORM_QUSE2 */
2397                                 0x00000000 /* EMC_DLL_XFORM_QUSE3 */
2398                                 0x00000000 /* EMC_DLL_XFORM_QUSE4 */
2399                                 0x00000000 /* EMC_DLL_XFORM_QUSE5 */
2400                                 0x00000000 /* EMC_DLL_XFORM_QUSE6 */
2401                                 0x00000000 /* EMC_DLL_XFORM_QUSE7 */
2402                                 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */
2403                                 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */
2404                                 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */
2405                                 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */
2406                                 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */
2407                                 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */
2408                                 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */
2409                                 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */
2410                                 0x000fc000 /* EMC_DLL_XFORM_DQ0 */
2411                                 0x000fc000 /* EMC_DLL_XFORM_DQ1 */
2412                                 0x000fc000 /* EMC_DLL_XFORM_DQ2 */
2413                                 0x000fc000 /* EMC_DLL_XFORM_DQ3 */
2414                                 0x000002a0 /* EMC_XM2CMDPADCTRL */
2415                                 0x0800211c /* EMC_XM2DQSPADCTRL2 */
2416                                 0x00000000 /* EMC_XM2DQPADCTRL2 */
2417                                 0x77fff884 /* EMC_XM2CLKPADCTRL */
2418                                 0x01f1f108 /* EMC_XM2COMPPADCTRL */
2419                                 0x05057404 /* EMC_XM2VTTGENPADCTRL */
2420                                 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */
2421                                 0x08000168 /* EMC_XM2QUSEPADCTRL */
2422                                 0x08000000 /* EMC_XM2DQSPADCTRL3 */
2423                                 0x00000802 /* EMC_CTT_TERM_CTRL */
2424                                 0x00000000 /* EMC_ZCAL_INTERVAL */
2425                                 0x00000040 /* EMC_ZCAL_WAIT_CNT */
2426                                 0x000c000c /* EMC_MRS_WAIT_CNT */
2427                                 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */
2428                                 0x00000000 /* EMC_CTT */
2429                                 0x00000000 /* EMC_CTT_DURATION */
2430                                 0x8000040b /* EMC_DYN_SELF_REF_CONTROL */
2431                                 0xe8000000 /* EMC_FBIO_SPARE */
2432                                 0xff00ff00 /* EMC_CFG_RSV */
2433                         >;
2434                 };
2435                 timing-102000000 {
2436                         clock-frequency = <102000000>;
2437                         nvidia,emc-auto-cal-interval = <0x001fffff>;
2438                         nvidia,emc-mode-1 = <0x80100003>;
2439                         nvidia,emc-mode-2 = <0x80200008>;
2440                         nvidia,emc-mode-reset = <0x80001221>;
2441                         nvidia,emc-zcal-cnt-long = <0x00000040>;
2442                         nvidia,emc-cfg-periodic-qrst;
2443                         nvidia,emc-cfg-dyn-self-ref;
2444                         nvidia,emc-configuration = <
2445                                 0x00000004 /* EMC_RC */
2446                                 0x0000001e /* EMC_RFC */
2447                                 0x00000003 /* EMC_RAS */
2448                                 0x00000001 /* EMC_RP */
2449                                 0x00000002 /* EMC_R2W */
2450                                 0x0000000a /* EMC_W2R */
2451                                 0x00000005 /* EMC_R2P */
2452                                 0x0000000b /* EMC_W2P */
2453                                 0x00000001 /* EMC_RD_RCD */
2454                                 0x00000001 /* EMC_WR_RCD */
2455                                 0x00000003 /* EMC_RRD */
2456                                 0x00000001 /* EMC_REXT */
2457                                 0x00000000 /* EMC_WEXT */
2458                                 0x00000005 /* EMC_WDV */
2459                                 0x00000005 /* EMC_QUSE */
2460                                 0x00000004 /* EMC_QRST */
2461                                 0x0000000a /* EMC_QSAFE */
2462                                 0x0000000b /* EMC_RDV */
2463                                 0x00000303 /* EMC_REFRESH */
2464                                 0x00000000 /* EMC_BURST_REFRESH_NUM */
2465                                 0x000000c0 /* EMC_PRE_REFRESH_REQ_CNT */
2466                                 0x00000002 /* EMC_PDEX2WR */
2467                                 0x00000002 /* EMC_PDEX2RD */
2468                                 0x00000001 /* EMC_PCHG2PDEN */
2469                                 0x00000000 /* EMC_ACT2PDEN */
2470                                 0x00000007 /* EMC_AR2PDEN */
2471                                 0x0000000f /* EMC_RW2PDEN */
2472                                 0x00000020 /* EMC_TXSR */
2473                                 0x00000020 /* EMC_TXSRDLL */
2474                                 0x00000004 /* EMC_TCKE */
2475                                 0x00000005 /* EMC_TFAW */
2476                                 0x00000000 /* EMC_TRPAB */
2477                                 0x00000004 /* EMC_TCLKSTABLE */
2478                                 0x00000005 /* EMC_TCLKSTOP */
2479                                 0x0000031c /* EMC_TREFBW */
2480                                 0x00000006 /* EMC_QUSE_EXTRA */
2481                                 0x00000004 /* EMC_FBIO_CFG6 */
2482                                 0x00000000 /* EMC_ODT_WRITE */
2483                                 0x00000000 /* EMC_ODT_READ */
2484                                 0x00004288 /* EMC_FBIO_CFG5 */
2485                                 0x007800a4 /* EMC_CFG_DIG_DLL */
2486                                 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */
2487                                 0x000fc000 /* EMC_DLL_XFORM_DQS0 */
2488                                 0x000fc000 /* EMC_DLL_XFORM_DQS1 */
2489                                 0x000fc000 /* EMC_DLL_XFORM_DQS2 */
2490                                 0x000fc000 /* EMC_DLL_XFORM_DQS3 */
2491                                 0x000fc000 /* EMC_DLL_XFORM_DQS4 */
2492                                 0x000fc000 /* EMC_DLL_XFORM_DQS5 */
2493                                 0x000fc000 /* EMC_DLL_XFORM_DQS6 */
2494                                 0x000fc000 /* EMC_DLL_XFORM_DQS7 */
2495                                 0x00000000 /* EMC_DLL_XFORM_QUSE0 */
2496                                 0x00000000 /* EMC_DLL_XFORM_QUSE1 */
2497                                 0x00000000 /* EMC_DLL_XFORM_QUSE2 */
2498                                 0x00000000 /* EMC_DLL_XFORM_QUSE3 */
2499                                 0x00000000 /* EMC_DLL_XFORM_QUSE4 */
2500                                 0x00000000 /* EMC_DLL_XFORM_QUSE5 */
2501                                 0x00000000 /* EMC_DLL_XFORM_QUSE6 */
2502                                 0x00000000 /* EMC_DLL_XFORM_QUSE7 */
2503                                 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */
2504                                 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */
2505                                 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */
2506                                 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */
2507                                 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */
2508                                 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */
2509                                 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */
2510                                 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */
2511                                 0x000fc000 /* EMC_DLL_XFORM_DQ0 */
2512                                 0x000fc000 /* EMC_DLL_XFORM_DQ1 */
2513                                 0x000fc000 /* EMC_DLL_XFORM_DQ2 */
2514                                 0x000fc000 /* EMC_DLL_XFORM_DQ3 */
2515                                 0x000002a0 /* EMC_XM2CMDPADCTRL */
2516                                 0x0800211c /* EMC_XM2DQSPADCTRL2 */
2517                                 0x00000000 /* EMC_XM2DQPADCTRL2 */
2518                                 0x77fff884 /* EMC_XM2CLKPADCTRL */
2519                                 0x01f1f108 /* EMC_XM2COMPPADCTRL */
2520                                 0x05057404 /* EMC_XM2VTTGENPADCTRL */
2521                                 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */
2522                                 0x08000168 /* EMC_XM2QUSEPADCTRL */
2523                                 0x08000000 /* EMC_XM2DQSPADCTRL3 */
2524                                 0x00000802 /* EMC_CTT_TERM_CTRL */
2525                                 0x00000000 /* EMC_ZCAL_INTERVAL */
2526                                 0x00000040 /* EMC_ZCAL_WAIT_CNT */
2527                                 0x000c000c /* EMC_MRS_WAIT_CNT */
2528                                 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */
2529                                 0x00000000 /* EMC_CTT */
2530                                 0x00000000 /* EMC_CTT_DURATION */
2531                                 0x80000713 /* EMC_DYN_SELF_REF_CONTROL */
2532                                 0xe8000000 /* EMC_FBIO_SPARE */
2533                                 0xff00ff00 /* EMC_CFG_RSV */
2534                         >;
2535                 };
2536                 timing-204000000 {
2537                         clock-frequency = <204000000>;
2538                         nvidia,emc-auto-cal-interval = <0x001fffff>;
2539                         nvidia,emc-mode-1 = <0x80100003>;
2540                         nvidia,emc-mode-2 = <0x80200008>;
2541                         nvidia,emc-mode-reset = <0x80001221>;
2542                         nvidia,emc-zcal-cnt-long = <0x00000040>;
2543                         nvidia,emc-cfg-periodic-qrst;
2544                         nvidia,emc-cfg-dyn-self-ref;
2545                         nvidia,emc-configuration = <
2546                                 0x00000009 /* EMC_RC */
2547                                 0x0000003d /* EMC_RFC */
2548                                 0x00000007 /* EMC_RAS */
2549                                 0x00000002 /* EMC_RP */
2550                                 0x00000002 /* EMC_R2W */
2551                                 0x0000000a /* EMC_W2R */
2552                                 0x00000005 /* EMC_R2P */
2553                                 0x0000000b /* EMC_W2P */
2554                                 0x00000002 /* EMC_RD_RCD */
2555                                 0x00000002 /* EMC_WR_RCD */
2556                                 0x00000003 /* EMC_RRD */
2557                                 0x00000001 /* EMC_REXT */
2558                                 0x00000000 /* EMC_WEXT */
2559                                 0x00000005 /* EMC_WDV */
2560                                 0x00000005 /* EMC_QUSE */
2561                                 0x00000004 /* EMC_QRST */
2562                                 0x0000000a /* EMC_QSAFE */
2563                                 0x0000000b /* EMC_RDV */
2564                                 0x00000607 /* EMC_REFRESH */
2565                                 0x00000000 /* EMC_BURST_REFRESH_NUM */
2566                                 0x00000181 /* EMC_PRE_REFRESH_REQ_CNT */
2567                                 0x00000002 /* EMC_PDEX2WR */
2568                                 0x00000002 /* EMC_PDEX2RD */
2569                                 0x00000001 /* EMC_PCHG2PDEN */
2570                                 0x00000000 /* EMC_ACT2PDEN */
2571                                 0x00000007 /* EMC_AR2PDEN */
2572                                 0x0000000f /* EMC_RW2PDEN */
2573                                 0x00000040 /* EMC_TXSR */
2574                                 0x00000040 /* EMC_TXSRDLL */
2575                                 0x00000004 /* EMC_TCKE */
2576                                 0x00000009 /* EMC_TFAW */
2577                                 0x00000000 /* EMC_TRPAB */
2578                                 0x00000004 /* EMC_TCLKSTABLE */
2579                                 0x00000005 /* EMC_TCLKSTOP */
2580                                 0x00000638 /* EMC_TREFBW */
2581                                 0x00000006 /* EMC_QUSE_EXTRA */
2582                                 0x00000006 /* EMC_FBIO_CFG6 */
2583                                 0x00000000 /* EMC_ODT_WRITE */
2584                                 0x00000000 /* EMC_ODT_READ */
2585                                 0x00004288 /* EMC_FBIO_CFG5 */
2586                                 0x004400a4 /* EMC_CFG_DIG_DLL */
2587                                 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */
2588                                 0x00080000 /* EMC_DLL_XFORM_DQS0 */
2589                                 0x00080000 /* EMC_DLL_XFORM_DQS1 */
2590                                 0x00080000 /* EMC_DLL_XFORM_DQS2 */
2591                                 0x00080000 /* EMC_DLL_XFORM_DQS3 */
2592                                 0x00080000 /* EMC_DLL_XFORM_DQS4 */
2593                                 0x00080000 /* EMC_DLL_XFORM_DQS5 */
2594                                 0x00080000 /* EMC_DLL_XFORM_DQS6 */
2595                                 0x00080000 /* EMC_DLL_XFORM_DQS7 */
2596                                 0x00000000 /* EMC_DLL_XFORM_QUSE0 */
2597                                 0x00000000 /* EMC_DLL_XFORM_QUSE1 */
2598                                 0x00000000 /* EMC_DLL_XFORM_QUSE2 */
2599                                 0x00000000 /* EMC_DLL_XFORM_QUSE3 */
2600                                 0x00000000 /* EMC_DLL_XFORM_QUSE4 */
2601                                 0x00000000 /* EMC_DLL_XFORM_QUSE5 */
2602                                 0x00000000 /* EMC_DLL_XFORM_QUSE6 */
2603                                 0x00000000 /* EMC_DLL_XFORM_QUSE7 */
2604                                 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */
2605                                 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */
2606                                 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */
2607                                 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */
2608                                 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */
2609                                 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */
2610                                 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */
2611                                 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */
2612                                 0x00080000 /* EMC_DLL_XFORM_DQ0 */
2613                                 0x00080000 /* EMC_DLL_XFORM_DQ1 */
2614                                 0x00080000 /* EMC_DLL_XFORM_DQ2 */
2615                                 0x00080000 /* EMC_DLL_XFORM_DQ3 */
2616                                 0x000002a0 /* EMC_XM2CMDPADCTRL */
2617                                 0x0800211c /* EMC_XM2DQSPADCTRL2 */
2618                                 0x00000000 /* EMC_XM2DQPADCTRL2 */
2619                                 0x77fff884 /* EMC_XM2CLKPADCTRL */
2620                                 0x01f1f108 /* EMC_XM2COMPPADCTRL */
2621                                 0x05057404 /* EMC_XM2VTTGENPADCTRL */
2622                                 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */
2623                                 0x08000168 /* EMC_XM2QUSEPADCTRL */
2624                                 0x08000000 /* EMC_XM2DQSPADCTRL3 */
2625                                 0x00000802 /* EMC_CTT_TERM_CTRL */
2626                                 0x00020000 /* EMC_ZCAL_INTERVAL */
2627                                 0x00000100 /* EMC_ZCAL_WAIT_CNT */
2628                                 0x000c000c /* EMC_MRS_WAIT_CNT */
2629                                 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */
2630                                 0x00000000 /* EMC_CTT */
2631                                 0x00000000 /* EMC_CTT_DURATION */
2632                                 0x80000d22 /* EMC_DYN_SELF_REF_CONTROL */
2633                                 0xe8000000 /* EMC_FBIO_SPARE */
2634                                 0xff00ff00 /* EMC_CFG_RSV */
2635                         >;
2636                 };
2637                 timing-400000000 {
2638                         clock-frequency = <400000000>;
2639                         nvidia,emc-auto-cal-interval = <0x001fffff>;
2640                         nvidia,emc-mode-1 = <0x80100002>;
2641                         nvidia,emc-mode-2 = <0x80200000>;
2642                         nvidia,emc-mode-reset = <0x80000521>;
2643                         nvidia,emc-zcal-cnt-long = <0x00000040>;
2644                         nvidia,emc-configuration = <
2645                                 0x00000012 /* EMC_RC */
2646                                 0x00000076 /* EMC_RFC */
2647                                 0x0000000c /* EMC_RAS */
2648                                 0x00000004 /* EMC_RP */
2649                                 0x00000003 /* EMC_R2W */
2650                                 0x00000008 /* EMC_W2R */
2651                                 0x00000002 /* EMC_R2P */
2652                                 0x0000000a /* EMC_W2P */
2653                                 0x00000004 /* EMC_RD_RCD */
2654                                 0x00000004 /* EMC_WR_RCD */
2655                                 0x00000002 /* EMC_RRD */
2656                                 0x00000001 /* EMC_REXT */
2657                                 0x00000000 /* EMC_WEXT */
2658                                 0x00000004 /* EMC_WDV */
2659                                 0x00000006 /* EMC_QUSE */
2660                                 0x00000004 /* EMC_QRST */
2661                                 0x0000000a /* EMC_QSAFE */
2662                                 0x0000000c /* EMC_RDV */
2663                                 0x00000bf0 /* EMC_REFRESH */
2664                                 0x00000000 /* EMC_BURST_REFRESH_NUM */
2665                                 0x000002fc /* EMC_PRE_REFRESH_REQ_CNT */
2666                                 0x00000001 /* EMC_PDEX2WR */
2667                                 0x00000008 /* EMC_PDEX2RD */
2668                                 0x00000001 /* EMC_PCHG2PDEN */
2669                                 0x00000000 /* EMC_ACT2PDEN */
2670                                 0x00000008 /* EMC_AR2PDEN */
2671                                 0x0000000f /* EMC_RW2PDEN */
2672                                 0x0000007c /* EMC_TXSR */
2673                                 0x00000200 /* EMC_TXSRDLL */
2674                                 0x00000004 /* EMC_TCKE */
2675                                 0x00000010 /* EMC_TFAW */
2676                                 0x00000000 /* EMC_TRPAB */
2677                                 0x00000004 /* EMC_TCLKSTABLE */
2678                                 0x00000005 /* EMC_TCLKSTOP */
2679                                 0x00000c30 /* EMC_TREFBW */
2680                                 0x00000000 /* EMC_QUSE_EXTRA */
2681                                 0x00000004 /* EMC_FBIO_CFG6 */
2682                                 0x00000000 /* EMC_ODT_WRITE */
2683                                 0x00000000 /* EMC_ODT_READ */
2684                                 0x00007088 /* EMC_FBIO_CFG5 */
2685                                 0x001d0084 /* EMC_CFG_DIG_DLL */
2686                                 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */
2687                                 0x00044000 /* EMC_DLL_XFORM_DQS0 */
2688                                 0x00044000 /* EMC_DLL_XFORM_DQS1 */
2689                                 0x00044000 /* EMC_DLL_XFORM_DQS2 */
2690                                 0x00044000 /* EMC_DLL_XFORM_DQS3 */
2691                                 0x00044000 /* EMC_DLL_XFORM_DQS4 */
2692                                 0x00044000 /* EMC_DLL_XFORM_DQS5 */
2693                                 0x00044000 /* EMC_DLL_XFORM_DQS6 */
2694                                 0x00044000 /* EMC_DLL_XFORM_DQS7 */
2695                                 0x00000000 /* EMC_DLL_XFORM_QUSE0 */
2696                                 0x00000000 /* EMC_DLL_XFORM_QUSE1 */
2697                                 0x00000000 /* EMC_DLL_XFORM_QUSE2 */
2698                                 0x00000000 /* EMC_DLL_XFORM_QUSE3 */
2699                                 0x00000000 /* EMC_DLL_XFORM_QUSE4 */
2700                                 0x00000000 /* EMC_DLL_XFORM_QUSE5 */
2701                                 0x00000000 /* EMC_DLL_XFORM_QUSE6 */
2702                                 0x00000000 /* EMC_DLL_XFORM_QUSE7 */
2703                                 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */
2704                                 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */
2705                                 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */
2706                                 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */
2707                                 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */
2708                                 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */
2709                                 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */
2710                                 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */
2711                                 0x00058000 /* EMC_DLL_XFORM_DQ0 */
2712                                 0x00058000 /* EMC_DLL_XFORM_DQ1 */
2713                                 0x00058000 /* EMC_DLL_XFORM_DQ2 */
2714                                 0x00058000 /* EMC_DLL_XFORM_DQ3 */
2715                                 0x000002a0 /* EMC_XM2CMDPADCTRL */
2716                                 0x0800013d /* EMC_XM2DQSPADCTRL2 */
2717                                 0x00000000 /* EMC_XM2DQPADCTRL2 */
2718                                 0x77fff884 /* EMC_XM2CLKPADCTRL */
2719                                 0x01f1f508 /* EMC_XM2COMPPADCTRL */
2720                                 0x05057404 /* EMC_XM2VTTGENPADCTRL */
2721                                 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */
2722                                 0x080001e8 /* EMC_XM2QUSEPADCTRL */
2723                                 0x08000021 /* EMC_XM2DQSPADCTRL3 */
2724                                 0x00000802 /* EMC_CTT_TERM_CTRL */
2725                                 0x00020000 /* EMC_ZCAL_INTERVAL */
2726                                 0x00000100 /* EMC_ZCAL_WAIT_CNT */
2727                                 0x0148000c /* EMC_MRS_WAIT_CNT */
2728                                 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */
2729                                 0x00000000 /* EMC_CTT */
2730                                 0x00000000 /* EMC_CTT_DURATION */
2731                                 0x800018c8 /* EMC_DYN_SELF_REF_CONTROL */
2732                                 0xe8000000 /* EMC_FBIO_SPARE */
2733                                 0xff00ff89 /* EMC_CFG_RSV */
2734                         >;
2735                 };
2736                 timing-800000000 {
2737                         clock-frequency = <800000000>;
2738                         nvidia,emc-auto-cal-interval = <0x001fffff>;
2739                         nvidia,emc-mode-1 = <0x80100002>;
2740                         nvidia,emc-mode-2 = <0x80200018>;
2741                         nvidia,emc-mode-reset = <0x80000d71>;
2742                         nvidia,emc-zcal-cnt-long = <0x00000040>;
2743                         nvidia,emc-cfg-periodic-qrst;
2744                         nvidia,emc-configuration = <
2745                                 0x00000025 /* EMC_RC */
2746                                 0x000000ee /* EMC_RFC */
2747                                 0x0000001a /* EMC_RAS */
2748                                 0x00000009 /* EMC_RP */
2749                                 0x00000005 /* EMC_R2W */
2750                                 0x0000000d /* EMC_W2R */
2751                                 0x00000004 /* EMC_R2P */
2752                                 0x00000013 /* EMC_W2P */
2753                                 0x00000009 /* EMC_RD_RCD */
2754                                 0x00000009 /* EMC_WR_RCD */
2755                                 0x00000003 /* EMC_RRD */
2756                                 0x00000001 /* EMC_REXT */
2757                                 0x00000000 /* EMC_WEXT */
2758                                 0x00000007 /* EMC_WDV */
2759                                 0x0000000a /* EMC_QUSE */
2760                                 0x00000009 /* EMC_QRST */
2761                                 0x0000000b /* EMC_QSAFE */
2762                                 0x00000011 /* EMC_RDV */
2763                                 0x00001820 /* EMC_REFRESH */
2764                                 0x00000000 /* EMC_BURST_REFRESH_NUM */
2765                                 0x00000608 /* EMC_PRE_REFRESH_REQ_CNT */
2766                                 0x00000003 /* EMC_PDEX2WR */
2767                                 0x00000012 /* EMC_PDEX2RD */
2768                                 0x00000001 /* EMC_PCHG2PDEN */
2769                                 0x00000000 /* EMC_ACT2PDEN */
2770                                 0x0000000f /* EMC_AR2PDEN */
2771                                 0x00000018 /* EMC_RW2PDEN */
2772                                 0x000000f8 /* EMC_TXSR */
2773                                 0x00000200 /* EMC_TXSRDLL */
2774                                 0x00000005 /* EMC_TCKE */
2775                                 0x00000020 /* EMC_TFAW */
2776                                 0x00000000 /* EMC_TRPAB */
2777                                 0x00000007 /* EMC_TCLKSTABLE */
2778                                 0x00000008 /* EMC_TCLKSTOP */
2779                                 0x00001860 /* EMC_TREFBW */
2780                                 0x0000000b /* EMC_QUSE_EXTRA */
2781                                 0x00000006 /* EMC_FBIO_CFG6 */
2782                                 0x00000000 /* EMC_ODT_WRITE */
2783                                 0x00000000 /* EMC_ODT_READ */
2784                                 0x00005088 /* EMC_FBIO_CFG5 */
2785                                 0xf0070191 /* EMC_CFG_DIG_DLL */
2786                                 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */
2787                                 0x0000000c /* EMC_DLL_XFORM_DQS0 */
2788                                 0x007fc00a /* EMC_DLL_XFORM_DQS1 */
2789                                 0x00000008 /* EMC_DLL_XFORM_DQS2 */
2790                                 0x0000000a /* EMC_DLL_XFORM_DQS3 */
2791                                 0x0000000a /* EMC_DLL_XFORM_DQS4 */
2792                                 0x0000000a /* EMC_DLL_XFORM_DQS5 */
2793                                 0x0000000a /* EMC_DLL_XFORM_DQS6 */
2794                                 0x0000000a /* EMC_DLL_XFORM_DQS7 */
2795                                 0x00018000 /* EMC_DLL_XFORM_QUSE0 */
2796                                 0x00018000 /* EMC_DLL_XFORM_QUSE1 */
2797                                 0x00018000 /* EMC_DLL_XFORM_QUSE2 */
2798                                 0x00018000 /* EMC_DLL_XFORM_QUSE3 */
2799                                 0x00018000 /* EMC_DLL_XFORM_QUSE4 */
2800                                 0x00018000 /* EMC_DLL_XFORM_QUSE5 */
2801                                 0x00018000 /* EMC_DLL_XFORM_QUSE6 */
2802                                 0x00018000 /* EMC_DLL_XFORM_QUSE7 */
2803                                 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */
2804                                 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */
2805                                 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */
2806                                 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */
2807                                 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */
2808                                 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */
2809                                 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */
2810                                 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */
2811                                 0x0000000a /* EMC_DLL_XFORM_DQ0 */
2812                                 0x0000000c /* EMC_DLL_XFORM_DQ1 */
2813                                 0x0000000a /* EMC_DLL_XFORM_DQ2 */
2814                                 0x0000000a /* EMC_DLL_XFORM_DQ3 */
2815                                 0x000002a0 /* EMC_XM2CMDPADCTRL */
2816                                 0x0600013d /* EMC_XM2DQSPADCTRL2 */
2817                                 0x22220000 /* EMC_XM2DQPADCTRL2 */
2818                                 0x77fff884 /* EMC_XM2CLKPADCTRL */
2819                                 0x01f1f501 /* EMC_XM2COMPPADCTRL */
2820                                 0x07077404 /* EMC_XM2VTTGENPADCTRL */
2821                                 0x54000000 /* EMC_XM2VTTGENPADCTRL2 */
2822                                 0x080001e8 /* EMC_XM2QUSEPADCTRL */
2823                                 0x0a000021 /* EMC_XM2DQSPADCTRL3 */
2824                                 0x00000802 /* EMC_CTT_TERM_CTRL */
2825                                 0x00020000 /* EMC_ZCAL_INTERVAL */
2826                                 0x00000100 /* EMC_ZCAL_WAIT_CNT */
2827                                 0x00d0000c /* EMC_MRS_WAIT_CNT */
2828                                 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */
2829                                 0x00000000 /* EMC_CTT */
2830                                 0x00000000 /* EMC_CTT_DURATION */
2831                                 0x8000308c /* EMC_DYN_SELF_REF_CONTROL */
2832                                 0xe8000000 /* EMC_FBIO_SPARE */
2833                                 0xff00ff49 /* EMC_CFG_RSV */
2834                         >;
2835                 };
2836         };
2837 };
2838 &state_default {
2839         clk_32k_out_pa0 {
2840                 nvidia,pins = "clk_32k_out_pa0";
2841                 nvidia,function = "blink";
2842                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
2843                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
2844                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
2845         };
2846         uart3_cts_n_pa1 {
2847                 nvidia,pins = "uart3_cts_n_pa1";
2848                 nvidia,function = "uartc";
2849                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
2850                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
2851                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
2852         };
2853         dap2_fs_pa2 {
2854                 nvidia,pins = "dap2_fs_pa2";
2855                 nvidia,function = "i2s1";
2856                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
2857                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
2858                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
2859         };
2860         dap2_sclk_pa3 {
2861                 nvidia,pins = "dap2_sclk_pa3";
2862                 nvidia,function = "i2s1";
2863                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
2864                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
2865                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
2866         };
2867         dap2_din_pa4 {
2868                 nvidia,pins = "dap2_din_pa4";
2869                 nvidia,function = "i2s1";
2870                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
2871                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
2872                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
2873         };
2874         dap2_dout_pa5 {
2875                 nvidia,pins = "dap2_dout_pa5";
2876                 nvidia,function = "i2s1";
2877                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
2878                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
2879                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
2880         };
2881         sdmmc3_clk_pa6 {
2882                 nvidia,pins = "sdmmc3_clk_pa6";
2883                 nvidia,function = "sdmmc3";
2884                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
2885                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
2886                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
2887         };
2888         sdmmc3_cmd_pa7 {
2889                 nvidia,pins = "sdmmc3_cmd_pa7";
2890                 nvidia,function = "sdmmc3";
2891                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
2892                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
2893                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
2894         };
2895         gmi_a17_pb0 {
2896                 nvidia,pins = "gmi_a17_pb0";
2897                 nvidia,function = "spi4";
2898                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
2899                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
2900                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
2901         };
2902         gmi_a18_pb1 {
2903                 nvidia,pins = "gmi_a18_pb1";
2904                 nvidia,function = "spi4";
2905                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
2906                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
2907                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
2908         };
2909         lcd_pwr0_pb2 {
2910                 nvidia,pins = "lcd_pwr0_pb2";
2911                 nvidia,function = "displaya";
2912                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
2913                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
2914                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
2915         };
2916         lcd_pclk_pb3 {
2917                 nvidia,pins = "lcd_pclk_pb3";
2918                 nvidia,function = "displaya";
2919                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
2920                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
2921                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
2922         };
2923         sdmmc3_dat3_pb4 {
2924                 nvidia,pins = "sdmmc3_dat3_pb4";
2925                 nvidia,function = "sdmmc3";
2926                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
2927                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
2928                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
2929         };
2930         sdmmc3_dat2_pb5 {
2931                 nvidia,pins = "sdmmc3_dat2_pb5";
2932                 nvidia,function = "sdmmc3";
2933                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
2934                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
2935                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
2936         };
2937         sdmmc3_dat1_pb6 {
2938                 nvidia,pins = "sdmmc3_dat1_pb6";
2939                 nvidia,function = "sdmmc3";
2940                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
2941                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
2942                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
2943         };
2944         sdmmc3_dat0_pb7 {
2945                 nvidia,pins = "sdmmc3_dat0_pb7";
2946                 nvidia,function = "sdmmc3";
2947                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
2948                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
2949                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
2950         };
2951         uart3_rts_n_pc0 {
2952                 nvidia,pins = "uart3_rts_n_pc0";
2953                 nvidia,function = "uartc";
2954                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
2955                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
2956                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
2957         };
2958         lcd_pwr1_pc1 {
2959                 nvidia,pins = "lcd_pwr1_pc1";
2960                 nvidia,function = "displaya";
2961                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
2962                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
2963                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
2964         };
2965         uart2_txd_pc2 {
2966                 nvidia,pins = "uart2_txd_pc2";
2967                 nvidia,function = "uartb";
2968                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
2969                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
2970                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
2971         };
2972         uart2_rxd_pc3 {
2973                 nvidia,pins = "uart2_rxd_pc3";
2974                 nvidia,function = "uartb";
2975                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
2976                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
2977                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
2978         };
2979         gen1_i2c_scl_pc4 {
2980                 nvidia,pins = "gen1_i2c_scl_pc4";
2981                 nvidia,function = "i2c1";
2982                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
2983                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
2984                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
2985                 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
2986         };
2987         gen1_i2c_sda_pc5 {
2988                 nvidia,pins = "gen1_i2c_sda_pc5";
2989                 nvidia,function = "i2c1";
2990                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
2991                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
2992                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
2993                 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
2994         };
2995         lcd_pwr2_pc6 {
2996                 nvidia,pins = "lcd_pwr2_pc6";
2997                 nvidia,function = "displaya";
2998                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
2999                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3000                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3001         };
3002         gmi_wp_n_pc7 {
3003                 nvidia,pins = "gmi_wp_n_pc7";
3004                 nvidia,function = "gmi";
3005                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3006                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
3007                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
3008         };
3009         sdmmc3_dat5_pd0 {
3010                 nvidia,pins = "sdmmc3_dat5_pd0";
3011                 nvidia,function = "sdmmc3";
3012                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
3013                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
3014                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3015         };
3016         sdmmc3_dat4_pd1 {
3017                 nvidia,pins = "sdmmc3_dat4_pd1";
3018                 nvidia,function = "sdmmc3";
3019                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
3020                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
3021                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
3022         };
3023         lcd_dc1_pd2 {
3024                 nvidia,pins = "lcd_dc1_pd2";
3025                 nvidia,function = "displaya";
3026                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3027                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3028                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3029         };
3030         sdmmc3_dat6_pd3 {
3031                 nvidia,pins = "sdmmc3_dat6_pd3";
3032                 nvidia,function = "spi4";
3033                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3034                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
3035                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3036         };
3037         sdmmc3_dat7_pd4 {
3038                 nvidia,pins = "sdmmc3_dat7_pd4";
3039                 nvidia,function = "spi4";
3040                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3041                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
3042                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3043         };
3044         vi_d1_pd5 {
3045                 nvidia,pins = "vi_d1_pd5";
3046                 nvidia,function = "sdmmc2";
3047                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3048                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
3049                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
3050         };
3051         vi_vsync_pd6 {
3052                 nvidia,pins = "vi_vsync_pd6";
3053                 nvidia,function = "ddr";
3054                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3055                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
3056                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
3057         };
3058         vi_hsync_pd7 {
3059                 nvidia,pins = "vi_hsync_pd7";
3060                 nvidia,function = "ddr";
3061                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3062                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
3063                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
3064         };
3065         lcd_d0_pe0 {
3066                 nvidia,pins = "lcd_d0_pe0";
3067                 nvidia,function = "displaya";
3068                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3069                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3070                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3071         };
3072         lcd_d1_pe1 {
3073                 nvidia,pins = "lcd_d1_pe1";
3074                 nvidia,function = "displaya";
3075                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3076                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3077                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3078         };
3079         lcd_d2_pe2 {
3080                 nvidia,pins = "lcd_d2_pe2";
3081                 nvidia,function = "displaya";
3082                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3083                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3084                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3085         };
3086         lcd_d3_pe3 {
3087                 nvidia,pins = "lcd_d3_pe3";
3088                 nvidia,function = "displaya";
3089                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3090                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3091                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3092         };
3093         lcd_d4_pe4 {
3094                 nvidia,pins = "lcd_d4_pe4";
3095                 nvidia,function = "displaya";
3096                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3097                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3098                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3099         };
3100         lcd_d5_pe5 {
3101                 nvidia,pins = "lcd_d5_pe5";
3102                 nvidia,function = "displaya";
3103                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3104                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3105                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3106         };
3107         lcd_d6_pe6 {
3108                 nvidia,pins = "lcd_d6_pe6";
3109                 nvidia,function = "displaya";
3110                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3111                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3112                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3113         };
3114         lcd_d7_pe7 {
3115                 nvidia,pins = "lcd_d7_pe7";
3116                 nvidia,function = "displaya";
3117                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3118                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3119                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3120         };
3121         lcd_d8_pf0 {
3122                 nvidia,pins = "lcd_d8_pf0";
3123                 nvidia,function = "displaya";
3124                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3125                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3126                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3127         };
3128         lcd_d9_pf1 {
3129                 nvidia,pins = "lcd_d9_pf1";
3130                 nvidia,function = "displaya";
3131                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3132                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3133                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3134         };
3135         lcd_d10_pf2 {
3136                 nvidia,pins = "lcd_d10_pf2";
3137                 nvidia,function = "displaya";
3138                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3139                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3140                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3141         };
3142         lcd_d11_pf3 {
3143                 nvidia,pins = "lcd_d11_pf3";
3144                 nvidia,function = "displaya";
3145                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3146                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3147                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3148         };
3149         lcd_d12_pf4 {
3150                 nvidia,pins = "lcd_d12_pf4";
3151                 nvidia,function = "displaya";
3152                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3153                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3154                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3155         };
3156         lcd_d13_pf5 {
3157                 nvidia,pins = "lcd_d13_pf5";
3158                 nvidia,function = "displaya";
3159                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3160                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3161                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3162         };
3163         lcd_d14_pf6 {
3164                 nvidia,pins = "lcd_d14_pf6";
3165                 nvidia,function = "displaya";
3166                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3167                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3168                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3169         };
3170         lcd_d15_pf7 {
3171                 nvidia,pins = "lcd_d15_pf7";
3172                 nvidia,function = "displaya";
3173                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3174                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3175                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3176         };
3177         gmi_ad0_pg0 {
3178                 nvidia,pins = "gmi_ad0_pg0";
3179                 nvidia,function = "nand";
3180                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3181                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
3182                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
3183         };
3184         gmi_ad1_pg1 {
3185                 nvidia,pins = "gmi_ad1_pg1";
3186                 nvidia,function = "nand";
3187                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3188                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3189                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3190         };
3191         gmi_ad2_pg2 {
3192                 nvidia,pins = "gmi_ad2_pg2";
3193                 nvidia,function = "nand";
3194                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3195                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
3196                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
3197         };
3198         gmi_ad3_pg3 {
3199                 nvidia,pins = "gmi_ad3_pg3";
3200                 nvidia,function = "nand";
3201                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3202                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
3203                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
3204         };
3205         gmi_ad4_pg4 {
3206                 nvidia,pins = "gmi_ad4_pg4";
3207                 nvidia,function = "nand";
3208                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3209                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
3210                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
3211         };
3212         gmi_ad5_pg5 {
3213                 nvidia,pins = "gmi_ad5_pg5";
3214                 nvidia,function = "nand";
3215                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3216                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
3217                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
3218         };
3219         gmi_ad6_pg6 {
3220                 nvidia,pins = "gmi_ad6_pg6";
3221                 nvidia,function = "nand";
3222                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3223                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
3224                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
3225         };
3226         gmi_ad7_pg7 {
3227                 nvidia,pins = "gmi_ad7_pg7";
3228                 nvidia,function = "nand";
3229                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3230                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
3231                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
3232         };
3233         gmi_ad8_ph0 {
3234                 nvidia,pins = "gmi_ad8_ph0";
3235                 nvidia,function = "pwm0";
3236                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3237                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3238                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3239         };
3240         gmi_ad9_ph1 {
3241                 nvidia,pins = "gmi_ad9_ph1";
3242                 nvidia,function = "pwm1";
3243                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3244                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3245                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3246         };
3247         gmi_ad10_ph2 {
3248                 nvidia,pins = "gmi_ad10_ph2";
3249                 nvidia,function = "pwm2";
3250                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3251                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
3252                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3253         };
3254         gmi_ad11_ph3 {
3255                 nvidia,pins = "gmi_ad11_ph3";
3256                 nvidia,function = "nand";
3257                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3258                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3259                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3260         };
3261         gmi_ad12_ph4 {
3262                 nvidia,pins = "gmi_ad12_ph4";
3263                 nvidia,function = "nand";
3264                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3265                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3266                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3267         };
3268         gmi_ad13_ph5 {
3269                 nvidia,pins = "gmi_ad13_ph5";
3270                 nvidia,function = "nand";
3271                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3272                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3273                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3274         };
3275         gmi_ad14_ph6 {
3276                 nvidia,pins = "gmi_ad14_ph6";
3277                 nvidia,function = "nand";
3278                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3279                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3280                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3281         };
3282         gmi_wr_n_pi0 {
3283                 nvidia,pins = "gmi_wr_n_pi0";
3284                 nvidia,function = "nand";
3285                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3286                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3287                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3288         };
3289         gmi_oe_n_pi1 {
3290                 nvidia,pins = "gmi_oe_n_pi1";
3291                 nvidia,function = "nand";
3292                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3293                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3294                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3295         };
3296         gmi_dqs_pi2 {
3297                 nvidia,pins = "gmi_dqs_pi2";
3298                 nvidia,function = "nand";
3299                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3300                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3301                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3302         };
3303         gmi_iordy_pi5 {
3304                 nvidia,pins = "gmi_iordy_pi5";
3305                 nvidia,function = "rsvd1";
3306                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3307                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3308                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3309         };
3310         gmi_cs7_n_pi6 {
3311                 nvidia,pins = "gmi_cs7_n_pi6";
3312                 nvidia,function = "nand";
3313                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3314                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3315                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3316         };
3317         gmi_wait_pi7 {
3318                 nvidia,pins = "gmi_wait_pi7";
3319                 nvidia,function = "nand";
3320                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3321                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3322                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3323         };
3324         lcd_de_pj1 {
3325                 nvidia,pins = "lcd_de_pj1";
3326                 nvidia,function = "displaya";
3327                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3328                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3329                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3330         };
3331         gmi_cs1_n_pj2 {
3332                 nvidia,pins = "gmi_cs1_n_pj2";
3333                 nvidia,function = "rsvd1";
3334                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3335                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
3336                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3337         };
3338         lcd_hsync_pj3 {
3339                 nvidia,pins = "lcd_hsync_pj3";
3340                 nvidia,function = "displaya";
3341                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3342                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3343                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3344         };
3345         lcd_vsync_pj4 {
3346                 nvidia,pins = "lcd_vsync_pj4";
3347                 nvidia,function = "displaya";
3348                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3349                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3350                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3351         };
3352         uart2_cts_n_pj5 {
3353                 nvidia,pins = "uart2_cts_n_pj5";
3354                 nvidia,function = "uartb";
3355                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
3356                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3357                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3358         };
3359         uart2_rts_n_pj6 {
3360                 nvidia,pins = "uart2_rts_n_pj6";
3361                 nvidia,function = "uartb";
3362                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3363                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3364                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3365         };
3366         gmi_a16_pj7 {
3367                 nvidia,pins = "gmi_a16_pj7";
3368                 nvidia,function = "spi4";
3369                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3370                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3371                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3372         };
3373         gmi_adv_n_pk0 {
3374                 nvidia,pins = "gmi_adv_n_pk0";
3375                 nvidia,function = "nand";
3376                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3377                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3378                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3379         };
3380         gmi_clk_pk1 {
3381                 nvidia,pins = "gmi_clk_pk1";
3382                 nvidia,function = "nand";
3383                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3384                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3385                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3386         };
3387         gmi_cs2_n_pk3 {
3388                 nvidia,pins = "gmi_cs2_n_pk3";
3389                 nvidia,function = "rsvd1";
3390                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3391                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3392                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3393         };
3394         gmi_cs3_n_pk4 {
3395                 nvidia,pins = "gmi_cs3_n_pk4";
3396                 nvidia,function = "nand";
3397                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3398                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3399                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3400         };
3401         spdif_out_pk5 {
3402                 nvidia,pins = "spdif_out_pk5";
3403                 nvidia,function = "spdif";
3404                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3405                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
3406                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3407         };
3408         spdif_in_pk6 {
3409                 nvidia,pins = "spdif_in_pk6";
3410                 nvidia,function = "spdif";
3411                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3412                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
3413                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
3414         };
3415         gmi_a19_pk7 {
3416                 nvidia,pins = "gmi_a19_pk7";
3417                 nvidia,function = "spi4";
3418                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3419                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3420                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3421         };
3422         vi_d2_pl0 {
3423                 nvidia,pins = "vi_d2_pl0";
3424                 nvidia,function = "sdmmc2";
3425                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3426                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3427                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3428         };
3429         vi_d3_pl1 {
3430                 nvidia,pins = "vi_d3_pl1";
3431                 nvidia,function = "sdmmc2";
3432                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3433                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3434                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3435         };
3436         vi_d4_pl2 {
3437                 nvidia,pins = "vi_d4_pl2";
3438                 nvidia,function = "vi";
3439                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3440                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3441                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3442         };
3443         vi_d5_pl3 {
3444                 nvidia,pins = "vi_d5_pl3";
3445                 nvidia,function = "sdmmc2";
3446                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3447                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3448                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3449         };
3450         vi_d6_pl4 {
3451                 nvidia,pins = "vi_d6_pl4";
3452                 nvidia,function = "vi";
3453                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3454                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
3455                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3456         };
3457         vi_d7_pl5 {
3458                 nvidia,pins = "vi_d7_pl5";
3459                 nvidia,function = "sdmmc2";
3460                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3461                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3462                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3463         };
3464         vi_d8_pl6 {
3465                 nvidia,pins = "vi_d8_pl6";
3466                 nvidia,function = "sdmmc2";
3467                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3468                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
3469                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3470         };
3471         vi_d9_pl7 {
3472                 nvidia,pins = "vi_d9_pl7";
3473                 nvidia,function = "sdmmc2";
3474                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3475                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3476                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3477         };
3478         lcd_d16_pm0 {
3479                 nvidia,pins = "lcd_d16_pm0";
3480                 nvidia,function = "displaya";
3481                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3482                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3483                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3484         };
3485         lcd_d17_pm1 {
3486                 nvidia,pins = "lcd_d17_pm1";
3487                 nvidia,function = "displaya";
3488                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3489                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3490                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3491         };
3492         lcd_d18_pm2 {
3493                 nvidia,pins = "lcd_d18_pm2";
3494                 nvidia,function = "displaya";
3495                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3496                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3497                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3498         };
3499         lcd_d19_pm3 {
3500                 nvidia,pins = "lcd_d19_pm3";
3501                 nvidia,function = "displaya";
3502                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3503                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3504                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3505         };
3506         lcd_d20_pm4 {
3507                 nvidia,pins = "lcd_d20_pm4";
3508                 nvidia,function = "displaya";
3509                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3510                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3511                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3512         };
3513         lcd_d21_pm5 {
3514                 nvidia,pins = "lcd_d21_pm5";
3515                 nvidia,function = "displaya";
3516                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3517                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3518                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3519         };
3520         lcd_d22_pm6 {
3521                 nvidia,pins = "lcd_d22_pm6";
3522                 nvidia,function = "displaya";
3523                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3524                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3525                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3526         };
3527         lcd_d23_pm7 {
3528                 nvidia,pins = "lcd_d23_pm7";
3529                 nvidia,function = "displaya";
3530                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3531                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3532                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3533         };
3534         dap1_fs_pn0 {
3535                 nvidia,pins = "dap1_fs_pn0";
3536                 nvidia,function = "i2s0";
3537                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3538                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
3539                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
3540         };
3541         dap1_din_pn1 {
3542                 nvidia,pins = "dap1_din_pn1";
3543                 nvidia,function = "i2s0";
3544                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3545                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
3546                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
3547         };
3548         dap1_dout_pn2 {
3549                 nvidia,pins = "dap1_dout_pn2";
3550                 nvidia,function = "i2s0";
3551                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3552                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
3553                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
3554         };
3555         dap1_sclk_pn3 {
3556                 nvidia,pins = "dap1_sclk_pn3";
3557                 nvidia,function = "i2s0";
3558                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3559                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
3560                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
3561         };
3562         lcd_cs0_n_pn4 {
3563                 nvidia,pins = "lcd_cs0_n_pn4";
3564                 nvidia,function = "displaya";
3565                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3566                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3567                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3568         };
3569         lcd_sdout_pn5 {
3570                 nvidia,pins = "lcd_sdout_pn5";
3571                 nvidia,function = "displaya";
3572                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3573                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3574                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3575         };
3576         lcd_dc0_pn6 {
3577                 nvidia,pins = "lcd_dc0_pn6";
3578                 nvidia,function = "displaya";
3579                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3580                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3581                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3582         };
3583         hdmi_int_pn7 {
3584                 nvidia,pins = "hdmi_int_pn7";
3585                 nvidia,function = "hdmi";
3586                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3587                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3588                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
3589         };
3590         ulpi_data7_po0 {
3591                 nvidia,pins = "ulpi_data7_po0";
3592                 nvidia,function = "uarta";
3593                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
3594                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3595                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3596         };
3597         ulpi_data0_po1 {
3598                 nvidia,pins = "ulpi_data0_po1";
3599                 nvidia,function = "uarta";
3600                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3601                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3602                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3603         };
3604         ulpi_data1_po2 {
3605                 nvidia,pins = "ulpi_data1_po2";
3606                 nvidia,function = "uarta";
3607                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3608                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3609                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3610         };
3611         ulpi_data2_po3 {
3612                 nvidia,pins = "ulpi_data2_po3";
3613                 nvidia,function = "uarta";
3614                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3615                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3616                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3617         };
3618         ulpi_data3_po4 {
3619                 nvidia,pins = "ulpi_data3_po4";
3620                 nvidia,function = "uarta";
3621                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3622                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
3623                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
3624         };
3625         ulpi_data4_po5 {
3626                 nvidia,pins = "ulpi_data4_po5";
3627                 nvidia,function = "uarta";
3628                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3629                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3630                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3631         };
3632         ulpi_data5_po6 {
3633                 nvidia,pins = "ulpi_data5_po6";
3634                 nvidia,function = "uarta";
3635                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3636                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3637                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3638         };
3639         ulpi_data6_po7 {
3640                 nvidia,pins = "ulpi_data6_po7";
3641                 nvidia,function = "uarta";
3642                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3643                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3644                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3645         };
3646         dap3_fs_pp0 {
3647                 nvidia,pins = "dap3_fs_pp0";
3648                 nvidia,function = "i2s2";
3649                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3650                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
3651                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
3652         };
3653         dap3_din_pp1 {
3654                 nvidia,pins = "dap3_din_pp1";
3655                 nvidia,function = "i2s2";
3656                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3657                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
3658                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
3659         };
3660         dap3_dout_pp2 {
3661                 nvidia,pins = "dap3_dout_pp2";
3662                 nvidia,function = "i2s2";
3663                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3664                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
3665                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
3666         };
3667         dap3_sclk_pp3 {
3668                 nvidia,pins = "dap3_sclk_pp3";
3669                 nvidia,function = "i2s2";
3670                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3671                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
3672                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
3673         };
3674         dap4_fs_pp4 {
3675                 nvidia,pins = "dap4_fs_pp4";
3676                 nvidia,function = "i2s3";
3677                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3678                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
3679                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
3680         };
3681         dap4_din_pp5 {
3682                 nvidia,pins = "dap4_din_pp5";
3683                 nvidia,function = "i2s3";
3684                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3685                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
3686                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
3687         };
3688         dap4_dout_pp6 {
3689                 nvidia,pins = "dap4_dout_pp6";
3690                 nvidia,function = "i2s3";
3691                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3692                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
3693                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
3694         };
3695         dap4_sclk_pp7 {
3696                 nvidia,pins = "dap4_sclk_pp7";
3697                 nvidia,function = "i2s3";
3698                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3699                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
3700                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
3701         };
3702         kb_col0_pq0 {
3703                 nvidia,pins = "kb_col0_pq0";
3704                 nvidia,function = "kbc";
3705                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3706                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3707                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3708         };
3709         kb_col1_pq1 {
3710                 nvidia,pins = "kb_col1_pq1";
3711                 nvidia,function = "kbc";
3712                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3713                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3714                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3715         };
3716         kb_col2_pq2 {
3717                 nvidia,pins = "kb_col2_pq2";
3718                 nvidia,function = "kbc";
3719                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3720                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3721                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3722         };
3723         kb_col3_pq3 {
3724                 nvidia,pins = "kb_col3_pq3";
3725                 nvidia,function = "kbc";
3726                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3727                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3728                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3729         };
3730         kb_col4_pq4 {
3731                 nvidia,pins = "kb_col4_pq4";
3732                 nvidia,function = "kbc";
3733                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3734                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3735                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3736         };
3737         kb_col5_pq5 {
3738                 nvidia,pins = "kb_col5_pq5";
3739                 nvidia,function = "kbc";
3740                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3741                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3742                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3743         };
3744         kb_col6_pq6 {
3745                 nvidia,pins = "kb_col6_pq6";
3746                 nvidia,function = "kbc";
3747                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3748                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3749                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3750         };
3751         kb_col7_pq7 {
3752                 nvidia,pins = "kb_col7_pq7";
3753                 nvidia,function = "kbc";
3754                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3755                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3756                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3757         };
3758         kb_row0_pr0 {
3759                 nvidia,pins = "kb_row0_pr0";
3760                 nvidia,function = "kbc";
3761                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3762                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3763                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3764         };
3765         kb_row1_pr1 {
3766                 nvidia,pins = "kb_row1_pr1";
3767                 nvidia,function = "kbc";
3768                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3769                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3770                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3771         };
3772         kb_row2_pr2 {
3773                 nvidia,pins = "kb_row2_pr2";
3774                 nvidia,function = "kbc";
3775                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3776                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3777                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3778         };
3779         kb_row3_pr3 {
3780                 nvidia,pins = "kb_row3_pr3";
3781                 nvidia,function = "kbc";
3782                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3783                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3784                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3785         };
3786         kb_row4_pr4 {
3787                 nvidia,pins = "kb_row4_pr4";
3788                 nvidia,function = "kbc";
3789                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3790                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3791                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3792         };
3793         kb_row5_pr5 {
3794                 nvidia,pins = "kb_row5_pr5";
3795                 nvidia,function = "kbc";
3796                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3797                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3798                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3799         };
3800         kb_row6_pr6 {
3801                 nvidia,pins = "kb_row6_pr6";
3802                 nvidia,function = "kbc";
3803                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3804                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3805                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3806         };
3807         kb_row7_pr7 {
3808                 nvidia,pins = "kb_row7_pr7";
3809                 nvidia,function = "kbc";
3810                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3811                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
3812                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
3813         };
3814         kb_row8_ps0 {
3815                 nvidia,pins = "kb_row8_ps0";
3816                 nvidia,function = "kbc";
3817                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3818                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3819                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3820         };
3821         kb_row9_ps1 {
3822                 nvidia,pins = "kb_row9_ps1";
3823                 nvidia,function = "kbc";
3824                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3825                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3826                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3827         };
3828         kb_row10_ps2 {
3829                 nvidia,pins = "kb_row10_ps2";
3830                 nvidia,function = "kbc";
3831                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3832                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3833                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3834         };
3835         kb_row11_ps3 {
3836                 nvidia,pins = "kb_row11_ps3";
3837                 nvidia,function = "kbc";
3838                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3839                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3840                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3841         };
3842         kb_row12_ps4 {
3843                 nvidia,pins = "kb_row12_ps4";
3844                 nvidia,function = "kbc";
3845                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3846                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3847                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3848         };
3849         kb_row13_ps5 {
3850                 nvidia,pins = "kb_row13_ps5";
3851                 nvidia,function = "kbc";
3852                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3853                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3854                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3855         };
3856         kb_row14_ps6 {
3857                 nvidia,pins = "kb_row14_ps6";
3858                 nvidia,function = "kbc";
3859                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3860                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3861                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3862         };
3863         kb_row15_ps7 {
3864                 nvidia,pins = "kb_row15_ps7";
3865                 nvidia,function = "kbc";
3866                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3867                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3868                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3869         };
3870         vi_pclk_pt0 {
3871                 nvidia,pins = "vi_pclk_pt0";
3872                 nvidia,function = "rsvd1";
3873                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
3874                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
3875                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3876         };
3877         vi_mclk_pt1 {
3878                 nvidia,pins = "vi_mclk_pt1";
3879                 nvidia,function = "vi";
3880                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3881                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3882                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3883         };
3884         vi_d10_pt2 {
3885                 nvidia,pins = "vi_d10_pt2";
3886                 nvidia,function = "ddr";
3887                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3888                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
3889                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
3890         };
3891         vi_d11_pt3 {
3892                 nvidia,pins = "vi_d11_pt3";
3893                 nvidia,function = "ddr";
3894                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
3895                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
3896                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
3897         };
3898         vi_d0_pt4 {
3899                 nvidia,pins = "vi_d0_pt4";
3900                 nvidia,function = "ddr";
3901                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3902                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
3903                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
3904         };
3905         gen2_i2c_scl_pt5 {
3906                 nvidia,pins = "gen2_i2c_scl_pt5";
3907                 nvidia,function = "i2c2";
3908                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3909                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3910                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3911                 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
3912         };
3913         gen2_i2c_sda_pt6 {
3914                 nvidia,pins = "gen2_i2c_sda_pt6";
3915                 nvidia,function = "i2c2";
3916                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3917                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3918                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3919                 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
3920         };
3921         sdmmc4_cmd_pt7 {
3922                 nvidia,pins = "sdmmc4_cmd_pt7";
3923                 nvidia,function = "sdmmc4";
3924                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
3925                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
3926                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
3927                 nvidia,io-reset = <TEGRA_PIN_DISABLE>;
3928         };
3929         pu0 {
3930                 nvidia,pins = "pu0";
3931                 nvidia,function = "owr";
3932                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3933                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
3934                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3935         };
3936         pu1 {
3937                 nvidia,pins = "pu1";
3938                 nvidia,function = "rsvd1";
3939                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3940                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
3941                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3942         };
3943         pu2 {
3944                 nvidia,pins = "pu2";
3945                 nvidia,function = "rsvd1";
3946                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3947                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3948                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3949         };
3950         pu3 {
3951                 nvidia,pins = "pu3";
3952                 nvidia,function = "pwm0";
3953                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3954                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3955                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3956         };
3957         pu4 {
3958                 nvidia,pins = "pu4";
3959                 nvidia,function = "pwm1";
3960                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3961                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3962                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3963         };
3964         pu5 {
3965                 nvidia,pins = "pu5";
3966                 nvidia,function = "rsvd4";
3967                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3968                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3969                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3970         };
3971         pu6 {
3972                 nvidia,pins = "pu6";
3973                 nvidia,function = "pwm3";
3974                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3975                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
3976                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
3977         };
3978         jtag_rtck_pu7 {
3979                 nvidia,pins = "jtag_rtck_pu7";
3980                 nvidia,function = "rtck";
3981                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3982                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
3983                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3984         };
3985         pv0 {
3986                 nvidia,pins = "pv0";
3987                 nvidia,function = "rsvd1";
3988                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
3989                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
3990                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
3991         };
3992         pv1 {
3993                 nvidia,pins = "pv1";
3994                 nvidia,function = "rsvd1";
3995                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3996                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3997                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3998         };
3999         pv2 {
4000                 nvidia,pins = "pv2";
4001                 nvidia,function = "owr";
4002                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
4003                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
4004                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
4005         };
4006         pv3 {
4007                 nvidia,pins = "pv3";
4008                 nvidia,function = "clk_12m_out";
4009                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
4010                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
4011                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
4012         };
4013         ddc_scl_pv4 {
4014                 nvidia,pins = "ddc_scl_pv4";
4015                 nvidia,function = "i2c4";
4016                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
4017                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
4018                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
4019         };
4020         ddc_sda_pv5 {
4021                 nvidia,pins = "ddc_sda_pv5";
4022                 nvidia,function = "i2c4";
4023                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
4024                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
4025                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
4026         };
4027         crt_hsync_pv6 {
4028                 nvidia,pins = "crt_hsync_pv6";
4029                 nvidia,function = "crt";
4030                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
4031                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
4032                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
4033         };
4034         crt_vsync_pv7 {
4035                 nvidia,pins = "crt_vsync_pv7";
4036                 nvidia,function = "crt";
4037                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
4038                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
4039                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
4040         };
4041         lcd_cs1_n_pw0 {
4042                 nvidia,pins = "lcd_cs1_n_pw0";
4043                 nvidia,function = "displaya";
4044                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
4045                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
4046                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
4047         };
4048         lcd_m1_pw1 {
4049                 nvidia,pins = "lcd_m1_pw1";
4050                 nvidia,function = "displaya";
4051                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
4052                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
4053                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
4054         };
4055         spi2_cs1_n_pw2 {
4056                 nvidia,pins = "spi2_cs1_n_pw2";
4057                 nvidia,function = "spi2";
4058                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
4059                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
4060                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
4061         };
4062         clk1_out_pw4 {
4063                 nvidia,pins = "clk1_out_pw4";
4064                 nvidia,function = "extperiph1";
4065                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
4066                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
4067                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
4068         };
4069         clk2_out_pw5 {
4070                 nvidia,pins = "clk2_out_pw5";
4071                 nvidia,function = "extperiph2";
4072                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
4073                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
4074                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
4075         };
4076         uart3_txd_pw6 {
4077                 nvidia,pins = "uart3_txd_pw6";
4078                 nvidia,function = "uartc";
4079                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
4080                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
4081                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
4082         };
4083         uart3_rxd_pw7 {
4084                 nvidia,pins = "uart3_rxd_pw7";
4085                 nvidia,function = "uartc";
4086                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
4087                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
4088                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
4089         };
4090         spi2_sck_px2 {
4091                 nvidia,pins = "spi2_sck_px2";
4092                 nvidia,function = "gmi";
4093                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
4094                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
4095                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
4096         };
4097         spi1_mosi_px4 {
4098                 nvidia,pins = "spi1_mosi_px4";
4099                 nvidia,function = "spi1";
4100                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
4101                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
4102                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
4103         };
4104         spi1_sck_px5 {
4105                 nvidia,pins = "spi1_sck_px5";
4106                 nvidia,function = "spi1";
4107                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
4108                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
4109                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
4110         };
4111         spi1_cs0_n_px6 {
4112                 nvidia,pins = "spi1_cs0_n_px6";
4113                 nvidia,function = "spi1";
4114                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
4115                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
4116                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
4117         };
4118         spi1_miso_px7 {
4119                 nvidia,pins = "spi1_miso_px7";
4120                 nvidia,function = "spi1";
4121                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
4122                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
4123                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
4124         };
4125         ulpi_clk_py0 {
4126                 nvidia,pins = "ulpi_clk_py0";
4127                 nvidia,function = "uartd";
4128                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
4129                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
4130                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
4131         };
4132         ulpi_dir_py1 {
4133                 nvidia,pins = "ulpi_dir_py1";
4134                 nvidia,function = "uartd";
4135                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
4136                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
4137                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
4138         };
4139         ulpi_nxt_py2 {
4140                 nvidia,pins = "ulpi_nxt_py2";
4141                 nvidia,function = "uartd";
4142                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
4143                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
4144                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
4145         };
4146         ulpi_stp_py3 {
4147                 nvidia,pins = "ulpi_stp_py3";
4148                 nvidia,function = "uartd";
4149                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
4150                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
4151                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
4152         };
4153         sdmmc1_dat3_py4 {
4154                 nvidia,pins = "sdmmc1_dat3_py4";
4155                 nvidia,function = "sdmmc1";
4156                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
4157                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
4158                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
4159         };
4160         sdmmc1_dat2_py5 {
4161                 nvidia,pins = "sdmmc1_dat2_py5";
4162                 nvidia,function = "sdmmc1";
4163                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
4164                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
4165                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
4166         };
4167         sdmmc1_dat1_py6 {
4168                 nvidia,pins = "sdmmc1_dat1_py6";
4169                 nvidia,function = "sdmmc1";
4170                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
4171                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
4172                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
4173         };
4174         sdmmc1_dat0_py7 {
4175                 nvidia,pins = "sdmmc1_dat0_py7";
4176                 nvidia,function = "sdmmc1";
4177                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
4178                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
4179                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
4180         };
4181         sdmmc1_clk_pz0 {
4182                 nvidia,pins = "sdmmc1_clk_pz0";
4183                 nvidia,function = "sdmmc1";
4184                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
4185                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
4186                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
4187         };
4188         sdmmc1_cmd_pz1 {
4189                 nvidia,pins = "sdmmc1_cmd_pz1";
4190                 nvidia,function = "sdmmc1";
4191                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
4192                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
4193                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
4194         };
4195         lcd_sdin_pz2 {
4196                 nvidia,pins = "lcd_sdin_pz2";
4197                 nvidia,function = "displaya";
4198                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
4199                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
4200                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
4201         };
4202         lcd_wr_n_pz3 {
4203                 nvidia,pins = "lcd_wr_n_pz3";
4204                 nvidia,function = "displaya";
4205                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
4206                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
4207                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
4208         };
4209         lcd_sck_pz4 {
4210                 nvidia,pins = "lcd_sck_pz4";
4211                 nvidia,function = "displaya";
4212                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
4213                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
4214                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
4215         };
4216         sys_clk_req_pz5 {
4217                 nvidia,pins = "sys_clk_req_pz5";
4218                 nvidia,function = "sysclk";
4219                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
4220                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
4221                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
4222         };
4223         pwr_i2c_scl_pz6 {
4224                 nvidia,pins = "pwr_i2c_scl_pz6";
4225                 nvidia,function = "i2cpwr";
4226                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
4227                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
4228                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
4229                 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
4230         };
4231         pwr_i2c_sda_pz7 {
4232                 nvidia,pins = "pwr_i2c_sda_pz7";
4233                 nvidia,function = "i2cpwr";
4234                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
4235                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
4236                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
4237                 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
4238         };
4239         sdmmc4_dat0_paa0 {
4240                 nvidia,pins = "sdmmc4_dat0_paa0";
4241                 nvidia,function = "sdmmc4";
4242                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
4243                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
4244                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
4245                 nvidia,io-reset = <TEGRA_PIN_DISABLE>;
4246         };
4247         sdmmc4_dat1_paa1 {
4248                 nvidia,pins = "sdmmc4_dat1_paa1";
4249                 nvidia,function = "sdmmc4";
4250                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
4251                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
4252                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
4253                 nvidia,io-reset = <TEGRA_PIN_DISABLE>;
4254         };
4255         sdmmc4_dat2_paa2 {
4256                 nvidia,pins = "sdmmc4_dat2_paa2";
4257                 nvidia,function = "sdmmc4";
4258                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
4259                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
4260                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
4261                 nvidia,io-reset = <TEGRA_PIN_DISABLE>;
4262         };
4263         sdmmc4_dat3_paa3 {
4264                 nvidia,pins = "sdmmc4_dat3_paa3";
4265                 nvidia,function = "sdmmc4";
4266                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
4267                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
4268                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
4269                 nvidia,io-reset = <TEGRA_PIN_DISABLE>;
4270         };
4271         sdmmc4_dat4_paa4 {
4272                 nvidia,pins = "sdmmc4_dat4_paa4";
4273                 nvidia,function = "sdmmc4";
4274                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
4275                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
4276                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
4277                 nvidia,io-reset = <TEGRA_PIN_DISABLE>;
4278         };
4279         sdmmc4_dat5_paa5 {
4280                 nvidia,pins = "sdmmc4_dat5_paa5";
4281                 nvidia,function = "sdmmc4";
4282                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
4283                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
4284                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
4285                 nvidia,io-reset = <TEGRA_PIN_DISABLE>;
4286         };
4287         sdmmc4_dat6_paa6 {
4288                 nvidia,pins = "sdmmc4_dat6_paa6";
4289                 nvidia,function = "sdmmc4";
4290                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
4291                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
4292                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
4293                 nvidia,io-reset = <TEGRA_PIN_DISABLE>;
4294         };
4295         sdmmc4_dat7_paa7 {
4296                 nvidia,pins = "sdmmc4_dat7_paa7";
4297                 nvidia,function = "sdmmc4";
4298                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
4299                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
4300                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
4301                 nvidia,io-reset = <TEGRA_PIN_DISABLE>;
4302         };
4303         pbb0 {
4304                 nvidia,pins = "pbb0";
4305                 nvidia,function = "i2s4";
4306                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
4307                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
4308                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
4309         };
4310         cam_i2c_scl_pbb1 {
4311                 nvidia,pins = "cam_i2c_scl_pbb1";
4312                 nvidia,function = "i2c3";
4313                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
4314                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
4315                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
4316                 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
4317         };
4318         cam_i2c_sda_pbb2 {
4319                 nvidia,pins = "cam_i2c_sda_pbb2";
4320                 nvidia,function = "i2c3";
4321                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
4322                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
4323                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
4324                 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
4325         };
4326         pbb3 {
4327                 nvidia,pins = "pbb3";
4328                 nvidia,function = "vgp3";
4329                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
4330                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
4331                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
4332         };
4333         pbb4 {
4334                 nvidia,pins = "pbb4";
4335                 nvidia,function = "vgp4";
4336                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
4337                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
4338                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
4339         };
4340         pbb5 {
4341                 nvidia,pins = "pbb5";
4342                 nvidia,function = "vgp5";
4343                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
4344                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
4345                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
4346         };
4347         pbb6 {
4348                 nvidia,pins = "pbb6";
4349                 nvidia,function = "vgp6";
4350                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
4351                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
4352                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
4353         };
4354         pbb7 {
4355                 nvidia,pins = "pbb7";
4356                 nvidia,function = "i2s4";
4357                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
4358                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
4359                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
4360         };
4361         cam_mclk_pcc0 {
4362                 nvidia,pins = "cam_mclk_pcc0";
4363                 nvidia,function = "vi_alt3";
4364                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
4365                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
4366                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
4367         };
4368         pcc1 {
4369                 nvidia,pins = "pcc1";
4370                 nvidia,function = "i2s4";
4371                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
4372                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
4373                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
4374         };
4375         pcc2 {
4376                 nvidia,pins = "pcc2";
4377                 nvidia,function = "i2s4";
4378                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
4379                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
4380                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
4381         };
4382         sdmmc4_rst_n_pcc3 {
4383                 nvidia,pins = "sdmmc4_rst_n_pcc3";
4384                 nvidia,function = "sdmmc4";
4385                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
4386                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
4387                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
4388                 nvidia,io-reset = <TEGRA_PIN_DISABLE>;
4389         };
4390         sdmmc4_clk_pcc4 {
4391                 nvidia,pins = "sdmmc4_clk_pcc4";
4392                 nvidia,function = "sdmmc4";
4393                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
4394                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
4395                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
4396                 nvidia,io-reset = <TEGRA_PIN_DISABLE>;
4397         };
4398         clk2_req_pcc5 {
4399                 nvidia,pins = "clk2_req_pcc5";
4400                 nvidia,function = "dap";
4401                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
4402                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
4403                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
4404         };
4405         pex_l2_rst_n_pcc6 {
4406                 nvidia,pins = "pex_l2_rst_n_pcc6";
4407                 nvidia,function = "pcie";
4408                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
4409                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
4410                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
4411         };
4412         pex_l2_clkreq_n_pcc7 {
4413                 nvidia,pins = "pex_l2_clkreq_n_pcc7";
4414                 nvidia,function = "pcie";
4415                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
4416                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
4417                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
4418         };
4419         pex_l0_prsnt_n_pdd0 {
4420                 nvidia,pins = "pex_l0_prsnt_n_pdd0";
4421                 nvidia,function = "pcie";
4422                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
4423                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
4424                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
4425         };
4426         pex_l0_rst_n_pdd1 {
4427                 nvidia,pins = "pex_l0_rst_n_pdd1";
4428                 nvidia,function = "pcie";
4429                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
4430                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
4431                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
4432         };
4433         pex_l0_clkreq_n_pdd2 {
4434                 nvidia,pins = "pex_l0_clkreq_n_pdd2";
4435                 nvidia,function = "pcie";
4436                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
4437                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
4438                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
4439         };
4440         pex_wake_n_pdd3 {
4441                 nvidia,pins = "pex_wake_n_pdd3";
4442                 nvidia,function = "pcie";
4443                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
4444                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
4445                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
4446         };
4447         pex_l1_prsnt_n_pdd4 {
4448                 nvidia,pins = "pex_l1_prsnt_n_pdd4";
4449                 nvidia,function = "pcie";
4450                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
4451                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
4452                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
4453         };
4454         pex_l1_rst_n_pdd5 {
4455                 nvidia,pins = "pex_l1_rst_n_pdd5";
4456                 nvidia,function = "pcie";
4457                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
4458                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
4459                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
4460         };
4461         pex_l1_clkreq_n_pdd6 {
4462                 nvidia,pins = "pex_l1_clkreq_n_pdd6";
4463                 nvidia,function = "pcie";
4464                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
4465                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
4466                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
4467         };
4468         pex_l2_prsnt_n_pdd7 {
4469                 nvidia,pins = "pex_l2_prsnt_n_pdd7";
4470                 nvidia,function = "pcie";
4471                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
4472                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
4473                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
4474         };
4475         clk3_out_pee0 {
4476                 nvidia,pins = "clk3_out_pee0";
4477                 nvidia,function = "extperiph3";
4478                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
4479                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
4480                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
4481         };
4482         clk3_req_pee1 {
4483                 nvidia,pins = "clk3_req_pee1";
4484                 nvidia,function = "dev3";
4485                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
4486                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
4487                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
4488         };
4489         clk1_req_pee2 {
4490                 nvidia,pins = "clk1_req_pee2";
4491                 nvidia,function = "dap";
4492                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
4493                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
4494                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
4495         };
4496         hdmi_cec_pee3 {
4497                 nvidia,pins = "hdmi_cec_pee3";
4498                 nvidia,function = "cec";
4499                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
4500                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
4501                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
4502                 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
4503         };
4504         owr {
4505                 nvidia,pins = "owr";
4506                 nvidia,function = "owr";
4507                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
4508                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
4509                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
4510         };
4511         drive_groups {
4512                 nvidia,pins = "drive_gma",
4513                               "drive_gmb",
4514                               "drive_gmc",
4515                               "drive_gmd";
4516                 nvidia,pull-down-strength = <9>;
4517                 nvidia,pull-up-strength = <9>;
4518                 nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOWEST>;
4519                 nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_SLOWEST>;
4520         };
4521 };
4522
4523 &emc_icc_dvfs_opp_table {
4524         /delete-node/ opp@900000000,1350;
4525 };
4526
4527 &emc_bw_dfs_opp_table {
4528         /delete-node/ opp@900000000;
4529 };