arch/arm/boot/dts/tegra20.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 #include <dt-bindings/clock/tegra20-car.h>
   3 #include <dt-bindings/gpio/tegra-gpio.h>
   4 #include <dt-bindings/memory/tegra20-mc.h>
   5 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
   6 #include <dt-bindings/interrupt-controller/arm-gic.h>
   7 #include <dt-bindings/soc/tegra-pmc.h>
   8
   9 / {
  10         compatible = "nvidia,tegra20";
  11         interrupt-parent = <&lic>;
  12         #address-cells = <1>;
  13         #size-cells = <1>;
  14
  15         memory@0 {
  16                 device_type = "memory";
  17                 reg = <0 0>;
  18         };
  19
  20         sram@40000000 {
  21                 compatible = "mmio-sram";
  22                 reg = <0x40000000 0x40000>;
  23                 #address-cells = <1>;
  24                 #size-cells = <1>;
  25                 ranges = <0 0x40000000 0x40000>;
  26
  27                 vde_pool: sram@400 {
  28                         reg = <0x400 0x3fc00>;
  29                         pool;
  30                 };
  31         };
  32
  33         host1x@50000000 {
  34                 compatible = "nvidia,tegra20-host1x";
  35                 reg = <0x50000000 0x00024000>;
  36                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
  37                              <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
  38                 interrupt-names = "syncpt", "host1x";
  39                 clocks = <&tegra_car TEGRA20_CLK_HOST1X>;
  40                 clock-names = "host1x";
  41                 resets = <&tegra_car 28>;
  42                 reset-names = "host1x";
  43
  44                 #address-cells = <1>;
  45                 #size-cells = <1>;
  46
  47                 ranges = <0x54000000 0x54000000 0x04000000>;
  48
  49                 mpe@54040000 {
  50                         compatible = "nvidia,tegra20-mpe";
  51                         reg = <0x54040000 0x00040000>;
  52                         interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
  53                         clocks = <&tegra_car TEGRA20_CLK_MPE>;
  54                         resets = <&tegra_car 60>;
  55                         reset-names = "mpe";
  56                 };
  57
  58                 vi@54080000 {
  59                         compatible = "nvidia,tegra20-vi";
  60                         reg = <0x54080000 0x00040000>;
  61                         interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
  62                         clocks = <&tegra_car TEGRA20_CLK_VI>;
  63                         resets = <&tegra_car 20>;
  64                         reset-names = "vi";
  65                 };
  66
  67                 epp@540c0000 {
  68                         compatible = "nvidia,tegra20-epp";
  69                         reg = <0x540c0000 0x00040000>;
  70                         interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
  71                         clocks = <&tegra_car TEGRA20_CLK_EPP>;
  72                         resets = <&tegra_car 19>;
  73                         reset-names = "epp";
  74                 };
  75
  76                 isp@54100000 {
  77                         compatible = "nvidia,tegra20-isp";
  78                         reg = <0x54100000 0x00040000>;
  79                         interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
  80                         clocks = <&tegra_car TEGRA20_CLK_ISP>;
  81                         resets = <&tegra_car 23>;
  82                         reset-names = "isp";
  83                 };
  84
  85                 gr2d@54140000 {
  86                         compatible = "nvidia,tegra20-gr2d";
  87                         reg = <0x54140000 0x00040000>;
  88                         interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
  89                         clocks = <&tegra_car TEGRA20_CLK_GR2D>;
  90                         resets = <&tegra_car 21>;
  91                         reset-names = "2d";
  92                 };
  93
  94                 gr3d@54180000 {
  95                         compatible = "nvidia,tegra20-gr3d";
  96                         reg = <0x54180000 0x00040000>;
  97                         clocks = <&tegra_car TEGRA20_CLK_GR3D>;
  98                         resets = <&tegra_car 24>;
  99                         reset-names = "3d";
 100                 };
 101
 102                 dc@54200000 {
 103                         compatible = "nvidia,tegra20-dc";
 104                         reg = <0x54200000 0x00040000>;
 105                         interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 106                         clocks = <&tegra_car TEGRA20_CLK_DISP1>,
 107                                  <&tegra_car TEGRA20_CLK_PLL_P>;
 108                         clock-names = "dc", "parent";
 109                         resets = <&tegra_car 27>;
 110                         reset-names = "dc";
 111
 112                         nvidia,head = <0>;
 113
 114                         rgb {
 115                                 status = "disabled";
 116                         };
 117                 };
 118
 119                 dc@54240000 {
 120                         compatible = "nvidia,tegra20-dc";
 121                         reg = <0x54240000 0x00040000>;
 122                         interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 123                         clocks = <&tegra_car TEGRA20_CLK_DISP2>,
 124                                  <&tegra_car TEGRA20_CLK_PLL_P>;
 125                         clock-names = "dc", "parent";
 126                         resets = <&tegra_car 26>;
 127                         reset-names = "dc";
 128
 129                         nvidia,head = <1>;
 130
 131                         rgb {
 132                                 status = "disabled";
 133                         };
 134                 };
 135
 136                 hdmi@54280000 {
 137                         compatible = "nvidia,tegra20-hdmi";
 138                         reg = <0x54280000 0x00040000>;
 139                         interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 140                         clocks = <&tegra_car TEGRA20_CLK_HDMI>,
 141                                  <&tegra_car TEGRA20_CLK_PLL_D_OUT0>;
 142                         clock-names = "hdmi", "parent";
 143                         resets = <&tegra_car 51>;
 144                         reset-names = "hdmi";
 145                         status = "disabled";
 146                 };
 147
 148                 tvo@542c0000 {
 149                         compatible = "nvidia,tegra20-tvo";
 150                         reg = <0x542c0000 0x00040000>;
 151                         interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
 152                         clocks = <&tegra_car TEGRA20_CLK_TVO>;
 153                         status = "disabled";
 154                 };
 155
 156                 dsi@54300000 {
 157                         compatible = "nvidia,tegra20-dsi";
 158                         reg = <0x54300000 0x00040000>;
 159                         clocks = <&tegra_car TEGRA20_CLK_DSI>,
 160                                  <&tegra_car TEGRA20_CLK_PLL_D_OUT0>;
 161                         clock-names = "dsi", "parent";
 162                         resets = <&tegra_car 48>;
 163                         reset-names = "dsi";
 164                         status = "disabled";
 165                 };
 166         };
 167
 168         timer@50040600 {
 169                 compatible = "arm,cortex-a9-twd-timer";
 170                 interrupt-parent = <&intc>;
 171                 reg = <0x50040600 0x20>;
 172                 interrupts = <GIC_PPI 13
 173                         (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>;
 174                 clocks = <&tegra_car TEGRA20_CLK_TWD>;
 175         };
 176
 177         intc: interrupt-controller@50041000 {
 178                 compatible = "arm,cortex-a9-gic";
 179                 reg = <0x50041000 0x1000>,
 180                       <0x50040100 0x0100>;
 181                 interrupt-controller;
 182                 #interrupt-cells = <3>;
 183                 interrupt-parent = <&intc>;
 184         };
 185
 186         cache-controller@50043000 {
 187                 compatible = "arm,pl310-cache";
 188                 reg = <0x50043000 0x1000>;
 189                 arm,data-latency = <5 5 2>;
 190                 arm,tag-latency = <4 4 2>;
 191                 cache-unified;
 192                 cache-level = <2>;
 193         };
 194
 195         lic: interrupt-controller@60004000 {
 196                 compatible = "nvidia,tegra20-ictlr";
 197                 reg = <0x60004000 0x100>,
 198                       <0x60004100 0x50>,
 199                       <0x60004200 0x50>,
 200                       <0x60004300 0x50>;
 201                 interrupt-controller;
 202                 #interrupt-cells = <3>;
 203                 interrupt-parent = <&intc>;
 204         };
 205
 206         timer@60005000 {
 207                 compatible = "nvidia,tegra20-timer";
 208                 reg = <0x60005000 0x60>;
 209                 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 210                              <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
 211                              <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
 212                              <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
 213                 clocks = <&tegra_car TEGRA20_CLK_TIMER>;
 214         };
 215
 216         tegra_car: clock@60006000 {
 217                 compatible = "nvidia,tegra20-car";
 218                 reg = <0x60006000 0x1000>;
 219                 #clock-cells = <1>;
 220                 #reset-cells = <1>;
 221         };
 222
 223         flow-controller@60007000 {
 224                 compatible = "nvidia,tegra20-flowctrl";
 225                 reg = <0x60007000 0x1000>;
 226         };
 227
 228         apbdma: dma@6000a000 {
 229                 compatible = "nvidia,tegra20-apbdma";
 230                 reg = <0x6000a000 0x1200>;
 231                 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
 232                              <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
 233                              <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
 234                              <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
 235                              <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
 236                              <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
 237                              <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
 238                              <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
 239                              <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
 240                              <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
 241                              <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
 242                              <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
 243                              <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
 244                              <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
 245                              <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
 246                              <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
 247                 clocks = <&tegra_car TEGRA20_CLK_APBDMA>;
 248                 resets = <&tegra_car 34>;
 249                 reset-names = "dma";
 250                 #dma-cells = <1>;
 251         };
 252
 253         ahb@6000c000 {
 254                 compatible = "nvidia,tegra20-ahb";
 255                 reg = <0x6000c000 0x110>; /* AHB Arbitration + Gizmo Controller */
 256         };
 257
 258         gpio: gpio@6000d000 {
 259                 compatible = "nvidia,tegra20-gpio";
 260                 reg = <0x6000d000 0x1000>;
 261                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
 262                              <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
 263                              <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
 264                              <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
 265                              <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
 266                              <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
 267                              <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
 268                 #gpio-cells = <2>;
 269                 gpio-controller;
 270                 #interrupt-cells = <2>;
 271                 interrupt-controller;
 272                 /*
 273                 gpio-ranges = <&pinmux 0 0 224>;
 274                 */
 275         };
 276
 277         vde@6001a000 {
 278                 compatible = "nvidia,tegra20-vde";
 279                 reg = <0x6001a000 0x1000>, /* Syntax Engine */
 280                       <0x6001b000 0x1000>, /* Video Bitstream Engine */
 281                       <0x6001c000  0x100>, /* Macroblock Engine */
 282                       <0x6001c200  0x100>, /* Post-processing Engine */
 283                       <0x6001c400  0x100>, /* Motion Compensation Engine */
 284                       <0x6001c600  0x100>, /* Transform Engine */
 285                       <0x6001c800  0x100>, /* Pixel prediction block */
 286                       <0x6001ca00  0x100>, /* Video DMA */
 287                       <0x6001d800  0x300>; /* Video frame controls */
 288                 reg-names = "sxe", "bsev", "mbe", "ppe", "mce",
 289                             "tfe", "ppb", "vdma", "frameid";
 290                 iram = <&vde_pool>; /* IRAM region */
 291                 interrupts = <GIC_SPI  9 IRQ_TYPE_LEVEL_HIGH>, /* Sync token interrupt */
 292                              <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, /* BSE-V interrupt */
 293                              <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; /* SXE interrupt */
 294                 interrupt-names = "sync-token", "bsev", "sxe";
 295                 clocks = <&tegra_car TEGRA20_CLK_VDE>;
 296                 reset-names = "vde", "mc";
 297                 resets = <&tegra_car 61>, <&mc TEGRA20_MC_RESET_VDE>;
 298         };
 299
 300         apbmisc@70000800 {
 301                 compatible = "nvidia,tegra20-apbmisc";
 302                 reg = <0x70000800 0x64>, /* Chip revision */
 303                       <0x70000008 0x04>; /* Strapping options */
 304         };
 305
 306         pinmux: pinmux@70000014 {
 307                 compatible = "nvidia,tegra20-pinmux";
 308                 reg = <0x70000014 0x10>, /* Tri-state registers */
 309                       <0x70000080 0x20>, /* Mux registers */
 310                       <0x700000a0 0x14>, /* Pull-up/down registers */
 311                       <0x70000868 0xa8>; /* Pad control registers */
 312         };
 313
 314         das@70000c00 {
 315                 compatible = "nvidia,tegra20-das";
 316                 reg = <0x70000c00 0x80>;
 317         };
 318
 319         tegra_ac97: ac97@70002000 {
 320                 compatible = "nvidia,tegra20-ac97";
 321                 reg = <0x70002000 0x200>;
 322                 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
 323                 clocks = <&tegra_car TEGRA20_CLK_AC97>;
 324                 resets = <&tegra_car 3>;
 325                 reset-names = "ac97";
 326                 dmas = <&apbdma 12>, <&apbdma 12>;
 327                 dma-names = "rx", "tx";
 328                 status = "disabled";
 329         };
 330
 331         tegra_i2s1: i2s@70002800 {
 332                 compatible = "nvidia,tegra20-i2s";
 333                 reg = <0x70002800 0x200>;
 334                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 335                 clocks = <&tegra_car TEGRA20_CLK_I2S1>;
 336                 resets = <&tegra_car 11>;
 337                 reset-names = "i2s";
 338                 dmas = <&apbdma 2>, <&apbdma 2>;
 339                 dma-names = "rx", "tx";
 340                 status = "disabled";
 341         };
 342
 343         tegra_i2s2: i2s@70002a00 {
 344                 compatible = "nvidia,tegra20-i2s";
 345                 reg = <0x70002a00 0x200>;
 346                 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 347                 clocks = <&tegra_car TEGRA20_CLK_I2S2>;
 348                 resets = <&tegra_car 18>;
 349                 reset-names = "i2s";
 350                 dmas = <&apbdma 1>, <&apbdma 1>;
 351                 dma-names = "rx", "tx";
 352                 status = "disabled";
 353         };
 354
 355         /*
 356          * There are two serial driver i.e. 8250 based simple serial
 357          * driver and APB DMA based serial driver for higher baudrate
 358          * and performace. To enable the 8250 based driver, the compatible
 359          * is "nvidia,tegra20-uart" and to enable the APB DMA based serial
 360          * driver, the compatible is "nvidia,tegra20-hsuart".
 361          */
 362         uarta: serial@70006000 {
 363                 compatible = "nvidia,tegra20-uart";
 364                 reg = <0x70006000 0x40>;
 365                 reg-shift = <2>;
 366                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 367                 clocks = <&tegra_car TEGRA20_CLK_UARTA>;
 368                 resets = <&tegra_car 6>;
 369                 reset-names = "serial";
 370                 dmas = <&apbdma 8>, <&apbdma 8>;
 371                 dma-names = "rx", "tx";
 372                 status = "disabled";
 373         };
 374
 375         uartb: serial@70006040 {
 376                 compatible = "nvidia,tegra20-uart";
 377                 reg = <0x70006040 0x40>;
 378                 reg-shift = <2>;
 379                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 380                 clocks = <&tegra_car TEGRA20_CLK_UARTB>;
 381                 resets = <&tegra_car 7>;
 382                 reset-names = "serial";
 383                 dmas = <&apbdma 9>, <&apbdma 9>;
 384                 dma-names = "rx", "tx";
 385                 status = "disabled";
 386         };
 387
 388         uartc: serial@70006200 {
 389                 compatible = "nvidia,tegra20-uart";
 390                 reg = <0x70006200 0x100>;
 391                 reg-shift = <2>;
 392                 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 393                 clocks = <&tegra_car TEGRA20_CLK_UARTC>;
 394                 resets = <&tegra_car 55>;
 395                 reset-names = "serial";
 396                 dmas = <&apbdma 10>, <&apbdma 10>;
 397                 dma-names = "rx", "tx";
 398                 status = "disabled";
 399         };
 400
 401         uartd: serial@70006300 {
 402                 compatible = "nvidia,tegra20-uart";
 403                 reg = <0x70006300 0x100>;
 404                 reg-shift = <2>;
 405                 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
 406                 clocks = <&tegra_car TEGRA20_CLK_UARTD>;
 407                 resets = <&tegra_car 65>;
 408                 reset-names = "serial";
 409                 dmas = <&apbdma 19>, <&apbdma 19>;
 410                 dma-names = "rx", "tx";
 411                 status = "disabled";
 412         };
 413
 414         uarte: serial@70006400 {
 415                 compatible = "nvidia,tegra20-uart";
 416                 reg = <0x70006400 0x100>;
 417                 reg-shift = <2>;
 418                 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
 419                 clocks = <&tegra_car TEGRA20_CLK_UARTE>;
 420                 resets = <&tegra_car 66>;
 421                 reset-names = "serial";
 422                 dmas = <&apbdma 20>, <&apbdma 20>;
 423                 dma-names = "rx", "tx";
 424                 status = "disabled";
 425         };
 426
 427         nand-controller@70008000 {
 428                 compatible = "nvidia,tegra20-nand";
 429                 reg = <0x70008000 0x100>;
 430                 #address-cells = <1>;
 431                 #size-cells = <0>;
 432                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 433                 clocks = <&tegra_car TEGRA20_CLK_NDFLASH>;
 434                 clock-names = "nand";
 435                 resets = <&tegra_car 13>;
 436                 reset-names = "nand";
 437                 assigned-clocks = <&tegra_car TEGRA20_CLK_NDFLASH>;
 438                 assigned-clock-rates = <150000000>;
 439                 status = "disabled";
 440         };
 441
 442         gmi@70009000 {
 443                 compatible = "nvidia,tegra20-gmi";
 444                 reg = <0x70009000 0x1000>;
 445                 #address-cells = <2>;
 446                 #size-cells = <1>;
 447                 ranges = <0 0 0xd0000000 0xfffffff>;
 448                 clocks = <&tegra_car TEGRA20_CLK_NOR>;
 449                 clock-names = "gmi";
 450                 resets = <&tegra_car 42>;
 451                 reset-names = "gmi";
 452                 status = "disabled";
 453         };
 454
 455         pwm: pwm@7000a000 {
 456                 compatible = "nvidia,tegra20-pwm";
 457                 reg = <0x7000a000 0x100>;
 458                 #pwm-cells = <2>;
 459                 clocks = <&tegra_car TEGRA20_CLK_PWM>;
 460                 resets = <&tegra_car 17>;
 461                 reset-names = "pwm";
 462                 status = "disabled";
 463         };
 464
 465         rtc@7000e000 {
 466                 compatible = "nvidia,tegra20-rtc";
 467                 reg = <0x7000e000 0x100>;
 468                 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
 469                 clocks = <&tegra_car TEGRA20_CLK_RTC>;
 470         };
 471
 472         i2c@7000c000 {
 473                 compatible = "nvidia,tegra20-i2c";
 474                 reg = <0x7000c000 0x100>;
 475                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 476                 #address-cells = <1>;
 477                 #size-cells = <0>;
 478                 clocks = <&tegra_car TEGRA20_CLK_I2C1>,
 479                          <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
 480                 clock-names = "div-clk", "fast-clk";
 481                 resets = <&tegra_car 12>;
 482                 reset-names = "i2c";
 483                 dmas = <&apbdma 21>, <&apbdma 21>;
 484                 dma-names = "rx", "tx";
 485                 status = "disabled";
 486         };
 487
 488         spi@7000c380 {
 489                 compatible = "nvidia,tegra20-sflash";
 490                 reg = <0x7000c380 0x80>;
 491                 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 492                 #address-cells = <1>;
 493                 #size-cells = <0>;
 494                 clocks = <&tegra_car TEGRA20_CLK_SPI>;
 495                 resets = <&tegra_car 43>;
 496                 reset-names = "spi";
 497                 dmas = <&apbdma 11>, <&apbdma 11>;
 498                 dma-names = "rx", "tx";
 499                 status = "disabled";
 500         };
 501
 502         i2c@7000c400 {
 503                 compatible = "nvidia,tegra20-i2c";
 504                 reg = <0x7000c400 0x100>;
 505                 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 506                 #address-cells = <1>;
 507                 #size-cells = <0>;
 508                 clocks = <&tegra_car TEGRA20_CLK_I2C2>,
 509                          <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
 510                 clock-names = "div-clk", "fast-clk";
 511                 resets = <&tegra_car 54>;
 512                 reset-names = "i2c";
 513                 dmas = <&apbdma 22>, <&apbdma 22>;
 514                 dma-names = "rx", "tx";
 515                 status = "disabled";
 516         };
 517
 518         i2c@7000c500 {
 519                 compatible = "nvidia,tegra20-i2c";
 520                 reg = <0x7000c500 0x100>;
 521                 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
 522                 #address-cells = <1>;
 523                 #size-cells = <0>;
 524                 clocks = <&tegra_car TEGRA20_CLK_I2C3>,
 525                          <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
 526                 clock-names = "div-clk", "fast-clk";
 527                 resets = <&tegra_car 67>;
 528                 reset-names = "i2c";
 529                 dmas = <&apbdma 23>, <&apbdma 23>;
 530                 dma-names = "rx", "tx";
 531                 status = "disabled";
 532         };
 533
 534         i2c@7000d000 {
 535                 compatible = "nvidia,tegra20-i2c-dvc";
 536                 reg = <0x7000d000 0x200>;
 537                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 538                 #address-cells = <1>;
 539                 #size-cells = <0>;
 540                 clocks = <&tegra_car TEGRA20_CLK_DVC>,
 541                          <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
 542                 clock-names = "div-clk", "fast-clk";
 543                 resets = <&tegra_car 47>;
 544                 reset-names = "i2c";
 545                 dmas = <&apbdma 24>, <&apbdma 24>;
 546                 dma-names = "rx", "tx";
 547                 status = "disabled";
 548         };
 549
 550         spi@7000d400 {
 551                 compatible = "nvidia,tegra20-slink";
 552                 reg = <0x7000d400 0x200>;
 553                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 554                 #address-cells = <1>;
 555                 #size-cells = <0>;
 556                 clocks = <&tegra_car TEGRA20_CLK_SBC1>;
 557                 resets = <&tegra_car 41>;
 558                 reset-names = "spi";
 559                 dmas = <&apbdma 15>, <&apbdma 15>;
 560                 dma-names = "rx", "tx";
 561                 status = "disabled";
 562         };
 563
 564         spi@7000d600 {
 565                 compatible = "nvidia,tegra20-slink";
 566                 reg = <0x7000d600 0x200>;
 567                 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 568                 #address-cells = <1>;
 569                 #size-cells = <0>;
 570                 clocks = <&tegra_car TEGRA20_CLK_SBC2>;
 571                 resets = <&tegra_car 44>;
 572                 reset-names = "spi";
 573                 dmas = <&apbdma 16>, <&apbdma 16>;
 574                 dma-names = "rx", "tx";
 575                 status = "disabled";
 576         };
 577
 578         spi@7000d800 {
 579                 compatible = "nvidia,tegra20-slink";
 580                 reg = <0x7000d800 0x200>;
 581                 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 582                 #address-cells = <1>;
 583                 #size-cells = <0>;
 584                 clocks = <&tegra_car TEGRA20_CLK_SBC3>;
 585                 resets = <&tegra_car 46>;
 586                 reset-names = "spi";
 587                 dmas = <&apbdma 17>, <&apbdma 17>;
 588                 dma-names = "rx", "tx";
 589                 status = "disabled";
 590         };
 591
 592         spi@7000da00 {
 593                 compatible = "nvidia,tegra20-slink";
 594                 reg = <0x7000da00 0x200>;
 595                 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
 596                 #address-cells = <1>;
 597                 #size-cells = <0>;
 598                 clocks = <&tegra_car TEGRA20_CLK_SBC4>;
 599                 resets = <&tegra_car 68>;
 600                 reset-names = "spi";
 601                 dmas = <&apbdma 18>, <&apbdma 18>;
 602                 dma-names = "rx", "tx";
 603                 status = "disabled";
 604         };
 605
 606         kbc@7000e200 {
 607                 compatible = "nvidia,tegra20-kbc";
 608                 reg = <0x7000e200 0x100>;
 609                 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 610                 clocks = <&tegra_car TEGRA20_CLK_KBC>;
 611                 resets = <&tegra_car 36>;
 612                 reset-names = "kbc";
 613                 status = "disabled";
 614         };
 615
 616         tegra_pmc: pmc@7000e400 {
 617                 compatible = "nvidia,tegra20-pmc";
 618                 reg = <0x7000e400 0x400>;
 619                 clocks = <&tegra_car TEGRA20_CLK_PCLK>, <&clk32k_in>;
 620                 clock-names = "pclk", "clk32k_in";
 621                 #clock-cells = <1>;
 622         };
 623
 624         mc: memory-controller@7000f000 {
 625                 compatible = "nvidia,tegra20-mc-gart";
 626                 reg = <0x7000f000 0x00000400>, /* controller registers */
 627                       <0x58000000 0x02000000>; /* GART aperture */
 628                 clocks = <&tegra_car TEGRA20_CLK_MC>;
 629                 clock-names = "mc";
 630                 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
 631                 #reset-cells = <1>;
 632                 #iommu-cells = <0>;
 633         };
 634
 635         memory-controller@7000f400 {
 636                 compatible = "nvidia,tegra20-emc";
 637                 reg = <0x7000f400 0x200>;
 638                 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
 639                 clocks = <&tegra_car TEGRA20_CLK_EMC>;
 640                 #address-cells = <1>;
 641                 #size-cells = <0>;
 642         };
 643
 644         fuse@7000f800 {
 645                 compatible = "nvidia,tegra20-efuse";
 646                 reg = <0x7000f800 0x400>;
 647                 clocks = <&tegra_car TEGRA20_CLK_FUSE>;
 648                 clock-names = "fuse";
 649                 resets = <&tegra_car 39>;
 650                 reset-names = "fuse";
 651         };
 652
 653         pcie@80003000 {
 654                 compatible = "nvidia,tegra20-pcie";
 655                 device_type = "pci";
 656                 reg = <0x80003000 0x00000800>, /* PADS registers */
 657                       <0x80003800 0x00000200>, /* AFI registers */
 658                       <0x90000000 0x10000000>; /* configuration space */
 659                 reg-names = "pads", "afi", "cs";
 660                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
 661                              <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
 662                 interrupt-names = "intr", "msi";
 663
 664                 #interrupt-cells = <1>;
 665                 interrupt-map-mask = <0 0 0 0>;
 666                 interrupt-map = <0 0 0 0 &intc GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
 667
 668                 bus-range = <0x00 0xff>;
 669                 #address-cells = <3>;
 670                 #size-cells = <2>;
 671
 672                 ranges = <0x02000000 0 0x80000000 0x80000000 0 0x00001000>, /* port 0 registers */
 673                          <0x02000000 0 0x80001000 0x80001000 0 0x00001000>, /* port 1 registers */
 674                          <0x01000000 0 0          0x82000000 0 0x00010000>, /* downstream I/O */
 675                          <0x02000000 0 0xa0000000 0xa0000000 0 0x08000000>, /* non-prefetchable memory */
 676                          <0x42000000 0 0xa8000000 0xa8000000 0 0x18000000>; /* prefetchable memory */
 677
 678                 clocks = <&tegra_car TEGRA20_CLK_PEX>,
 679                          <&tegra_car TEGRA20_CLK_AFI>,
 680                          <&tegra_car TEGRA20_CLK_PLL_E>;
 681                 clock-names = "pex", "afi", "pll_e";
 682                 resets = <&tegra_car 70>,
 683                          <&tegra_car 72>,
 684                          <&tegra_car 74>;
 685                 reset-names = "pex", "afi", "pcie_x";
 686                 status = "disabled";
 687
 688                 pci@1,0 {
 689                         device_type = "pci";
 690                         assigned-addresses = <0x82000800 0 0x80000000 0 0x1000>;
 691                         reg = <0x000800 0 0 0 0>;
 692                         bus-range = <0x00 0xff>;
 693                         status = "disabled";
 694
 695                         #address-cells = <3>;
 696                         #size-cells = <2>;
 697                         ranges;
 698
 699                         nvidia,num-lanes = <2>;
 700                 };
 701
 702                 pci@2,0 {
 703                         device_type = "pci";
 704                         assigned-addresses = <0x82001000 0 0x80001000 0 0x1000>;
 705                         reg = <0x001000 0 0 0 0>;
 706                         bus-range = <0x00 0xff>;
 707                         status = "disabled";
 708
 709                         #address-cells = <3>;
 710                         #size-cells = <2>;
 711                         ranges;
 712
 713                         nvidia,num-lanes = <2>;
 714                 };
 715         };
 716
 717         usb@c5000000 {
 718                 compatible = "nvidia,tegra20-ehci", "usb-ehci";
 719                 reg = <0xc5000000 0x4000>;
 720                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 721                 phy_type = "utmi";
 722                 nvidia,has-legacy-mode;
 723                 clocks = <&tegra_car TEGRA20_CLK_USBD>;
 724                 resets = <&tegra_car 22>;
 725                 reset-names = "usb";
 726                 nvidia,needs-double-reset;
 727                 nvidia,phy = <&phy1>;
 728                 status = "disabled";
 729         };
 730
 731         phy1: usb-phy@c5000000 {
 732                 compatible = "nvidia,tegra20-usb-phy";
 733                 reg = <0xc5000000 0x4000>,
 734                       <0xc5000000 0x4000>;
 735                 phy_type = "utmi";
 736                 clocks = <&tegra_car TEGRA20_CLK_USBD>,
 737                          <&tegra_car TEGRA20_CLK_PLL_U>,
 738                          <&tegra_car TEGRA20_CLK_CLK_M>,
 739                          <&tegra_car TEGRA20_CLK_USBD>;
 740                 clock-names = "reg", "pll_u", "timer", "utmi-pads";
 741                 resets = <&tegra_car 22>, <&tegra_car 22>;
 742                 reset-names = "usb", "utmi-pads";
 743                 #phy-cells = <0>;
 744                 nvidia,has-legacy-mode;
 745                 nvidia,hssync-start-delay = <9>;
 746                 nvidia,idle-wait-delay = <17>;
 747                 nvidia,elastic-limit = <16>;
 748                 nvidia,term-range-adj = <6>;
 749                 nvidia,xcvr-setup = <9>;
 750                 nvidia,xcvr-lsfslew = <1>;
 751                 nvidia,xcvr-lsrslew = <1>;
 752                 nvidia,has-utmi-pad-registers;
 753                 status = "disabled";
 754         };
 755
 756         usb@c5004000 {
 757                 compatible = "nvidia,tegra20-ehci", "usb-ehci";
 758                 reg = <0xc5004000 0x4000>;
 759                 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
 760                 phy_type = "ulpi";
 761                 clocks = <&tegra_car TEGRA20_CLK_USB2>;
 762                 resets = <&tegra_car 58>;
 763                 reset-names = "usb";
 764                 nvidia,phy = <&phy2>;
 765                 status = "disabled";
 766         };
 767
 768         phy2: usb-phy@c5004000 {
 769                 compatible = "nvidia,tegra20-usb-phy";
 770                 reg = <0xc5004000 0x4000>;
 771                 phy_type = "ulpi";
 772                 clocks = <&tegra_car TEGRA20_CLK_USB2>,
 773                          <&tegra_car TEGRA20_CLK_PLL_U>,
 774                          <&tegra_car TEGRA20_CLK_CDEV2>;
 775                 clock-names = "reg", "pll_u", "ulpi-link";
 776                 resets = <&tegra_car 58>, <&tegra_car 22>;
 777                 reset-names = "usb", "utmi-pads";
 778                 #phy-cells = <0>;
 779                 status = "disabled";
 780         };
 781
 782         usb@c5008000 {
 783                 compatible = "nvidia,tegra20-ehci", "usb-ehci";
 784                 reg = <0xc5008000 0x4000>;
 785                 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 786                 phy_type = "utmi";
 787                 clocks = <&tegra_car TEGRA20_CLK_USB3>;
 788                 resets = <&tegra_car 59>;
 789                 reset-names = "usb";
 790                 nvidia,phy = <&phy3>;
 791                 status = "disabled";
 792         };
 793
 794         phy3: usb-phy@c5008000 {
 795                 compatible = "nvidia,tegra20-usb-phy";
 796                 reg = <0xc5008000 0x4000>,
 797                       <0xc5000000 0x4000>;
 798                 phy_type = "utmi";
 799                 clocks = <&tegra_car TEGRA20_CLK_USB3>,
 800                          <&tegra_car TEGRA20_CLK_PLL_U>,
 801                          <&tegra_car TEGRA20_CLK_CLK_M>,
 802                          <&tegra_car TEGRA20_CLK_USBD>;
 803                 clock-names = "reg", "pll_u", "timer", "utmi-pads";
 804                 resets = <&tegra_car 59>, <&tegra_car 22>;
 805                 reset-names = "usb", "utmi-pads";
 806                 #phy-cells = <0>;
 807                 nvidia,hssync-start-delay = <9>;
 808                 nvidia,idle-wait-delay = <17>;
 809                 nvidia,elastic-limit = <16>;
 810                 nvidia,term-range-adj = <6>;
 811                 nvidia,xcvr-setup = <9>;
 812                 nvidia,xcvr-lsfslew = <2>;
 813                 nvidia,xcvr-lsrslew = <2>;
 814                 status = "disabled";
 815         };
 816
 817         mmc@c8000000 {
 818                 compatible = "nvidia,tegra20-sdhci";
 819                 reg = <0xc8000000 0x200>;
 820                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 821                 clocks = <&tegra_car TEGRA20_CLK_SDMMC1>;
 822                 clock-names = "sdhci";
 823                 resets = <&tegra_car 14>;
 824                 reset-names = "sdhci";
 825                 status = "disabled";
 826         };
 827
 828         mmc@c8000200 {
 829                 compatible = "nvidia,tegra20-sdhci";
 830                 reg = <0xc8000200 0x200>;
 831                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 832                 clocks = <&tegra_car TEGRA20_CLK_SDMMC2>;
 833                 clock-names = "sdhci";
 834                 resets = <&tegra_car 9>;
 835                 reset-names = "sdhci";
 836                 status = "disabled";
 837         };
 838
 839         mmc@c8000400 {
 840                 compatible = "nvidia,tegra20-sdhci";
 841                 reg = <0xc8000400 0x200>;
 842                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 843                 clocks = <&tegra_car TEGRA20_CLK_SDMMC3>;
 844                 clock-names = "sdhci";
 845                 resets = <&tegra_car 69>;
 846                 reset-names = "sdhci";
 847                 status = "disabled";
 848         };
 849
 850         mmc@c8000600 {
 851                 compatible = "nvidia,tegra20-sdhci";
 852                 reg = <0xc8000600 0x200>;
 853                 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 854                 clocks = <&tegra_car TEGRA20_CLK_SDMMC4>;
 855                 clock-names = "sdhci";
 856                 resets = <&tegra_car 15>;
 857                 reset-names = "sdhci";
 858                 status = "disabled";
 859         };
 860
 861         cpus {
 862                 #address-cells = <1>;
 863                 #size-cells = <0>;
 864
 865                 cpu@0 {
 866                         device_type = "cpu";
 867                         compatible = "arm,cortex-a9";
 868                         reg = <0>;
 869                         clocks = <&tegra_car TEGRA20_CLK_CCLK>;
 870                 };
 871
 872                 cpu@1 {
 873                         device_type = "cpu";
 874                         compatible = "arm,cortex-a9";
 875                         reg = <1>;
 876                         clocks = <&tegra_car TEGRA20_CLK_CCLK>;
 877                 };
 878         };
 879
 880         pmu {
 881                 compatible = "arm,cortex-a9-pmu";
 882                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
 883                              <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 884                 interrupt-affinity = <&{/cpus/cpu@0}>,
 885                                      <&{/cpus/cpu@1}>;
 886         };
 887 };