arch/arm/boot/dts/tegra20-trimslice.dts

   1 // SPDX-License-Identifier: GPL-2.0
   2 /dts-v1/;
   3
   4 #include <dt-bindings/input/input.h>
   5 #include "tegra20.dtsi"
   6 #include "tegra20-cpu-opp.dtsi"
   7
   8 / {
   9         model = "Compulab TrimSlice board";
  10         compatible = "compulab,trimslice", "nvidia,tegra20";
  11
  12         aliases {
  13                 rtc0 = "/i2c@7000c500/rtc@56";
  14                 rtc1 = "/rtc@7000e000";
  15                 serial0 = &uarta;
  16         };
  17
  18         chosen {
  19                 stdout-path = "serial0:115200n8";
  20         };
  21
  22         memory@0 {
  23                 reg = <0x00000000 0x40000000>;
  24         };
  25
  26         host1x@50000000 {
  27                 hdmi@54280000 {
  28                         status = "okay";
  29
  30                         vdd-supply = <&hdmi_vdd_reg>;
  31                         pll-supply = <&hdmi_pll_reg>;
  32
  33                         nvidia,ddc-i2c-bus = <&hdmi_ddc>;
  34                         nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
  35                                 GPIO_ACTIVE_HIGH>;
  36                 };
  37         };
  38
  39         pinmux@70000014 {
  40                 pinctrl-names = "default";
  41                 pinctrl-0 = <&state_default>;
  42
  43                 state_default: pinmux {
  44                         ata {
  45                                 nvidia,pins = "ata";
  46                                 nvidia,function = "ide";
  47                         };
  48                         atb {
  49                                 nvidia,pins = "atb", "gma";
  50                                 nvidia,function = "sdio4";
  51                         };
  52                         atc {
  53                                 nvidia,pins = "atc", "gmb";
  54                                 nvidia,function = "nand";
  55                         };
  56                         atd {
  57                                 nvidia,pins = "atd", "ate", "gme", "pta";
  58                                 nvidia,function = "gmi";
  59                         };
  60                         cdev1 {
  61                                 nvidia,pins = "cdev1";
  62                                 nvidia,function = "plla_out";
  63                         };
  64                         cdev2 {
  65                                 nvidia,pins = "cdev2";
  66                                 nvidia,function = "pllp_out4";
  67                         };
  68                         crtp {
  69                                 nvidia,pins = "crtp";
  70                                 nvidia,function = "crt";
  71                         };
  72                         csus {
  73                                 nvidia,pins = "csus";
  74                                 nvidia,function = "vi_sensor_clk";
  75                         };
  76                         dap1 {
  77                                 nvidia,pins = "dap1";
  78                                 nvidia,function = "dap1";
  79                         };
  80                         dap2 {
  81                                 nvidia,pins = "dap2";
  82                                 nvidia,function = "dap2";
  83                         };
  84                         dap3 {
  85                                 nvidia,pins = "dap3";
  86                                 nvidia,function = "dap3";
  87                         };
  88                         dap4 {
  89                                 nvidia,pins = "dap4";
  90                                 nvidia,function = "dap4";
  91                         };
  92                         ddc {
  93                                 nvidia,pins = "ddc";
  94                                 nvidia,function = "i2c2";
  95                         };
  96                         dta {
  97                                 nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte";
  98                                 nvidia,function = "vi";
  99                         };
 100                         dtf {
 101                                 nvidia,pins = "dtf";
 102                                 nvidia,function = "i2c3";
 103                         };
 104                         gmc {
 105                                 nvidia,pins = "gmc", "gmd";
 106                                 nvidia,function = "sflash";
 107                         };
 108                         gpu {
 109                                 nvidia,pins = "gpu";
 110                                 nvidia,function = "uarta";
 111                         };
 112                         gpu7 {
 113                                 nvidia,pins = "gpu7";
 114                                 nvidia,function = "rtck";
 115                         };
 116                         gpv {
 117                                 nvidia,pins = "gpv", "slxa", "slxk";
 118                                 nvidia,function = "pcie";
 119                         };
 120                         hdint {
 121                                 nvidia,pins = "hdint";
 122                                 nvidia,function = "hdmi";
 123                         };
 124                         i2cp {
 125                                 nvidia,pins = "i2cp";
 126                                 nvidia,function = "i2cp";
 127                         };
 128                         irrx {
 129                                 nvidia,pins = "irrx", "irtx";
 130                                 nvidia,function = "uartb";
 131                         };
 132                         kbca {
 133                                 nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
 134                                         "kbce", "kbcf";
 135                                 nvidia,function = "kbc";
 136                         };
 137                         lcsn {
 138                                 nvidia,pins = "lcsn", "ld0", "ld1", "ld2",
 139                                         "ld3", "ld4", "ld5", "ld6", "ld7",
 140                                         "ld8", "ld9", "ld10", "ld11", "ld12",
 141                                         "ld13", "ld14", "ld15", "ld16", "ld17",
 142                                         "ldc", "ldi", "lhp0", "lhp1", "lhp2",
 143                                         "lhs", "lm0", "lm1", "lpp", "lpw0",
 144                                         "lpw1", "lpw2", "lsc0", "lsc1", "lsck",
 145                                         "lsda", "lsdi", "lspi", "lvp0", "lvp1",
 146                                         "lvs";
 147                                 nvidia,function = "displaya";
 148                         };
 149                         owc {
 150                                 nvidia,pins = "owc", "uac";
 151                                 nvidia,function = "rsvd2";
 152                         };
 153                         pmc {
 154                                 nvidia,pins = "pmc";
 155                                 nvidia,function = "pwr_on";
 156                         };
 157                         rm {
 158                                 nvidia,pins = "rm";
 159                                 nvidia,function = "i2c1";
 160                         };
 161                         sdb {
 162                                 nvidia,pins = "sdb", "sdc", "sdd";
 163                                 nvidia,function = "pwm";
 164                         };
 165                         sdio1 {
 166                                 nvidia,pins = "sdio1";
 167                                 nvidia,function = "sdio1";
 168                         };
 169                         slxc {
 170                                 nvidia,pins = "slxc", "slxd";
 171                                 nvidia,function = "sdio3";
 172                         };
 173                         spdi {
 174                                 nvidia,pins = "spdi", "spdo";
 175                                 nvidia,function = "spdif";
 176                         };
 177                         spia {
 178                                 nvidia,pins = "spia", "spib", "spic";
 179                                 nvidia,function = "spi2";
 180                         };
 181                         spid {
 182                                 nvidia,pins = "spid", "spie", "spif";
 183                                 nvidia,function = "spi1";
 184                         };
 185                         spig {
 186                                 nvidia,pins = "spig", "spih";
 187                                 nvidia,function = "spi2_alt";
 188                         };
 189                         uaa {
 190                                 nvidia,pins = "uaa", "uab", "uda";
 191                                 nvidia,function = "ulpi";
 192                         };
 193                         uad {
 194                                 nvidia,pins = "uad";
 195                                 nvidia,function = "irda";
 196                         };
 197                         uca {
 198                                 nvidia,pins = "uca", "ucb";
 199                                 nvidia,function = "uartc";
 200                         };
 201                         conf_ata {
 202                                 nvidia,pins = "ata", "atc", "atd", "ate",
 203                                         "crtp", "dap2", "dap3", "dap4", "dta",
 204                                         "dtb", "dtc", "dtd", "dte", "gmb",
 205                                         "gme", "i2cp", "pta", "slxc", "slxd",
 206                                         "spdi", "spdo", "uda";
 207                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 208                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 209                         };
 210                         conf_atb {
 211                                 nvidia,pins = "atb", "cdev1", "cdev2", "dap1",
 212                                         "gma", "gmc", "gmd", "gpu", "gpu7",
 213                                         "gpv", "sdio1", "slxa", "slxk", "uac";
 214                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 215                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 216                         };
 217                         conf_ck32 {
 218                                 nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
 219                                         "pmcc", "pmcd", "pmce", "xm2c", "xm2d";
 220                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 221                         };
 222                         conf_csus {
 223                                 nvidia,pins = "csus", "spia", "spib",
 224                                         "spid", "spif";
 225                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
 226                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 227                         };
 228                         conf_ddc {
 229                                 nvidia,pins = "ddc", "dtf", "rm", "sdc", "sdd";
 230                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
 231                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 232                         };
 233                         conf_hdint {
 234                                 nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
 235                                         "lpw1", "lsc1", "lsck", "lsda", "lsdi",
 236                                         "lvp0", "pmc";
 237                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 238                         };
 239                         conf_irrx {
 240                                 nvidia,pins = "irrx", "irtx", "kbca", "kbcb",
 241                                         "kbcc", "kbcd", "kbce", "kbcf", "owc",
 242                                         "spic", "spie", "spig", "spih", "uaa",
 243                                         "uab", "uad", "uca", "ucb";
 244                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
 245                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 246                         };
 247                         conf_lc {
 248                                 nvidia,pins = "lc", "ls";
 249                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
 250                         };
 251                         conf_ld0 {
 252                                 nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
 253                                         "ld5", "ld6", "ld7", "ld8", "ld9",
 254                                         "ld10", "ld11", "ld12", "ld13", "ld14",
 255                                         "ld15", "ld16", "ld17", "ldi", "lhp0",
 256                                         "lhp1", "lhp2", "lhs", "lm0", "lpp",
 257                                         "lpw0", "lpw2", "lsc0", "lspi", "lvp1",
 258                                         "lvs", "sdb";
 259                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 260                         };
 261                         conf_ld17_0 {
 262                                 nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
 263                                         "ld23_22";
 264                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
 265                         };
 266                         conf_spif {
 267                                 nvidia,pins = "spif";
 268                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
 269                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 270                         };
 271                 };
 272         };
 273
 274         i2s@70002800 {
 275                 status = "okay";
 276         };
 277
 278         serial@70006000 {
 279                 status = "okay";
 280         };
 281
 282         dvi_ddc: i2c@7000c000 {
 283                 status = "okay";
 284                 clock-frequency = <100000>;
 285         };
 286
 287         spi@7000c380 {
 288                 status = "okay";
 289                 spi-max-frequency = <48000000>;
 290                 spi-flash@0 {
 291                         compatible = "winbond,w25q80bl", "jedec,spi-nor";
 292                         reg = <0>;
 293                         spi-max-frequency = <48000000>;
 294                 };
 295         };
 296
 297         hdmi_ddc: i2c@7000c400 {
 298                 status = "okay";
 299                 clock-frequency = <100000>;
 300         };
 301
 302         i2c@7000c500 {
 303                 status = "okay";
 304                 clock-frequency = <400000>;
 305
 306                 codec: codec@1a {
 307                         compatible = "ti,tlv320aic23";
 308                         reg = <0x1a>;
 309                 };
 310
 311                 rtc@56 {
 312                         compatible = "emmicro,em3027";
 313                         reg = <0x56>;
 314                 };
 315         };
 316
 317         pmc@7000e400 {
 318                 nvidia,suspend-mode = <1>;
 319                 nvidia,cpu-pwr-good-time = <5000>;
 320                 nvidia,cpu-pwr-off-time = <5000>;
 321                 nvidia,core-pwr-good-time = <3845 3845>;
 322                 nvidia,core-pwr-off-time = <3875>;
 323                 nvidia,sys-clock-req-active-high;
 324         };
 325
 326         pcie@80003000 {
 327                 status = "okay";
 328
 329                 avdd-pex-supply = <&pci_vdd_reg>;
 330                 vdd-pex-supply = <&pci_vdd_reg>;
 331                 avdd-pex-pll-supply = <&pci_vdd_reg>;
 332                 avdd-plle-supply = <&pci_vdd_reg>;
 333                 vddio-pex-clk-supply = <&pci_clk_reg>;
 334
 335                 pci@1,0 {
 336                         status = "okay";
 337                 };
 338         };
 339
 340         usb@c5000000 {
 341                 status = "okay";
 342         };
 343
 344         usb-phy@c5000000 {
 345                 status = "okay";
 346                 vbus-supply = <&vbus_reg>;
 347         };
 348
 349         usb@c5004000 {
 350                 status = "okay";
 351                 nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 0)
 352                         GPIO_ACTIVE_LOW>;
 353         };
 354
 355         usb-phy@c5004000 {
 356                 status = "okay";
 357                 nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 0)
 358                         GPIO_ACTIVE_LOW>;
 359         };
 360
 361         usb@c5008000 {
 362                 status = "okay";
 363         };
 364
 365         usb-phy@c5008000 {
 366                 status = "okay";
 367         };
 368
 369         mmc@c8000000 {
 370                 status = "okay";
 371                 broken-cd;
 372                 bus-width = <4>;
 373         };
 374
 375         mmc@c8000600 {
 376                 status = "okay";
 377                 cd-gpios = <&gpio TEGRA_GPIO(P, 1) GPIO_ACTIVE_LOW>;
 378                 wp-gpios = <&gpio TEGRA_GPIO(P, 2) GPIO_ACTIVE_HIGH>;
 379                 bus-width = <4>;
 380         };
 381
 382         clk32k_in: clock@0 {
 383                 compatible = "fixed-clock";
 384                 clock-frequency = <32768>;
 385                 #clock-cells = <0>;
 386         };
 387
 388         gpio-keys {
 389                 compatible = "gpio-keys";
 390
 391                 power {
 392                         label = "Power";
 393                         gpios = <&gpio TEGRA_GPIO(X, 6) GPIO_ACTIVE_LOW>;
 394                         linux,code = <KEY_POWER>;
 395                         wakeup-source;
 396                 };
 397         };
 398
 399         poweroff {
 400                 compatible = "gpio-poweroff";
 401                 gpios = <&gpio TEGRA_GPIO(X, 7) GPIO_ACTIVE_LOW>;
 402         };
 403
 404         hdmi_vdd_reg: regulator@0 {
 405                 compatible = "regulator-fixed";
 406                 regulator-name = "avdd_hdmi";
 407                 regulator-min-microvolt = <3300000>;
 408                 regulator-max-microvolt = <3300000>;
 409                 regulator-always-on;
 410         };
 411
 412         hdmi_pll_reg: regulator@1 {
 413                 compatible = "regulator-fixed";
 414                 regulator-name = "avdd_hdmi_pll";
 415                 regulator-min-microvolt = <1800000>;
 416                 regulator-max-microvolt = <1800000>;
 417                 regulator-always-on;
 418         };
 419
 420         vbus_reg: regulator@2 {
 421                 compatible = "regulator-fixed";
 422                 regulator-name = "usb1_vbus";
 423                 regulator-min-microvolt = <5000000>;
 424                 regulator-max-microvolt = <5000000>;
 425                 enable-active-high;
 426                 gpio = <&gpio TEGRA_GPIO(V, 2) 0>;
 427                 regulator-always-on;
 428                 regulator-boot-on;
 429         };
 430
 431         pci_clk_reg: regulator@3 {
 432                 compatible = "regulator-fixed";
 433                 regulator-name = "pci_clk";
 434                 regulator-min-microvolt = <3300000>;
 435                 regulator-max-microvolt = <3300000>;
 436                 regulator-always-on;
 437         };
 438
 439         pci_vdd_reg: regulator@4 {
 440                 compatible = "regulator-fixed";
 441                 regulator-name = "pci_vdd";
 442                 regulator-min-microvolt = <1050000>;
 443                 regulator-max-microvolt = <1050000>;
 444                 regulator-always-on;
 445         };
 446
 447         sound {
 448                 compatible = "nvidia,tegra-audio-trimslice";
 449                 nvidia,i2s-controller = <&tegra_i2s1>;
 450                 nvidia,audio-codec = <&codec>;
 451
 452                 clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
 453                          <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
 454                          <&tegra_car TEGRA20_CLK_CDEV1>;
 455                 clock-names = "pll_a", "pll_a_out0", "mclk";
 456         };
 457
 458         cpus {
 459                 cpu0: cpu@0 {
 460                         operating-points-v2 = <&cpu0_opp_table>;
 461                 };
 462
 463                 cpu@1 {
 464                         operating-points-v2 = <&cpu0_opp_table>;
 465                 };
 466         };
 467 };