2 * Copyright 2015 Vishnu Patekar
4 * Vishnu Patekar <vishnupatekar0510@gmail.com>
6 * This file is dual-licensed: you can use it either under the terms
7 * of the GPL or the X11 license, at your option. Note that this dual
8 * licensing only applies to this file, and not this project as a
11 * a) This file is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of the
14 * License, or (at your option) any later version.
16 * This file is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
23 * b) Permission is hereby granted, free of charge, to any person
24 * obtaining a copy of this software and associated documentation
25 * files (the "Software"), to deal in the Software without
26 * restriction, including without limitation the rights to use,
27 * copy, modify, merge, publish, distribute, sublicense, and/or
28 * sell copies of the Software, and to permit persons to whom the
29 * Software is furnished to do so, subject to the following
32 * The above copyright notice and this permission notice shall be
33 * included in all copies or substantial portions of the Software.
35 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
36 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
37 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
38 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
39 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
40 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
41 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
42 * OTHER DEALINGS IN THE SOFTWARE.
45 #include <dt-bindings/interrupt-controller/arm-gic.h>
47 #include <dt-bindings/clock/sun8i-a83t-ccu.h>
48 #include <dt-bindings/clock/sun8i-de2.h>
49 #include <dt-bindings/clock/sun8i-r-ccu.h>
50 #include <dt-bindings/reset/sun8i-a83t-ccu.h>
51 #include <dt-bindings/reset/sun8i-de2.h>
52 #include <dt-bindings/reset/sun8i-r-ccu.h>
55 interrupt-parent = <&gic>;
64 compatible = "arm,cortex-a7";
66 clocks = <&ccu CLK_C0CPUX>;
67 operating-points-v2 = <&cpu0_opp_table>;
68 cci-control-port = <&cci_control0>;
69 enable-method = "allwinner,sun8i-a83t-smp";
75 compatible = "arm,cortex-a7";
77 clocks = <&ccu CLK_C0CPUX>;
78 operating-points-v2 = <&cpu0_opp_table>;
79 cci-control-port = <&cci_control0>;
80 enable-method = "allwinner,sun8i-a83t-smp";
86 compatible = "arm,cortex-a7";
88 clocks = <&ccu CLK_C0CPUX>;
89 operating-points-v2 = <&cpu0_opp_table>;
90 cci-control-port = <&cci_control0>;
91 enable-method = "allwinner,sun8i-a83t-smp";
97 compatible = "arm,cortex-a7";
99 clocks = <&ccu CLK_C0CPUX>;
100 operating-points-v2 = <&cpu0_opp_table>;
101 cci-control-port = <&cci_control0>;
102 enable-method = "allwinner,sun8i-a83t-smp";
104 #cooling-cells = <2>;
108 compatible = "arm,cortex-a7";
110 clocks = <&ccu CLK_C1CPUX>;
111 operating-points-v2 = <&cpu1_opp_table>;
112 cci-control-port = <&cci_control1>;
113 enable-method = "allwinner,sun8i-a83t-smp";
115 #cooling-cells = <2>;
119 compatible = "arm,cortex-a7";
121 clocks = <&ccu CLK_C1CPUX>;
122 operating-points-v2 = <&cpu1_opp_table>;
123 cci-control-port = <&cci_control1>;
124 enable-method = "allwinner,sun8i-a83t-smp";
126 #cooling-cells = <2>;
130 compatible = "arm,cortex-a7";
132 clocks = <&ccu CLK_C1CPUX>;
133 operating-points-v2 = <&cpu1_opp_table>;
134 cci-control-port = <&cci_control1>;
135 enable-method = "allwinner,sun8i-a83t-smp";
137 #cooling-cells = <2>;
141 compatible = "arm,cortex-a7";
143 clocks = <&ccu CLK_C1CPUX>;
144 operating-points-v2 = <&cpu1_opp_table>;
145 cci-control-port = <&cci_control1>;
146 enable-method = "allwinner,sun8i-a83t-smp";
148 #cooling-cells = <2>;
153 compatible = "arm,armv7-timer";
154 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
155 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
156 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
157 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
161 #address-cells = <1>;
165 /* TODO: PRCM block has a mux for this. */
168 compatible = "fixed-clock";
169 clock-frequency = <24000000>;
170 clock-accuracy = <50000>;
171 clock-output-names = "osc24M";
175 * This is called "internal OSC" in some places.
176 * It is an internal RC-based oscillator.
177 * TODO: Its controls are in the PRCM block.
181 compatible = "fixed-clock";
182 clock-frequency = <16000000>;
183 clock-output-names = "osc16M";
186 osc16Md512: osc16Md512_clk {
188 compatible = "fixed-factor-clock";
192 clock-output-names = "osc16M-d512";
197 compatible = "allwinner,sun8i-a83t-display-engine";
198 allwinner,pipelines = <&mixer0>, <&mixer1>;
202 cpu0_opp_table: opp_table0 {
203 compatible = "operating-points-v2";
207 opp-hz = /bits/ 64 <480000000>;
208 opp-microvolt = <840000>;
209 clock-latency-ns = <244144>; /* 8 32k periods */
213 opp-hz = /bits/ 64 <600000000>;
214 opp-microvolt = <840000>;
215 clock-latency-ns = <244144>; /* 8 32k periods */
219 opp-hz = /bits/ 64 <720000000>;
220 opp-microvolt = <840000>;
221 clock-latency-ns = <244144>; /* 8 32k periods */
225 opp-hz = /bits/ 64 <864000000>;
226 opp-microvolt = <840000>;
227 clock-latency-ns = <244144>; /* 8 32k periods */
231 opp-hz = /bits/ 64 <912000000>;
232 opp-microvolt = <840000>;
233 clock-latency-ns = <244144>; /* 8 32k periods */
237 opp-hz = /bits/ 64 <1008000000>;
238 opp-microvolt = <840000>;
239 clock-latency-ns = <244144>; /* 8 32k periods */
243 opp-hz = /bits/ 64 <1128000000>;
244 opp-microvolt = <840000>;
245 clock-latency-ns = <244144>; /* 8 32k periods */
249 opp-hz = /bits/ 64 <1200000000>;
250 opp-microvolt = <840000>;
251 clock-latency-ns = <244144>; /* 8 32k periods */
255 cpu1_opp_table: opp_table1 {
256 compatible = "operating-points-v2";
260 opp-hz = /bits/ 64 <480000000>;
261 opp-microvolt = <840000>;
262 clock-latency-ns = <244144>; /* 8 32k periods */
266 opp-hz = /bits/ 64 <600000000>;
267 opp-microvolt = <840000>;
268 clock-latency-ns = <244144>; /* 8 32k periods */
272 opp-hz = /bits/ 64 <720000000>;
273 opp-microvolt = <840000>;
274 clock-latency-ns = <244144>; /* 8 32k periods */
278 opp-hz = /bits/ 64 <864000000>;
279 opp-microvolt = <840000>;
280 clock-latency-ns = <244144>; /* 8 32k periods */
284 opp-hz = /bits/ 64 <912000000>;
285 opp-microvolt = <840000>;
286 clock-latency-ns = <244144>; /* 8 32k periods */
290 opp-hz = /bits/ 64 <1008000000>;
291 opp-microvolt = <840000>;
292 clock-latency-ns = <244144>; /* 8 32k periods */
296 opp-hz = /bits/ 64 <1128000000>;
297 opp-microvolt = <840000>;
298 clock-latency-ns = <244144>; /* 8 32k periods */
302 opp-hz = /bits/ 64 <1200000000>;
303 opp-microvolt = <840000>;
304 clock-latency-ns = <244144>; /* 8 32k periods */
309 compatible = "simple-bus";
310 #address-cells = <1>;
314 display_clocks: clock@1000000 {
315 compatible = "allwinner,sun8i-a83t-de2-clk";
316 reg = <0x01000000 0x100000>;
317 clocks = <&ccu CLK_BUS_DE>,
321 resets = <&ccu RST_BUS_DE>;
326 mixer0: mixer@1100000 {
327 compatible = "allwinner,sun8i-a83t-de2-mixer-0";
328 reg = <0x01100000 0x100000>;
329 clocks = <&display_clocks CLK_BUS_MIXER0>,
330 <&display_clocks CLK_MIXER0>;
333 resets = <&display_clocks RST_MIXER0>;
336 #address-cells = <1>;
340 #address-cells = <1>;
344 mixer0_out_tcon0: endpoint@0 {
346 remote-endpoint = <&tcon0_in_mixer0>;
349 mixer0_out_tcon1: endpoint@1 {
351 remote-endpoint = <&tcon1_in_mixer0>;
357 mixer1: mixer@1200000 {
358 compatible = "allwinner,sun8i-a83t-de2-mixer-1";
359 reg = <0x01200000 0x100000>;
360 clocks = <&display_clocks CLK_BUS_MIXER1>,
361 <&display_clocks CLK_MIXER1>;
364 resets = <&display_clocks RST_WB>;
367 #address-cells = <1>;
371 #address-cells = <1>;
375 mixer1_out_tcon0: endpoint@0 {
377 remote-endpoint = <&tcon0_in_mixer1>;
380 mixer1_out_tcon1: endpoint@1 {
382 remote-endpoint = <&tcon1_in_mixer1>;
389 compatible = "allwinner,sun8i-a83t-cpucfg";
390 reg = <0x01700000 0x400>;
394 compatible = "arm,cci-400";
395 #address-cells = <1>;
397 reg = <0x01790000 0x10000>;
398 ranges = <0x0 0x01790000 0x10000>;
400 cci_control0: slave-if@4000 {
401 compatible = "arm,cci-400-ctrl-if";
402 interface-type = "ace";
403 reg = <0x4000 0x1000>;
406 cci_control1: slave-if@5000 {
407 compatible = "arm,cci-400-ctrl-if";
408 interface-type = "ace";
409 reg = <0x5000 0x1000>;
413 compatible = "arm,cci-400-pmu,r1";
414 reg = <0x9000 0x5000>;
415 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
416 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
417 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
418 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
419 <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
420 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
421 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
422 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
426 syscon: syscon@1c00000 {
427 compatible = "allwinner,sun8i-a83t-system-controller",
429 reg = <0x01c00000 0x1000>;
432 dma: dma-controller@1c02000 {
433 compatible = "allwinner,sun8i-a83t-dma";
434 reg = <0x01c02000 0x1000>;
435 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
436 clocks = <&ccu CLK_BUS_DMA>;
437 resets = <&ccu RST_BUS_DMA>;
441 tcon0: lcd-controller@1c0c000 {
442 compatible = "allwinner,sun8i-a83t-tcon-lcd";
443 reg = <0x01c0c000 0x1000>;
444 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
445 clocks = <&ccu CLK_BUS_TCON0>, <&ccu CLK_TCON0>;
446 clock-names = "ahb", "tcon-ch0";
447 clock-output-names = "tcon-pixel-clock";
449 resets = <&ccu RST_BUS_TCON0>, <&ccu RST_BUS_LVDS>;
450 reset-names = "lcd", "lvds";
453 #address-cells = <1>;
457 #address-cells = <1>;
461 tcon0_in_mixer0: endpoint@0 {
463 remote-endpoint = <&mixer0_out_tcon0>;
466 tcon0_in_mixer1: endpoint@1 {
468 remote-endpoint = <&mixer1_out_tcon0>;
478 tcon1: lcd-controller@1c0d000 {
479 compatible = "allwinner,sun8i-a83t-tcon-tv";
480 reg = <0x01c0d000 0x1000>;
481 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
482 clocks = <&ccu CLK_BUS_TCON1>, <&ccu CLK_TCON1>;
483 clock-names = "ahb", "tcon-ch1";
484 resets = <&ccu RST_BUS_TCON1>;
488 #address-cells = <1>;
492 #address-cells = <1>;
496 tcon1_in_mixer0: endpoint@0 {
498 remote-endpoint = <&mixer0_out_tcon1>;
501 tcon1_in_mixer1: endpoint@1 {
503 remote-endpoint = <&mixer1_out_tcon1>;
508 #address-cells = <1>;
512 tcon1_out_hdmi: endpoint@1 {
514 remote-endpoint = <&hdmi_in_tcon1>;
521 compatible = "allwinner,sun8i-a83t-mmc",
522 "allwinner,sun7i-a20-mmc";
523 reg = <0x01c0f000 0x1000>;
524 clocks = <&ccu CLK_BUS_MMC0>,
526 <&ccu CLK_MMC0_OUTPUT>,
527 <&ccu CLK_MMC0_SAMPLE>;
532 resets = <&ccu RST_BUS_MMC0>;
534 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
536 #address-cells = <1>;
541 compatible = "allwinner,sun8i-a83t-mmc",
542 "allwinner,sun7i-a20-mmc";
543 reg = <0x01c10000 0x1000>;
544 clocks = <&ccu CLK_BUS_MMC1>,
546 <&ccu CLK_MMC1_OUTPUT>,
547 <&ccu CLK_MMC1_SAMPLE>;
552 resets = <&ccu RST_BUS_MMC1>;
554 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
555 pinctrl-names = "default";
556 pinctrl-0 = <&mmc1_pins>;
558 #address-cells = <1>;
563 compatible = "allwinner,sun8i-a83t-emmc";
564 reg = <0x01c11000 0x1000>;
565 clocks = <&ccu CLK_BUS_MMC2>,
567 <&ccu CLK_MMC2_OUTPUT>,
568 <&ccu CLK_MMC2_SAMPLE>;
573 resets = <&ccu RST_BUS_MMC2>;
575 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
577 #address-cells = <1>;
581 sid: eeprom@1c14000 {
582 compatible = "allwinner,sun8i-a83t-sid";
583 reg = <0x1c14000 0x400>;
586 usb_otg: usb@1c19000 {
587 compatible = "allwinner,sun8i-a83t-musb",
588 "allwinner,sun8i-a33-musb";
589 reg = <0x01c19000 0x0400>;
590 clocks = <&ccu CLK_BUS_OTG>;
591 resets = <&ccu RST_BUS_OTG>;
592 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
593 interrupt-names = "mc";
596 extcon = <&usbphy 0>;
601 usbphy: phy@1c19400 {
602 compatible = "allwinner,sun8i-a83t-usb-phy";
603 reg = <0x01c19400 0x10>,
606 reg-names = "phy_ctrl",
609 clocks = <&ccu CLK_USB_PHY0>,
612 <&ccu CLK_USB_HSIC_12M>;
613 clock-names = "usb0_phy",
617 resets = <&ccu RST_USB_PHY0>,
620 reset-names = "usb0_reset",
628 compatible = "allwinner,sun8i-a83t-ehci",
630 reg = <0x01c1a000 0x100>;
631 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
632 clocks = <&ccu CLK_BUS_EHCI0>;
633 resets = <&ccu RST_BUS_EHCI0>;
640 compatible = "allwinner,sun8i-a83t-ohci",
642 reg = <0x01c1a400 0x100>;
643 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
644 clocks = <&ccu CLK_BUS_OHCI0>, <&ccu CLK_USB_OHCI0>;
645 resets = <&ccu RST_BUS_OHCI0>;
652 compatible = "allwinner,sun8i-a83t-ehci",
654 reg = <0x01c1b000 0x100>;
655 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
656 clocks = <&ccu CLK_BUS_EHCI1>;
657 resets = <&ccu RST_BUS_EHCI1>;
664 compatible = "allwinner,sun8i-a83t-ccu";
665 reg = <0x01c20000 0x400>;
666 clocks = <&osc24M>, <&osc16Md512>;
667 clock-names = "hosc", "losc";
672 pio: pinctrl@1c20800 {
673 compatible = "allwinner,sun8i-a83t-pinctrl";
674 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
675 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
676 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
677 reg = <0x01c20800 0x400>;
678 clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc16Md512>;
679 clock-names = "apb", "hosc", "losc";
681 interrupt-controller;
682 #interrupt-cells = <3>;
686 csi_8bit_parallel_pins: csi-8bit-parallel-pins {
687 pins = "PE0", "PE2", "PE3", "PE6", "PE7",
688 "PE8", "PE9", "PE10", "PE11",
694 csi_mclk_pin: csi-mclk-pin {
699 emac_rgmii_pins: emac-rgmii-pins {
700 pins = "PD2", "PD3", "PD4", "PD5", "PD6", "PD7",
701 "PD11", "PD12", "PD13", "PD14", "PD18",
702 "PD19", "PD21", "PD22", "PD23";
705 * data lines in RGMII mode use DDR mode
706 * and need a higher signal drive strength
708 drive-strength = <40>;
711 hdmi_pins: hdmi-pins {
712 pins = "PH6", "PH7", "PH8";
716 i2c0_pins: i2c0-pins {
721 i2c1_pins: i2c1-pins {
727 i2c2_pe_pins: i2c2-pe-pins {
728 pins = "PE14", "PE15";
732 i2c2_ph_pins: i2c2-ph-pins {
737 i2s1_pins: i2s1-pins {
738 /* I2S1 does not have external MCLK pin */
739 pins = "PG10", "PG11", "PG12", "PG13";
743 lcd_lvds_pins: lcd-lvds-pins {
744 pins = "PD18", "PD19", "PD20", "PD21", "PD22",
745 "PD23", "PD24", "PD25", "PD26", "PD27";
749 mmc0_pins: mmc0-pins {
750 pins = "PF0", "PF1", "PF2",
753 drive-strength = <30>;
757 mmc1_pins: mmc1-pins {
758 pins = "PG0", "PG1", "PG2",
761 drive-strength = <30>;
765 mmc2_8bit_emmc_pins: mmc2-8bit-emmc-pins {
766 pins = "PC5", "PC6", "PC8", "PC9",
767 "PC10", "PC11", "PC12", "PC13",
768 "PC14", "PC15", "PC16";
770 drive-strength = <30>;
779 spdif_tx_pin: spdif-tx-pin {
784 uart0_pb_pins: uart0-pb-pins {
785 pins = "PB9", "PB10";
789 uart0_pf_pins: uart0-pf-pins {
794 uart1_pins: uart1-pins {
799 uart1_rts_cts_pins: uart1-rts-cts-pins {
805 uart2_pb_pins: uart2-pb-pins {
812 compatible = "allwinner,sun8i-a23-timer";
813 reg = <0x01c20c00 0xa0>;
814 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
815 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
820 compatible = "allwinner,sun6i-a31-wdt";
821 reg = <0x01c20ca0 0x20>;
822 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
826 spdif: spdif@1c21000 {
827 #sound-dai-cells = <0>;
828 compatible = "allwinner,sun8i-a83t-spdif",
829 "allwinner,sun8i-h3-spdif";
830 reg = <0x01c21000 0x400>;
831 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
832 clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>;
833 resets = <&ccu RST_BUS_SPDIF>;
834 clock-names = "apb", "spdif";
837 pinctrl-names = "default";
838 pinctrl-0 = <&spdif_tx_pin>;
843 #sound-dai-cells = <0>;
844 compatible = "allwinner,sun8i-a83t-i2s";
845 reg = <0x01c22000 0x400>;
846 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
847 clocks = <&ccu CLK_BUS_I2S0>, <&ccu CLK_I2S0>;
848 clock-names = "apb", "mod";
849 dmas = <&dma 3>, <&dma 3>;
850 resets = <&ccu RST_BUS_I2S0>;
851 dma-names = "rx", "tx";
856 #sound-dai-cells = <0>;
857 compatible = "allwinner,sun8i-a83t-i2s";
858 reg = <0x01c22400 0x400>;
859 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
860 clocks = <&ccu CLK_BUS_I2S1>, <&ccu CLK_I2S1>;
861 clock-names = "apb", "mod";
862 dmas = <&dma 4>, <&dma 4>;
863 resets = <&ccu RST_BUS_I2S1>;
864 dma-names = "rx", "tx";
865 pinctrl-names = "default";
866 pinctrl-0 = <&i2s1_pins>;
871 #sound-dai-cells = <0>;
872 compatible = "allwinner,sun8i-a83t-i2s";
873 reg = <0x01c22800 0x400>;
874 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
875 clocks = <&ccu CLK_BUS_I2S2>, <&ccu CLK_I2S2>;
876 clock-names = "apb", "mod";
878 resets = <&ccu RST_BUS_I2S2>;
884 compatible = "allwinner,sun8i-a83t-pwm",
885 "allwinner,sun8i-h3-pwm";
886 reg = <0x01c21400 0x400>;
892 uart0: serial@1c28000 {
893 compatible = "snps,dw-apb-uart";
894 reg = <0x01c28000 0x400>;
895 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
898 clocks = <&ccu CLK_BUS_UART0>;
899 resets = <&ccu RST_BUS_UART0>;
903 uart1: serial@1c28400 {
904 compatible = "snps,dw-apb-uart";
905 reg = <0x01c28400 0x400>;
906 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
909 clocks = <&ccu CLK_BUS_UART1>;
910 resets = <&ccu RST_BUS_UART1>;
914 uart2: serial@1c28800 {
915 compatible = "snps,dw-apb-uart";
916 reg = <0x01c28800 0x400>;
917 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
920 clocks = <&ccu CLK_BUS_UART2>;
921 resets = <&ccu RST_BUS_UART2>;
925 uart3: serial@1c28c00 {
926 compatible = "snps,dw-apb-uart";
927 reg = <0x01c28c00 0x400>;
928 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
931 clocks = <&ccu CLK_BUS_UART3>;
932 resets = <&ccu RST_BUS_UART3>;
936 uart4: serial@1c29000 {
937 compatible = "snps,dw-apb-uart";
938 reg = <0x01c29000 0x400>;
939 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
942 clocks = <&ccu CLK_BUS_UART4>;
943 resets = <&ccu RST_BUS_UART4>;
948 compatible = "allwinner,sun8i-a83t-i2c",
949 "allwinner,sun6i-a31-i2c";
950 reg = <0x01c2ac00 0x400>;
951 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
952 clocks = <&ccu CLK_BUS_I2C0>;
953 resets = <&ccu RST_BUS_I2C0>;
954 pinctrl-names = "default";
955 pinctrl-0 = <&i2c0_pins>;
957 #address-cells = <1>;
962 compatible = "allwinner,sun8i-a83t-i2c",
963 "allwinner,sun6i-a31-i2c";
964 reg = <0x01c2b000 0x400>;
965 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
966 clocks = <&ccu CLK_BUS_I2C1>;
967 resets = <&ccu RST_BUS_I2C1>;
968 pinctrl-names = "default";
969 pinctrl-0 = <&i2c1_pins>;
971 #address-cells = <1>;
976 compatible = "allwinner,sun8i-a83t-i2c",
977 "allwinner,sun6i-a31-i2c";
978 reg = <0x01c2b400 0x400>;
979 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
980 clocks = <&ccu CLK_BUS_I2C2>;
981 resets = <&ccu RST_BUS_I2C2>;
983 #address-cells = <1>;
987 emac: ethernet@1c30000 {
988 compatible = "allwinner,sun8i-a83t-emac";
990 reg = <0x01c30000 0x104>;
991 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
992 interrupt-names = "macirq";
994 reset-names = "stmmaceth";
996 clock-names = "stmmaceth";
1000 compatible = "snps,dwmac-mdio";
1001 #address-cells = <1>;
1006 gic: interrupt-controller@1c81000 {
1007 compatible = "arm,gic-400";
1008 reg = <0x01c81000 0x1000>,
1009 <0x01c82000 0x2000>,
1010 <0x01c84000 0x2000>,
1011 <0x01c86000 0x2000>;
1012 interrupt-controller;
1013 #interrupt-cells = <3>;
1014 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
1017 csi: camera@1cb0000 {
1018 compatible = "allwinner,sun8i-a83t-csi";
1019 reg = <0x01cb0000 0x1000>;
1020 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1021 clocks = <&ccu CLK_BUS_CSI>,
1022 <&ccu CLK_CSI_SCLK>,
1023 <&ccu CLK_DRAM_CSI>;
1024 clock-names = "bus", "mod", "ram";
1025 resets = <&ccu RST_BUS_CSI>;
1026 status = "disabled";
1032 hdmi: hdmi@1ee0000 {
1033 compatible = "allwinner,sun8i-a83t-dw-hdmi";
1034 reg = <0x01ee0000 0x10000>;
1036 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
1037 clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_SLOW>,
1039 clock-names = "iahb", "isfr", "tmds";
1040 resets = <&ccu RST_BUS_HDMI1>;
1041 reset-names = "ctrl";
1044 pinctrl-names = "default";
1045 pinctrl-0 = <&hdmi_pins>;
1046 status = "disabled";
1049 #address-cells = <1>;
1055 hdmi_in_tcon1: endpoint {
1056 remote-endpoint = <&tcon1_out_hdmi>;
1066 hdmi_phy: hdmi-phy@1ef0000 {
1067 compatible = "allwinner,sun8i-a83t-hdmi-phy";
1068 reg = <0x01ef0000 0x10000>;
1069 clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_SLOW>;
1070 clock-names = "bus", "mod";
1071 resets = <&ccu RST_BUS_HDMI0>;
1072 reset-names = "phy";
1076 r_intc: interrupt-controller@1f00c00 {
1077 compatible = "allwinner,sun8i-a83t-r-intc",
1078 "allwinner,sun6i-a31-r-intc";
1079 interrupt-controller;
1080 #interrupt-cells = <2>;
1081 reg = <0x01f00c00 0x400>;
1082 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
1085 r_ccu: clock@1f01400 {
1086 compatible = "allwinner,sun8i-a83t-r-ccu";
1087 reg = <0x01f01400 0x400>;
1088 clocks = <&osc24M>, <&osc16Md512>, <&osc16M>,
1090 clock-names = "hosc", "losc", "iosc", "pll-periph";
1096 compatible = "allwinner,sun8i-a83t-r-cpucfg";
1097 reg = <0x1f01c00 0x400>;
1101 compatible = "allwinner,sun8i-a83t-ir",
1102 "allwinner,sun6i-a31-ir";
1103 clocks = <&r_ccu CLK_APB0_IR>, <&r_ccu CLK_IR>;
1104 clock-names = "apb", "ir";
1105 resets = <&r_ccu RST_APB0_IR>;
1106 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
1107 reg = <0x01f02000 0x400>;
1108 pinctrl-names = "default";
1109 pinctrl-0 = <&r_cir_pin>;
1110 status = "disabled";
1113 r_lradc: lradc@1f03c00 {
1114 compatible = "allwinner,sun8i-a83t-r-lradc";
1115 reg = <0x01f03c00 0x100>;
1116 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
1117 status = "disabled";
1120 r_pio: pinctrl@1f02c00 {
1121 compatible = "allwinner,sun8i-a83t-r-pinctrl";
1122 reg = <0x01f02c00 0x400>;
1123 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
1124 clocks = <&r_ccu CLK_APB0_PIO>, <&osc24M>,
1126 clock-names = "apb", "hosc", "losc";
1129 interrupt-controller;
1130 #interrupt-cells = <3>;
1132 r_cir_pin: r-cir-pin {
1134 function = "s_cir_rx";
1137 r_rsb_pins: r-rsb-pins {
1138 pins = "PL0", "PL1";
1140 drive-strength = <20>;
1145 r_rsb: rsb@1f03400 {
1146 compatible = "allwinner,sun8i-a83t-rsb",
1147 "allwinner,sun8i-a23-rsb";
1148 reg = <0x01f03400 0x400>;
1149 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
1150 clocks = <&r_ccu CLK_APB0_RSB>;
1151 clock-frequency = <3000000>;
1152 resets = <&r_ccu RST_APB0_RSB>;
1153 pinctrl-names = "default";
1154 pinctrl-0 = <&r_rsb_pins>;
1155 status = "disabled";
1156 #address-cells = <1>;