arch/arm/boot/dts/sun8i-a23-a33.dtsi

   1 /*
   2  * Copyright 2014 Chen-Yu Tsai
   3  *
   4  * Chen-Yu Tsai <wens@csie.org>
   5  *
   6  * This file is dual-licensed: you can use it either under the terms
   7  * of the GPL or the X11 license, at your option. Note that this dual
   8  * licensing only applies to this file, and not this project as a
   9  * whole.
  10  *
  11  *  a) This file is free software; you can redistribute it and/or
  12  *     modify it under the terms of the GNU General Public License as
  13  *     published by the Free Software Foundation; either version 2 of the
  14  *     License, or (at your option) any later version.
  15  *
  16  *     This file is distributed in the hope that it will be useful,
  17  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  *     GNU General Public License for more details.
  20  *
  21  * Or, alternatively,
  22  *
  23  *  b) Permission is hereby granted, free of charge, to any person
  24  *     obtaining a copy of this software and associated documentation
  25  *     files (the "Software"), to deal in the Software without
  26  *     restriction, including without limitation the rights to use,
  27  *     copy, modify, merge, publish, distribute, sublicense, and/or
  28  *     sell copies of the Software, and to permit persons to whom the
  29  *     Software is furnished to do so, subject to the following
  30  *     conditions:
  31  *
  32  *     The above copyright notice and this permission notice shall be
  33  *     included in all copies or substantial portions of the Software.
  34  *
  35  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  36  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  37  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  38  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  39  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  40  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  41  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  42  *     OTHER DEALINGS IN THE SOFTWARE.
  43  */
  44
  45 #include <dt-bindings/interrupt-controller/arm-gic.h>
  46
  47 #include <dt-bindings/clock/sun8i-a23-a33-ccu.h>
  48 #include <dt-bindings/reset/sun8i-a23-a33-ccu.h>
  49
  50 / {
  51         interrupt-parent = <&gic>;
  52         #address-cells = <1>;
  53         #size-cells = <1>;
  54
  55         chosen {
  56                 #address-cells = <1>;
  57                 #size-cells = <1>;
  58                 ranges;
  59
  60                 simplefb_lcd: framebuffer-lcd0 {
  61                         compatible = "allwinner,simple-framebuffer",
  62                                      "simple-framebuffer";
  63                         allwinner,pipeline = "de_be0-lcd0";
  64                         clocks = <&ccu CLK_BUS_LCD>, <&ccu CLK_BUS_DE_BE>,
  65                                  <&ccu CLK_LCD_CH0>, <&ccu CLK_DE_BE>,
  66                                  <&ccu CLK_DRAM_DE_BE>, <&ccu CLK_DRC>;
  67                         status = "disabled";
  68                 };
  69         };
  70
  71         de: display-engine {
  72                 /* compatible gets set in SoC specific dtsi file */
  73                 allwinner,pipelines = <&fe0>;
  74                 status = "disabled";
  75         };
  76
  77         timer {
  78                 compatible = "arm,armv7-timer";
  79                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  80                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  81                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  82                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
  83                 clock-frequency = <24000000>;
  84                 arm,cpu-registers-not-fw-configured;
  85         };
  86
  87         cpus {
  88                 enable-method = "allwinner,sun8i-a23";
  89                 #address-cells = <1>;
  90                 #size-cells = <0>;
  91
  92                 cpu0: cpu@0 {
  93                         compatible = "arm,cortex-a7";
  94                         device_type = "cpu";
  95                         reg = <0>;
  96                 };
  97
  98                 cpu@1 {
  99                         compatible = "arm,cortex-a7";
 100                         device_type = "cpu";
 101                         reg = <1>;
 102                 };
 103         };
 104
 105         clocks {
 106                 #address-cells = <1>;
 107                 #size-cells = <1>;
 108                 ranges;
 109
 110                 osc24M: osc24M_clk {
 111                         #clock-cells = <0>;
 112                         compatible = "fixed-clock";
 113                         clock-frequency = <24000000>;
 114                         clock-accuracy = <50000>;
 115                         clock-output-names = "osc24M";
 116                 };
 117
 118                 ext_osc32k: ext_osc32k_clk {
 119                         #clock-cells = <0>;
 120                         compatible = "fixed-clock";
 121                         clock-frequency = <32768>;
 122                         clock-accuracy = <50000>;
 123                         clock-output-names = "ext-osc32k";
 124                 };
 125         };
 126
 127         soc {
 128                 compatible = "simple-bus";
 129                 #address-cells = <1>;
 130                 #size-cells = <1>;
 131                 ranges;
 132
 133                 system-control@1c00000 {
 134                         compatible = "allwinner,sun8i-a23-system-control";
 135                         reg = <0x01c00000 0x30>;
 136                         #address-cells = <1>;
 137                         #size-cells = <1>;
 138                         ranges;
 139
 140                         sram_c: sram@1d00000 {
 141                                 compatible = "mmio-sram";
 142                                 reg = <0x01d00000 0x80000>;
 143                                 #address-cells = <1>;
 144                                 #size-cells = <1>;
 145                                 ranges = <0 0x01d00000 0x80000>;
 146
 147                                 ve_sram: sram-section@0 {
 148                                         compatible = "allwinner,sun8i-a23-sram-c1",
 149                                                      "allwinner,sun4i-a10-sram-c1";
 150                                         reg = <0x000000 0x80000>;
 151                                 };
 152                         };
 153                 };
 154
 155                 dma: dma-controller@1c02000 {
 156                         compatible = "allwinner,sun8i-a23-dma";
 157                         reg = <0x01c02000 0x1000>;
 158                         interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
 159                         clocks = <&ccu CLK_BUS_DMA>;
 160                         resets = <&ccu RST_BUS_DMA>;
 161                         #dma-cells = <1>;
 162                 };
 163
 164                 nfc: nand-controller@1c03000 {
 165                         compatible = "allwinner,sun8i-a23-nand-controller";
 166                         reg = <0x01c03000 0x1000>;
 167                         interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
 168                         clocks = <&ccu CLK_BUS_NAND>, <&ccu CLK_NAND>;
 169                         clock-names = "ahb", "mod";
 170                         resets = <&ccu RST_BUS_NAND>;
 171                         reset-names = "ahb";
 172                         dmas = <&dma 5>;
 173                         dma-names = "rxtx";
 174                         pinctrl-names = "default";
 175                         pinctrl-0 = <&nand_pins &nand_cs0_pin &nand_rb0_pin>;
 176                         status = "disabled";
 177                         #address-cells = <1>;
 178                         #size-cells = <0>;
 179                 };
 180
 181                 tcon0: lcd-controller@1c0c000 {
 182                         /* compatible gets set in SoC specific dtsi file */
 183                         reg = <0x01c0c000 0x1000>;
 184                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 185                         dmas = <&dma 12>;
 186                         clocks = <&ccu CLK_BUS_LCD>,
 187                                  <&ccu CLK_LCD_CH0>,
 188                                  <&ccu 13>;
 189                         clock-names = "ahb",
 190                                       "tcon-ch0",
 191                                       "lvds-alt";
 192                         clock-output-names = "tcon-pixel-clock";
 193                         #clock-cells = <0>;
 194                         resets = <&ccu RST_BUS_LCD>,
 195                                  <&ccu RST_BUS_LVDS>;
 196                         reset-names = "lcd",
 197                                       "lvds";
 198                         status = "disabled";
 199
 200                         ports {
 201                                 #address-cells = <1>;
 202                                 #size-cells = <0>;
 203
 204                                 tcon0_in: port@0 {
 205                                         reg = <0>;
 206
 207                                         tcon0_in_drc0: endpoint {
 208                                                 remote-endpoint = <&drc0_out_tcon0>;
 209                                         };
 210                                 };
 211
 212                                 tcon0_out: port@1 {
 213                                         reg = <1>;
 214                                 };
 215                         };
 216                 };
 217
 218                 mmc0: mmc@1c0f000 {
 219                         compatible = "allwinner,sun7i-a20-mmc";
 220                         reg = <0x01c0f000 0x1000>;
 221                         clocks = <&ccu CLK_BUS_MMC0>,
 222                                  <&ccu CLK_MMC0>,
 223                                  <&ccu CLK_MMC0_OUTPUT>,
 224                                  <&ccu CLK_MMC0_SAMPLE>;
 225                         clock-names = "ahb",
 226                                       "mmc",
 227                                       "output",
 228                                       "sample";
 229                         resets = <&ccu RST_BUS_MMC0>;
 230                         reset-names = "ahb";
 231                         interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 232                         pinctrl-names = "default";
 233                         pinctrl-0 = <&mmc0_pins>;
 234                         status = "disabled";
 235                         #address-cells = <1>;
 236                         #size-cells = <0>;
 237                 };
 238
 239                 mmc1: mmc@1c10000 {
 240                         compatible = "allwinner,sun7i-a20-mmc";
 241                         reg = <0x01c10000 0x1000>;
 242                         clocks = <&ccu CLK_BUS_MMC1>,
 243                                  <&ccu CLK_MMC1>,
 244                                  <&ccu CLK_MMC1_OUTPUT>,
 245                                  <&ccu CLK_MMC1_SAMPLE>;
 246                         clock-names = "ahb",
 247                                       "mmc",
 248                                       "output",
 249                                       "sample";
 250                         resets = <&ccu RST_BUS_MMC1>;
 251                         reset-names = "ahb";
 252                         interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 253                         status = "disabled";
 254                         #address-cells = <1>;
 255                         #size-cells = <0>;
 256                 };
 257
 258                 mmc2: mmc@1c11000 {
 259                         compatible = "allwinner,sun7i-a20-mmc";
 260                         reg = <0x01c11000 0x1000>;
 261                         clocks = <&ccu CLK_BUS_MMC2>,
 262                                  <&ccu CLK_MMC2>,
 263                                  <&ccu CLK_MMC2_OUTPUT>,
 264                                  <&ccu CLK_MMC2_SAMPLE>;
 265                         clock-names = "ahb",
 266                                       "mmc",
 267                                       "output",
 268                                       "sample";
 269                         resets = <&ccu RST_BUS_MMC2>;
 270                         reset-names = "ahb";
 271                         interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 272                         status = "disabled";
 273                         #address-cells = <1>;
 274                         #size-cells = <0>;
 275                 };
 276
 277                 usb_otg: usb@1c19000 {
 278                         /* compatible gets set in SoC specific dtsi file */
 279                         reg = <0x01c19000 0x0400>;
 280                         clocks = <&ccu CLK_BUS_OTG>;
 281                         resets = <&ccu RST_BUS_OTG>;
 282                         interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 283                         interrupt-names = "mc";
 284                         phys = <&usbphy 0>;
 285                         phy-names = "usb";
 286                         extcon = <&usbphy 0>;
 287                         dr_mode = "otg";
 288                         status = "disabled";
 289                 };
 290
 291                 usbphy: phy@1c19400 {
 292                         /*
 293                          * compatible and address regions get set in
 294                          * SoC specific dtsi file
 295                          */
 296                         clocks = <&ccu CLK_USB_PHY0>,
 297                                  <&ccu CLK_USB_PHY1>;
 298                         clock-names = "usb0_phy",
 299                                       "usb1_phy";
 300                         resets = <&ccu RST_USB_PHY0>,
 301                                  <&ccu RST_USB_PHY1>;
 302                         reset-names = "usb0_reset",
 303                                       "usb1_reset";
 304                         status = "disabled";
 305                         #phy-cells = <1>;
 306                 };
 307
 308                 ehci0: usb@1c1a000 {
 309                         compatible = "allwinner,sun8i-a23-ehci", "generic-ehci";
 310                         reg = <0x01c1a000 0x100>;
 311                         interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 312                         clocks = <&ccu CLK_BUS_EHCI>;
 313                         resets = <&ccu RST_BUS_EHCI>;
 314                         phys = <&usbphy 1>;
 315                         phy-names = "usb";
 316                         status = "disabled";
 317                 };
 318
 319                 ohci0: usb@1c1a400 {
 320                         compatible = "allwinner,sun8i-a23-ohci", "generic-ohci";
 321                         reg = <0x01c1a400 0x100>;
 322                         interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 323                         clocks = <&ccu CLK_BUS_OHCI>, <&ccu CLK_USB_OHCI>;
 324                         resets = <&ccu RST_BUS_OHCI>;
 325                         phys = <&usbphy 1>;
 326                         phy-names = "usb";
 327                         status = "disabled";
 328                 };
 329
 330                 ccu: clock@1c20000 {
 331                         reg = <0x01c20000 0x400>;
 332                         clocks = <&osc24M>, <&rtc 0>;
 333                         clock-names = "hosc", "losc";
 334                         #clock-cells = <1>;
 335                         #reset-cells = <1>;
 336                 };
 337
 338                 pio: pinctrl@1c20800 {
 339                         /* compatible gets set in SoC specific dtsi file */
 340                         reg = <0x01c20800 0x400>;
 341                         interrupt-parent = <&r_intc>;
 342                         /* interrupts get set in SoC specific dtsi file */
 343                         clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&rtc 0>;
 344                         clock-names = "apb", "hosc", "losc";
 345                         gpio-controller;
 346                         interrupt-controller;
 347                         #interrupt-cells = <3>;
 348                         #gpio-cells = <3>;
 349
 350                         i2c0_pins: i2c0-pins {
 351                                 pins = "PH2", "PH3";
 352                                 function = "i2c0";
 353                         };
 354
 355                         i2c1_pins: i2c1-pins {
 356                                 pins = "PH4", "PH5";
 357                                 function = "i2c1";
 358                         };
 359
 360                         i2c2_pins: i2c2-pins {
 361                                 pins = "PE12", "PE13";
 362                                 function = "i2c2";
 363                         };
 364
 365                         lcd_rgb666_pins: lcd-rgb666-pins {
 366                                 pins = "PD2", "PD3", "PD4", "PD5", "PD6", "PD7",
 367                                        "PD10", "PD11", "PD12", "PD13", "PD14", "PD15",
 368                                        "PD18", "PD19", "PD20", "PD21", "PD22", "PD23",
 369                                        "PD24", "PD25", "PD26", "PD27";
 370                                 function = "lcd0";
 371                         };
 372
 373                         mmc0_pins: mmc0-pins {
 374                                 pins = "PF0", "PF1", "PF2",
 375                                        "PF3", "PF4", "PF5";
 376                                 function = "mmc0";
 377                                 drive-strength = <30>;
 378                                 bias-pull-up;
 379                         };
 380
 381                         mmc1_pg_pins: mmc1-pg-pins {
 382                                 pins = "PG0", "PG1", "PG2",
 383                                        "PG3", "PG4", "PG5";
 384                                 function = "mmc1";
 385                                 drive-strength = <30>;
 386                                 bias-pull-up;
 387                         };
 388
 389                         mmc2_8bit_pins: mmc2-8bit-pins {
 390                                 pins = "PC5", "PC6", "PC8",
 391                                        "PC9", "PC10", "PC11",
 392                                        "PC12", "PC13", "PC14",
 393                                        "PC15", "PC16";
 394                                 function = "mmc2";
 395                                 drive-strength = <30>;
 396                                 bias-pull-up;
 397                         };
 398
 399                         nand_pins: nand-pins {
 400                                 pins = "PC0", "PC1", "PC2", "PC5",
 401                                        "PC8", "PC9", "PC10", "PC11",
 402                                        "PC12", "PC13", "PC14", "PC15";
 403                                 function = "nand0";
 404                         };
 405
 406                         nand_cs0_pin: nand-cs0-pin {
 407                                 pins = "PC4";
 408                                 function = "nand0";
 409                                 bias-pull-up;
 410                         };
 411
 412                         nand_cs1_pin: nand-cs1-pin {
 413                                 pins = "PC3";
 414                                 function = "nand0";
 415                                 bias-pull-up;
 416                         };
 417
 418                         nand_rb0_pin: nand-rb0-pin {
 419                                 pins = "PC6";
 420                                 function = "nand0";
 421                                 bias-pull-up;
 422                         };
 423
 424                         nand_rb1_pin: nand-rb1-pin {
 425                                 pins = "PC7";
 426                                 function = "nand0";
 427                                 bias-pull-up;
 428                         };
 429
 430                         pwm0_pin: pwm0-pin {
 431                                 pins = "PH0";
 432                                 function = "pwm0";
 433                         };
 434
 435                         uart0_pf_pins: uart0-pf-pins {
 436                                 pins = "PF2", "PF4";
 437                                 function = "uart0";
 438                         };
 439
 440                         uart1_pg_pins: uart1-pg-pins {
 441                                 pins = "PG6", "PG7";
 442                                 function = "uart1";
 443                         };
 444
 445                         uart1_cts_rts_pg_pins: uart1-cts-rts-pg-pins {
 446                                 pins = "PG8", "PG9";
 447                                 function = "uart1";
 448                         };
 449                 };
 450
 451                 timer@1c20c00 {
 452                         compatible = "allwinner,sun8i-a23-timer";
 453                         reg = <0x01c20c00 0xa0>;
 454                         interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
 455                                      <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 456                         clocks = <&osc24M>;
 457                 };
 458
 459                 wdt0: watchdog@1c20ca0 {
 460                         compatible = "allwinner,sun6i-a31-wdt";
 461                         reg = <0x01c20ca0 0x20>;
 462                         interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 463                         clocks = <&osc24M>;
 464                 };
 465
 466                 pwm: pwm@1c21400 {
 467                         compatible = "allwinner,sun7i-a20-pwm";
 468                         reg = <0x01c21400 0xc>;
 469                         clocks = <&osc24M>;
 470                         #pwm-cells = <3>;
 471                         status = "disabled";
 472                 };
 473
 474                 lradc: lradc@1c22800 {
 475                         compatible = "allwinner,sun4i-a10-lradc-keys";
 476                         reg = <0x01c22800 0x100>;
 477                         interrupt-parent = <&r_intc>;
 478                         interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 479                         status = "disabled";
 480                 };
 481
 482                 uart0: serial@1c28000 {
 483                         compatible = "snps,dw-apb-uart";
 484                         reg = <0x01c28000 0x400>;
 485                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
 486                         reg-shift = <2>;
 487                         reg-io-width = <4>;
 488                         clocks = <&ccu CLK_BUS_UART0>;
 489                         resets = <&ccu RST_BUS_UART0>;
 490                         dmas = <&dma 6>, <&dma 6>;
 491                         dma-names = "rx", "tx";
 492                         status = "disabled";
 493                 };
 494
 495                 uart1: serial@1c28400 {
 496                         compatible = "snps,dw-apb-uart";
 497                         reg = <0x01c28400 0x400>;
 498                         interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 499                         reg-shift = <2>;
 500                         reg-io-width = <4>;
 501                         clocks = <&ccu CLK_BUS_UART1>;
 502                         resets = <&ccu RST_BUS_UART1>;
 503                         dmas = <&dma 7>, <&dma 7>;
 504                         dma-names = "rx", "tx";
 505                         status = "disabled";
 506                 };
 507
 508                 uart2: serial@1c28800 {
 509                         compatible = "snps,dw-apb-uart";
 510                         reg = <0x01c28800 0x400>;
 511                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
 512                         reg-shift = <2>;
 513                         reg-io-width = <4>;
 514                         clocks = <&ccu CLK_BUS_UART2>;
 515                         resets = <&ccu RST_BUS_UART2>;
 516                         dmas = <&dma 8>, <&dma 8>;
 517                         dma-names = "rx", "tx";
 518                         status = "disabled";
 519                 };
 520
 521                 uart3: serial@1c28c00 {
 522                         compatible = "snps,dw-apb-uart";
 523                         reg = <0x01c28c00 0x400>;
 524                         interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 525                         reg-shift = <2>;
 526                         reg-io-width = <4>;
 527                         clocks = <&ccu CLK_BUS_UART3>;
 528                         resets = <&ccu RST_BUS_UART3>;
 529                         dmas = <&dma 9>, <&dma 9>;
 530                         dma-names = "rx", "tx";
 531                         status = "disabled";
 532                 };
 533
 534                 uart4: serial@1c29000 {
 535                         compatible = "snps,dw-apb-uart";
 536                         reg = <0x01c29000 0x400>;
 537                         interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 538                         reg-shift = <2>;
 539                         reg-io-width = <4>;
 540                         clocks = <&ccu CLK_BUS_UART4>;
 541                         resets = <&ccu RST_BUS_UART4>;
 542                         dmas = <&dma 10>, <&dma 10>;
 543                         dma-names = "rx", "tx";
 544                         status = "disabled";
 545                 };
 546
 547                 i2c0: i2c@1c2ac00 {
 548                         compatible = "allwinner,sun6i-a31-i2c";
 549                         reg = <0x01c2ac00 0x400>;
 550                         interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
 551                         clocks = <&ccu CLK_BUS_I2C0>;
 552                         resets = <&ccu RST_BUS_I2C0>;
 553                         pinctrl-names = "default";
 554                         pinctrl-0 = <&i2c0_pins>;
 555                         status = "disabled";
 556                         #address-cells = <1>;
 557                         #size-cells = <0>;
 558                 };
 559
 560                 i2c1: i2c@1c2b000 {
 561                         compatible = "allwinner,sun6i-a31-i2c";
 562                         reg = <0x01c2b000 0x400>;
 563                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 564                         clocks = <&ccu CLK_BUS_I2C1>;
 565                         resets = <&ccu RST_BUS_I2C1>;
 566                         pinctrl-names = "default";
 567                         pinctrl-0 = <&i2c1_pins>;
 568                         status = "disabled";
 569                         #address-cells = <1>;
 570                         #size-cells = <0>;
 571                 };
 572
 573                 i2c2: i2c@1c2b400 {
 574                         compatible = "allwinner,sun6i-a31-i2c";
 575                         reg = <0x01c2b400 0x400>;
 576                         interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 577                         clocks = <&ccu CLK_BUS_I2C2>;
 578                         resets = <&ccu RST_BUS_I2C2>;
 579                         pinctrl-names = "default";
 580                         pinctrl-0 = <&i2c2_pins>;
 581                         status = "disabled";
 582                         #address-cells = <1>;
 583                         #size-cells = <0>;
 584                 };
 585
 586                 mali: gpu@1c40000 {
 587                         compatible = "allwinner,sun8i-a23-mali",
 588                                      "allwinner,sun7i-a20-mali", "arm,mali-400";
 589                         reg = <0x01c40000 0x10000>;
 590                         interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
 591                                      <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
 592                                      <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
 593                                      <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
 594                                      <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
 595                                      <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
 596                                      <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
 597                         interrupt-names = "gp",
 598                                           "gpmmu",
 599                                           "pp0",
 600                                           "ppmmu0",
 601                                           "pp1",
 602                                           "ppmmu1",
 603                                           "pmu";
 604                         clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>;
 605                         clock-names = "bus", "core";
 606                         resets = <&ccu RST_BUS_GPU>;
 607                         #cooling-cells = <2>;
 608
 609                         assigned-clocks = <&ccu CLK_GPU>;
 610                         assigned-clock-rates = <384000000>;
 611                 };
 612
 613                 gic: interrupt-controller@1c81000 {
 614                         compatible = "arm,gic-400";
 615                         reg = <0x01c81000 0x1000>,
 616                               <0x01c82000 0x2000>,
 617                               <0x01c84000 0x2000>,
 618                               <0x01c86000 0x2000>;
 619                         interrupt-controller;
 620                         #interrupt-cells = <3>;
 621                         interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 622                 };
 623
 624                 fe0: display-frontend@1e00000 {
 625                         /* compatible gets set in SoC specific dtsi file */
 626                         reg = <0x01e00000 0x20000>;
 627                         interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
 628                         clocks = <&ccu CLK_BUS_DE_FE>, <&ccu CLK_DE_FE>,
 629                                  <&ccu CLK_DRAM_DE_FE>;
 630                         clock-names = "ahb", "mod",
 631                                       "ram";
 632                         resets = <&ccu RST_BUS_DE_FE>;
 633
 634                         ports {
 635                                 #address-cells = <1>;
 636                                 #size-cells = <0>;
 637
 638                                 fe0_out: port@1 {
 639                                         reg = <1>;
 640
 641                                         fe0_out_be0: endpoint {
 642                                                 remote-endpoint = <&be0_in_fe0>;
 643                                         };
 644                                 };
 645                         };
 646                 };
 647
 648                 be0: display-backend@1e60000 {
 649                         /* compatible gets set in SoC specific dtsi file */
 650                         reg = <0x01e60000 0x10000>;
 651                         interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
 652                         clocks = <&ccu CLK_BUS_DE_BE>, <&ccu CLK_DE_BE>,
 653                                  <&ccu CLK_DRAM_DE_BE>;
 654                         clock-names = "ahb", "mod",
 655                                       "ram";
 656                         resets = <&ccu RST_BUS_DE_BE>;
 657
 658                         ports {
 659                                 #address-cells = <1>;
 660                                 #size-cells = <0>;
 661
 662                                 be0_in: port@0 {
 663                                         reg = <0>;
 664
 665                                         be0_in_fe0: endpoint {
 666                                                 remote-endpoint = <&fe0_out_be0>;
 667                                         };
 668                                 };
 669
 670                                 be0_out: port@1 {
 671                                         reg = <1>;
 672
 673                                         be0_out_drc0: endpoint {
 674                                                 remote-endpoint = <&drc0_in_be0>;
 675                                         };
 676                                 };
 677                         };
 678                 };
 679
 680                 drc0: drc@1e70000 {
 681                         /* compatible gets set in SoC specific dtsi file */
 682                         reg = <0x01e70000 0x10000>;
 683                         interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
 684                         clocks = <&ccu CLK_BUS_DRC>, <&ccu CLK_DRC>,
 685                                  <&ccu CLK_DRAM_DRC>;
 686                         clock-names = "ahb", "mod", "ram";
 687                         resets = <&ccu RST_BUS_DRC>;
 688
 689                         ports {
 690                                 #address-cells = <1>;
 691                                 #size-cells = <0>;
 692
 693                                 drc0_in: port@0 {
 694                                         reg = <0>;
 695
 696                                         drc0_in_be0: endpoint {
 697                                                 remote-endpoint = <&be0_out_drc0>;
 698                                         };
 699                                 };
 700
 701                                 drc0_out: port@1 {
 702                                         reg = <1>;
 703
 704                                         drc0_out_tcon0: endpoint {
 705                                                 remote-endpoint = <&tcon0_in_drc0>;
 706                                         };
 707                                 };
 708                         };
 709                 };
 710
 711                 rtc: rtc@1f00000 {
 712                         compatible = "allwinner,sun8i-a23-rtc";
 713                         reg = <0x01f00000 0x400>;
 714                         interrupt-parent = <&r_intc>;
 715                         interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
 716                                      <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 717                         clock-output-names = "osc32k", "osc32k-out";
 718                         clocks = <&ext_osc32k>;
 719                         #clock-cells = <1>;
 720                 };
 721
 722                 r_intc: interrupt-controller@1f00c00 {
 723                         compatible = "allwinner,sun6i-a31-r-intc";
 724                         interrupt-controller;
 725                         #interrupt-cells = <3>;
 726                         reg = <0x01f00c00 0x400>;
 727                         interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 728                 };
 729
 730                 prcm@1f01400 {
 731                         compatible = "allwinner,sun8i-a23-prcm";
 732                         reg = <0x01f01400 0x200>;
 733
 734                         ar100: ar100_clk {
 735                                 compatible = "fixed-factor-clock";
 736                                 #clock-cells = <0>;
 737                                 clock-div = <1>;
 738                                 clock-mult = <1>;
 739                                 clocks = <&osc24M>;
 740                                 clock-output-names = "ar100";
 741                         };
 742
 743                         ahb0: ahb0_clk {
 744                                 compatible = "fixed-factor-clock";
 745                                 #clock-cells = <0>;
 746                                 clock-div = <1>;
 747                                 clock-mult = <1>;
 748                                 clocks = <&ar100>;
 749                                 clock-output-names = "ahb0";
 750                         };
 751
 752                         apb0: apb0_clk {
 753                                 compatible = "allwinner,sun8i-a23-apb0-clk";
 754                                 #clock-cells = <0>;
 755                                 clocks = <&ahb0>;
 756                                 clock-output-names = "apb0";
 757                         };
 758
 759                         apb0_gates: apb0_gates_clk {
 760                                 compatible = "allwinner,sun8i-a23-apb0-gates-clk";
 761                                 #clock-cells = <1>;
 762                                 clocks = <&apb0>;
 763                                 clock-output-names = "apb0_pio", "apb0_timer",
 764                                                 "apb0_rsb", "apb0_uart",
 765                                                 "apb0_i2c";
 766                         };
 767
 768                         apb0_rst: apb0_rst {
 769                                 compatible = "allwinner,sun6i-a31-clock-reset";
 770                                 #reset-cells = <1>;
 771                         };
 772
 773                         codec_analog: codec-analog {
 774                                 compatible = "allwinner,sun8i-a23-codec-analog";
 775                         };
 776                 };
 777
 778                 cpucfg@1f01c00 {
 779                         compatible = "allwinner,sun8i-a23-cpuconfig";
 780                         reg = <0x01f01c00 0x300>;
 781                 };
 782
 783                 r_uart: serial@1f02800 {
 784                         compatible = "snps,dw-apb-uart";
 785                         reg = <0x01f02800 0x400>;
 786                         interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 787                         reg-shift = <2>;
 788                         reg-io-width = <4>;
 789                         clocks = <&apb0_gates 4>;
 790                         resets = <&apb0_rst 4>;
 791                         status = "disabled";
 792                 };
 793
 794                 r_i2c: i2c@1f02400 {
 795                         compatible = "allwinner,sun8i-a23-i2c",
 796                                      "allwinner,sun6i-a31-i2c";
 797                         reg = <0x01f02400 0x400>;
 798                         interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 799                         pinctrl-names = "default";
 800                         pinctrl-0 = <&r_i2c_pins>;
 801                         clocks = <&apb0_gates 6>;
 802                         resets = <&apb0_rst 6>;
 803                         status = "disabled";
 804                         #address-cells = <1>;
 805                         #size-cells = <0>;
 806                 };
 807
 808                 r_pio: pinctrl@1f02c00 {
 809                         compatible = "allwinner,sun8i-a23-r-pinctrl";
 810                         reg = <0x01f02c00 0x400>;
 811                         interrupt-parent = <&r_intc>;
 812                         interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 813                         clocks = <&apb0_gates 0>, <&osc24M>, <&rtc 0>;
 814                         clock-names = "apb", "hosc", "losc";
 815                         resets = <&apb0_rst 0>;
 816                         gpio-controller;
 817                         interrupt-controller;
 818                         #interrupt-cells = <3>;
 819                         #gpio-cells = <3>;
 820
 821                         r_i2c_pins: r-i2c-pins {
 822                                 pins = "PL0", "PL1";
 823                                 function = "s_i2c";
 824                                 bias-pull-up;
 825                         };
 826
 827                         r_rsb_pins: r-rsb-pins {
 828                                 pins = "PL0", "PL1";
 829                                 function = "s_rsb";
 830                                 drive-strength = <20>;
 831                                 bias-pull-up;
 832                         };
 833
 834                         r_uart_pins_a: r-uart-pins {
 835                                 pins = "PL2", "PL3";
 836                                 function = "s_uart";
 837                         };
 838                 };
 839
 840                 r_rsb: rsb@1f03400 {
 841                         compatible = "allwinner,sun8i-a23-rsb";
 842                         reg = <0x01f03400 0x400>;
 843                         interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 844                         clocks = <&apb0_gates 3>;
 845                         clock-frequency = <3000000>;
 846                         resets = <&apb0_rst 3>;
 847                         pinctrl-names = "default";
 848                         pinctrl-0 = <&r_rsb_pins>;
 849                         status = "disabled";
 850                         #address-cells = <1>;
 851                         #size-cells = <0>;
 852                 };
 853         };
 854 };