1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2015 STMicroelectronics R&D Limited
5 #include <dt-bindings/clock/stih418-clks.h>
8 * Fixed 30MHz oscillator inputs to SoC
10 clk_sysin: clk-sysin {
12 compatible = "fixed-clock";
13 clock-frequency = <30000000>;
14 clock-output-names = "CLK_SYSIN";
17 clk_tmdsout_hdmi: clk-tmdsout-hdmi {
19 compatible = "fixed-clock";
20 clock-frequency = <0>;
28 compatible = "st,stih418-clk", "simple-bus";
34 compatible = "st,clkgen-c32";
35 reg = <0x92b0000 0xffff>;
37 clockgen_a9_pll: clockgen-a9-pll {
39 compatible = "st,stih418-clkgen-plla9";
41 clocks = <&clk_sysin>;
46 * ARM CPU related clocks.
48 clk_m_a9: clk-m-a9@92b0000 {
50 compatible = "st,stih407-clkgen-a9-mux", "st,clkgen-mux";
51 reg = <0x92b0000 0x10000>;
53 clocks = <&clockgen_a9_pll 0>,
55 <&clk_s_c0_flexgen 13>,
56 <&clk_m_a9_ext2f_div2>;
59 * ARM Peripheral clock for timers
61 arm_periph_clk: clk-m-a9-periphs {
63 compatible = "fixed-factor-clock";
71 compatible = "st,clkgen-c32";
72 reg = <0x90ff000 0x1000>;
74 clk_s_a0_pll: clk-s-a0-pll {
76 compatible = "st,clkgen-pll0-a0";
78 clocks = <&clk_sysin>;
81 clk_s_a0_flexgen: clk-s-a0-flexgen {
82 compatible = "st,flexgen", "st,flexgen-stih410-a0";
86 clocks = <&clk_s_a0_pll 0>,
91 clk_s_c0_quadfs: clk-s-c0-quadfs@9103000 {
93 compatible = "st,quadfs-pll";
94 reg = <0x9103000 0x1000>;
96 clocks = <&clk_sysin>;
99 clk_s_c0: clockgen-c@9103000 {
100 compatible = "st,clkgen-c32";
101 reg = <0x9103000 0x1000>;
103 clk_s_c0_pll0: clk-s-c0-pll0 {
105 compatible = "st,clkgen-pll0-c0";
107 clocks = <&clk_sysin>;
110 clk_s_c0_pll1: clk-s-c0-pll1 {
112 compatible = "st,clkgen-pll1-c0";
114 clocks = <&clk_sysin>;
117 clk_s_c0_flexgen: clk-s-c0-flexgen {
119 compatible = "st,flexgen", "st,flexgen-stih418-c0";
121 clocks = <&clk_s_c0_pll0 0>,
123 <&clk_s_c0_quadfs 0>,
124 <&clk_s_c0_quadfs 1>,
125 <&clk_s_c0_quadfs 2>,
126 <&clk_s_c0_quadfs 3>,
130 * ARM Peripheral clock for timers
132 clk_m_a9_ext2f_div2: clk-m-a9-ext2f-div2s {
134 compatible = "fixed-factor-clock";
136 clocks = <&clk_s_c0_flexgen 13>;
138 clock-output-names = "clk-m-a9-ext2f-div2";
146 clk_s_d0_quadfs: clk-s-d0-quadfs@9104000 {
148 compatible = "st,quadfs-d0";
149 reg = <0x9104000 0x1000>;
151 clocks = <&clk_sysin>;
154 clockgen-d0@9104000 {
155 compatible = "st,clkgen-c32";
156 reg = <0x9104000 0x1000>;
158 clk_s_d0_flexgen: clk-s-d0-flexgen {
160 compatible = "st,flexgen", "st,flexgen-stih410-d0";
162 clocks = <&clk_s_d0_quadfs 0>,
163 <&clk_s_d0_quadfs 1>,
164 <&clk_s_d0_quadfs 2>,
165 <&clk_s_d0_quadfs 3>,
170 clk_s_d2_quadfs: clk-s-d2-quadfs@9106000 {
172 compatible = "st,quadfs-d2";
173 reg = <0x9106000 0x1000>;
175 clocks = <&clk_sysin>;
178 clockgen-d2@9106000 {
179 compatible = "st,clkgen-c32";
180 reg = <0x9106000 0x1000>;
182 clk_s_d2_flexgen: clk-s-d2-flexgen {
184 compatible = "st,flexgen", "st,flexgen-stih418-d2";
186 clocks = <&clk_s_d2_quadfs 0>,
187 <&clk_s_d2_quadfs 1>,
188 <&clk_s_d2_quadfs 2>,
189 <&clk_s_d2_quadfs 3>,
196 clk_s_d3_quadfs: clk-s-d3-quadfs@9107000 {
198 compatible = "st,quadfs-d3";
199 reg = <0x9107000 0x1000>;
201 clocks = <&clk_sysin>;
204 clockgen-d3@9107000 {
205 compatible = "st,clkgen-c32";
206 reg = <0x9107000 0x1000>;
208 clk_s_d3_flexgen: clk-s-d3-flexgen {
210 compatible = "st,flexgen", "st,flexgen-stih407-d3";
212 clocks = <&clk_s_d3_quadfs 0>,
213 <&clk_s_d3_quadfs 1>,
214 <&clk_s_d3_quadfs 2>,
215 <&clk_s_d3_quadfs 3>,