1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2014 STMicroelectronics R&D Limited
5 #include <dt-bindings/clock/stih407-clks.h>
8 * Fixed 30MHz oscillator inputs to SoC
10 clk_sysin: clk-sysin {
12 compatible = "fixed-clock";
13 clock-frequency = <30000000>;
16 clk_tmdsout_hdmi: clk-tmdsout-hdmi {
18 compatible = "fixed-clock";
19 clock-frequency = <0>;
31 compatible = "st,clkgen-c32";
32 reg = <0x92b0000 0xffff>;
34 clockgen_a9_pll: clockgen-a9-pll {
36 compatible = "st,stih407-clkgen-plla9";
38 clocks = <&clk_sysin>;
43 * ARM CPU related clocks.
45 clk_m_a9: clk-m-a9@92b0000 {
47 compatible = "st,stih407-clkgen-a9-mux";
48 reg = <0x92b0000 0x10000>;
50 clocks = <&clockgen_a9_pll 0>,
52 <&clk_s_c0_flexgen 13>,
53 <&clk_m_a9_ext2f_div2>;
57 * ARM Peripheral clock for timers
59 arm_periph_clk: clk-m-a9-periphs {
61 compatible = "fixed-factor-clock";
70 compatible = "st,clkgen-c32";
71 reg = <0x90ff000 0x1000>;
73 clk_s_a0_pll: clk-s-a0-pll {
75 compatible = "st,clkgen-pll0-a0";
77 clocks = <&clk_sysin>;
80 clk_s_a0_flexgen: clk-s-a0-flexgen {
81 compatible = "st,flexgen", "st,flexgen-stih407-a0";
85 clocks = <&clk_s_a0_pll 0>,
90 clk_s_c0_quadfs: clk-s-c0-quadfs@9103000 {
92 compatible = "st,quadfs-pll";
93 reg = <0x9103000 0x1000>;
95 clocks = <&clk_sysin>;
98 clk_s_c0: clockgen-c@9103000 {
99 compatible = "st,clkgen-c32";
100 reg = <0x9103000 0x1000>;
102 clk_s_c0_pll0: clk-s-c0-pll0 {
104 compatible = "st,clkgen-pll0-c0";
106 clocks = <&clk_sysin>;
109 clk_s_c0_pll1: clk-s-c0-pll1 {
111 compatible = "st,clkgen-pll1-c0";
113 clocks = <&clk_sysin>;
116 clk_s_c0_flexgen: clk-s-c0-flexgen {
118 compatible = "st,flexgen", "st,flexgen-stih407-c0";
120 clocks = <&clk_s_c0_pll0 0>,
122 <&clk_s_c0_quadfs 0>,
123 <&clk_s_c0_quadfs 1>,
124 <&clk_s_c0_quadfs 2>,
125 <&clk_s_c0_quadfs 3>,
129 * ARM Peripheral clock for timers
131 clk_m_a9_ext2f_div2: clk-m-a9-ext2f-div2s {
133 compatible = "fixed-factor-clock";
135 clocks = <&clk_s_c0_flexgen 13>;
137 clock-output-names = "clk-m-a9-ext2f-div2";
145 clk_s_d0_quadfs: clk-s-d0-quadfs@9104000 {
147 compatible = "st,quadfs-d0";
148 reg = <0x9104000 0x1000>;
150 clocks = <&clk_sysin>;
153 clockgen-d0@9104000 {
154 compatible = "st,clkgen-c32";
155 reg = <0x9104000 0x1000>;
157 clk_s_d0_flexgen: clk-s-d0-flexgen {
159 compatible = "st,flexgen", "st,flexgen-stih407-d0";
161 clocks = <&clk_s_d0_quadfs 0>,
162 <&clk_s_d0_quadfs 1>,
163 <&clk_s_d0_quadfs 2>,
164 <&clk_s_d0_quadfs 3>,
169 clk_s_d2_quadfs: clk-s-d2-quadfs@9106000 {
171 compatible = "st,quadfs-d2";
172 reg = <0x9106000 0x1000>;
174 clocks = <&clk_sysin>;
177 clockgen-d2@9106000 {
178 compatible = "st,clkgen-c32";
179 reg = <0x9106000 0x1000>;
181 clk_s_d2_flexgen: clk-s-d2-flexgen {
183 compatible = "st,flexgen", "st,flexgen-stih407-d2";
185 clocks = <&clk_s_d2_quadfs 0>,
186 <&clk_s_d2_quadfs 1>,
187 <&clk_s_d2_quadfs 2>,
188 <&clk_s_d2_quadfs 3>,
195 clk_s_d3_quadfs: clk-s-d3-quadfs@9107000 {
197 compatible = "st,quadfs-d3";
198 reg = <0x9107000 0x1000>;
200 clocks = <&clk_sysin>;
203 clockgen-d3@9107000 {
204 compatible = "st,clkgen-c32";
205 reg = <0x9107000 0x1000>;
207 clk_s_d3_flexgen: clk-s-d3-flexgen {
209 compatible = "st,flexgen", "st,flexgen-stih407-d3";
211 clocks = <&clk_s_d3_quadfs 0>,
212 <&clk_s_d3_quadfs 1>,
213 <&clk_s_d3_quadfs 2>,
214 <&clk_s_d3_quadfs 3>,