arch/arm/boot/dts/rk3xxx.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Copyright (c) 2013 MundoReader S.L.
   4  * Author: Heiko Stuebner <heiko@sntech.de>
   5  */
   6
   7 #include <dt-bindings/interrupt-controller/irq.h>
   8 #include <dt-bindings/interrupt-controller/arm-gic.h>
   9 #include <dt-bindings/soc/rockchip,boot-mode.h>
  10
  11 / {
  12         #address-cells = <1>;
  13         #size-cells = <1>;
  14
  15         interrupt-parent = <&gic>;
  16
  17         aliases {
  18                 ethernet0 = &emac;
  19                 i2c0 = &i2c0;
  20                 i2c1 = &i2c1;
  21                 i2c2 = &i2c2;
  22                 i2c3 = &i2c3;
  23                 i2c4 = &i2c4;
  24                 serial0 = &uart0;
  25                 serial1 = &uart1;
  26                 serial2 = &uart2;
  27                 serial3 = &uart3;
  28                 spi0 = &spi0;
  29                 spi1 = &spi1;
  30         };
  31
  32         xin24m: oscillator {
  33                 compatible = "fixed-clock";
  34                 clock-frequency = <24000000>;
  35                 #clock-cells = <0>;
  36                 clock-output-names = "xin24m";
  37         };
  38
  39         gpu: gpu@10090000 {
  40                 compatible = "arm,mali-400";
  41                 reg = <0x10090000 0x10000>;
  42                 clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>;
  43                 clock-names = "bus", "core";
  44                 assigned-clocks = <&cru ACLK_GPU>;
  45                 assigned-clock-rates = <100000000>;
  46                 resets = <&cru SRST_GPU>;
  47                 status = "disabled";
  48         };
  49
  50         L2: cache-controller@10138000 {
  51                 compatible = "arm,pl310-cache";
  52                 reg = <0x10138000 0x1000>;
  53                 cache-unified;
  54                 cache-level = <2>;
  55         };
  56
  57         scu@1013c000 {
  58                 compatible = "arm,cortex-a9-scu";
  59                 reg = <0x1013c000 0x100>;
  60         };
  61
  62         global_timer: global-timer@1013c200 {
  63                 compatible = "arm,cortex-a9-global-timer";
  64                 reg = <0x1013c200 0x20>;
  65                 interrupts = <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>;
  66                 clocks = <&cru CORE_PERI>;
  67         };
  68
  69         local_timer: local-timer@1013c600 {
  70                 compatible = "arm,cortex-a9-twd-timer";
  71                 reg = <0x1013c600 0x20>;
  72                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>;
  73                 clocks = <&cru CORE_PERI>;
  74         };
  75
  76         gic: interrupt-controller@1013d000 {
  77                 compatible = "arm,cortex-a9-gic";
  78                 interrupt-controller;
  79                 #interrupt-cells = <3>;
  80                 reg = <0x1013d000 0x1000>,
  81                       <0x1013c100 0x0100>;
  82         };
  83
  84         uart0: serial@10124000 {
  85                 compatible = "snps,dw-apb-uart";
  86                 reg = <0x10124000 0x400>;
  87                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
  88                 reg-shift = <2>;
  89                 reg-io-width = <1>;
  90                 clock-names = "baudclk", "apb_pclk";
  91                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
  92                 status = "disabled";
  93         };
  94
  95         uart1: serial@10126000 {
  96                 compatible = "snps,dw-apb-uart";
  97                 reg = <0x10126000 0x400>;
  98                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
  99                 reg-shift = <2>;
 100                 reg-io-width = <1>;
 101                 clock-names = "baudclk", "apb_pclk";
 102                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 103                 status = "disabled";
 104         };
 105
 106         qos_gpu: qos@1012d000 {
 107                 compatible = "rockchip,rk3066-qos", "syscon";
 108                 reg = <0x1012d000 0x20>;
 109         };
 110
 111         qos_vpu: qos@1012e000 {
 112                 compatible = "rockchip,rk3066-qos", "syscon";
 113                 reg = <0x1012e000 0x20>;
 114         };
 115
 116         qos_lcdc0: qos@1012f000 {
 117                 compatible = "rockchip,rk3066-qos", "syscon";
 118                 reg = <0x1012f000 0x20>;
 119         };
 120
 121         qos_cif0: qos@1012f080 {
 122                 compatible = "rockchip,rk3066-qos", "syscon";
 123                 reg = <0x1012f080 0x20>;
 124         };
 125
 126         qos_ipp: qos@1012f100 {
 127                 compatible = "rockchip,rk3066-qos", "syscon";
 128                 reg = <0x1012f100 0x20>;
 129         };
 130
 131         qos_lcdc1: qos@1012f180 {
 132                 compatible = "rockchip,rk3066-qos", "syscon";
 133                 reg = <0x1012f180 0x20>;
 134         };
 135
 136         qos_cif1: qos@1012f200 {
 137                 compatible = "rockchip,rk3066-qos", "syscon";
 138                 reg = <0x1012f200 0x20>;
 139         };
 140
 141         qos_rga: qos@1012f280 {
 142                 compatible = "rockchip,rk3066-qos", "syscon";
 143                 reg = <0x1012f280 0x20>;
 144         };
 145
 146         usb_otg: usb@10180000 {
 147                 compatible = "rockchip,rk3066-usb", "snps,dwc2";
 148                 reg = <0x10180000 0x40000>;
 149                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 150                 clocks = <&cru HCLK_OTG0>;
 151                 clock-names = "otg";
 152                 dr_mode = "otg";
 153                 g-np-tx-fifo-size = <16>;
 154                 g-rx-fifo-size = <275>;
 155                 g-tx-fifo-size = <256 128 128 64 64 32>;
 156                 phys = <&usbphy0>;
 157                 phy-names = "usb2-phy";
 158                 status = "disabled";
 159         };
 160
 161         usb_host: usb@101c0000 {
 162                 compatible = "snps,dwc2";
 163                 reg = <0x101c0000 0x40000>;
 164                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 165                 clocks = <&cru HCLK_OTG1>;
 166                 clock-names = "otg";
 167                 dr_mode = "host";
 168                 phys = <&usbphy1>;
 169                 phy-names = "usb2-phy";
 170                 status = "disabled";
 171         };
 172
 173         emac: ethernet@10204000 {
 174                 compatible = "snps,arc-emac";
 175                 reg = <0x10204000 0x3c>;
 176                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 177                 #address-cells = <1>;
 178                 #size-cells = <0>;
 179
 180                 rockchip,grf = <&grf>;
 181
 182                 clocks = <&cru HCLK_EMAC>, <&cru SCLK_MAC>;
 183                 clock-names = "hclk", "macref";
 184                 max-speed = <100>;
 185                 phy-mode = "rmii";
 186
 187                 status = "disabled";
 188         };
 189
 190         mmc0: mmc@10214000 {
 191                 compatible = "rockchip,rk2928-dw-mshc";
 192                 reg = <0x10214000 0x1000>;
 193                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 194                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
 195                 clock-names = "biu", "ciu";
 196                 dmas = <&dmac2 1>;
 197                 dma-names = "rx-tx";
 198                 fifo-depth = <256>;
 199                 resets = <&cru SRST_SDMMC>;
 200                 reset-names = "reset";
 201                 status = "disabled";
 202         };
 203
 204         mmc1: mmc@10218000 {
 205                 compatible = "rockchip,rk2928-dw-mshc";
 206                 reg = <0x10218000 0x1000>;
 207                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 208                 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>;
 209                 clock-names = "biu", "ciu";
 210                 dmas = <&dmac2 3>;
 211                 dma-names = "rx-tx";
 212                 fifo-depth = <256>;
 213                 resets = <&cru SRST_SDIO>;
 214                 reset-names = "reset";
 215                 status = "disabled";
 216         };
 217
 218         emmc: mmc@1021c000 {
 219                 compatible = "rockchip,rk2928-dw-mshc";
 220                 reg = <0x1021c000 0x1000>;
 221                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 222                 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>;
 223                 clock-names = "biu", "ciu";
 224                 dmas = <&dmac2 4>;
 225                 dma-names = "rx-tx";
 226                 fifo-depth = <256>;
 227                 resets = <&cru SRST_EMMC>;
 228                 reset-names = "reset";
 229                 status = "disabled";
 230         };
 231
 232         nfc: nand-controller@10500000 {
 233                 compatible = "rockchip,rk2928-nfc";
 234                 reg = <0x10500000 0x4000>;
 235                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 236                 clocks = <&cru HCLK_NANDC0>;
 237                 clock-names = "ahb";
 238                 status = "disabled";
 239         };
 240
 241         pmu: pmu@20004000 {
 242                 compatible = "rockchip,rk3066-pmu", "syscon", "simple-mfd";
 243                 reg = <0x20004000 0x100>;
 244
 245                 reboot-mode {
 246                         compatible = "syscon-reboot-mode";
 247                         offset = <0x40>;
 248                         mode-normal = <BOOT_NORMAL>;
 249                         mode-recovery = <BOOT_RECOVERY>;
 250                         mode-bootloader = <BOOT_FASTBOOT>;
 251                         mode-loader = <BOOT_BL_DOWNLOAD>;
 252                 };
 253         };
 254
 255         grf: grf@20008000 {
 256                 compatible = "syscon", "simple-mfd";
 257                 reg = <0x20008000 0x200>;
 258         };
 259
 260         dmac1_s: dma-controller@20018000 {
 261                 compatible = "arm,pl330", "arm,primecell";
 262                 reg = <0x20018000 0x4000>;
 263                 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 264                              <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 265                 #dma-cells = <1>;
 266                 arm,pl330-broken-no-flushp;
 267                 arm,pl330-periph-burst;
 268                 clocks = <&cru ACLK_DMA1>;
 269                 clock-names = "apb_pclk";
 270         };
 271
 272         dmac1_ns: dma-controller@2001c000 {
 273                 compatible = "arm,pl330", "arm,primecell";
 274                 reg = <0x2001c000 0x4000>;
 275                 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 276                              <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 277                 #dma-cells = <1>;
 278                 arm,pl330-broken-no-flushp;
 279                 arm,pl330-periph-burst;
 280                 clocks = <&cru ACLK_DMA1>;
 281                 clock-names = "apb_pclk";
 282                 status = "disabled";
 283         };
 284
 285         i2c0: i2c@2002d000 {
 286                 compatible = "rockchip,rk3066-i2c";
 287                 reg = <0x2002d000 0x1000>;
 288                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 289                 #address-cells = <1>;
 290                 #size-cells = <0>;
 291
 292                 rockchip,grf = <&grf>;
 293
 294                 clock-names = "i2c";
 295                 clocks = <&cru PCLK_I2C0>;
 296
 297                 status = "disabled";
 298         };
 299
 300         i2c1: i2c@2002f000 {
 301                 compatible = "rockchip,rk3066-i2c";
 302                 reg = <0x2002f000 0x1000>;
 303                 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 304                 #address-cells = <1>;
 305                 #size-cells = <0>;
 306
 307                 rockchip,grf = <&grf>;
 308
 309                 clocks = <&cru PCLK_I2C1>;
 310                 clock-names = "i2c";
 311
 312                 status = "disabled";
 313         };
 314
 315         pwm0: pwm@20030000 {
 316                 compatible = "rockchip,rk2928-pwm";
 317                 reg = <0x20030000 0x10>;
 318                 #pwm-cells = <2>;
 319                 clocks = <&cru PCLK_PWM01>;
 320                 status = "disabled";
 321         };
 322
 323         pwm1: pwm@20030010 {
 324                 compatible = "rockchip,rk2928-pwm";
 325                 reg = <0x20030010 0x10>;
 326                 #pwm-cells = <2>;
 327                 clocks = <&cru PCLK_PWM01>;
 328                 status = "disabled";
 329         };
 330
 331         wdt: watchdog@2004c000 {
 332                 compatible = "snps,dw-wdt";
 333                 reg = <0x2004c000 0x100>;
 334                 clocks = <&cru PCLK_WDT>;
 335                 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
 336                 status = "disabled";
 337         };
 338
 339         pwm2: pwm@20050020 {
 340                 compatible = "rockchip,rk2928-pwm";
 341                 reg = <0x20050020 0x10>;
 342                 #pwm-cells = <2>;
 343                 clocks = <&cru PCLK_PWM23>;
 344                 status = "disabled";
 345         };
 346
 347         pwm3: pwm@20050030 {
 348                 compatible = "rockchip,rk2928-pwm";
 349                 reg = <0x20050030 0x10>;
 350                 #pwm-cells = <2>;
 351                 clocks = <&cru PCLK_PWM23>;
 352                 status = "disabled";
 353         };
 354
 355         i2c2: i2c@20056000 {
 356                 compatible = "rockchip,rk3066-i2c";
 357                 reg = <0x20056000 0x1000>;
 358                 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
 359                 #address-cells = <1>;
 360                 #size-cells = <0>;
 361
 362                 rockchip,grf = <&grf>;
 363
 364                 clocks = <&cru PCLK_I2C2>;
 365                 clock-names = "i2c";
 366
 367                 status = "disabled";
 368         };
 369
 370         i2c3: i2c@2005a000 {
 371                 compatible = "rockchip,rk3066-i2c";
 372                 reg = <0x2005a000 0x1000>;
 373                 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
 374                 #address-cells = <1>;
 375                 #size-cells = <0>;
 376
 377                 rockchip,grf = <&grf>;
 378
 379                 clocks = <&cru PCLK_I2C3>;
 380                 clock-names = "i2c";
 381
 382                 status = "disabled";
 383         };
 384
 385         i2c4: i2c@2005e000 {
 386                 compatible = "rockchip,rk3066-i2c";
 387                 reg = <0x2005e000 0x1000>;
 388                 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 389                 #address-cells = <1>;
 390                 #size-cells = <0>;
 391
 392                 rockchip,grf = <&grf>;
 393
 394                 clocks = <&cru PCLK_I2C4>;
 395                 clock-names = "i2c";
 396
 397                 status = "disabled";
 398         };
 399
 400         uart2: serial@20064000 {
 401                 compatible = "snps,dw-apb-uart";
 402                 reg = <0x20064000 0x400>;
 403                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 404                 reg-shift = <2>;
 405                 reg-io-width = <1>;
 406                 clock-names = "baudclk", "apb_pclk";
 407                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 408                 status = "disabled";
 409         };
 410
 411         uart3: serial@20068000 {
 412                 compatible = "snps,dw-apb-uart";
 413                 reg = <0x20068000 0x400>;
 414                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 415                 reg-shift = <2>;
 416                 reg-io-width = <1>;
 417                 clock-names = "baudclk", "apb_pclk";
 418                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 419                 status = "disabled";
 420         };
 421
 422         saradc: saradc@2006c000 {
 423                 compatible = "rockchip,saradc";
 424                 reg = <0x2006c000 0x100>;
 425                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 426                 #io-channel-cells = <1>;
 427                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 428                 clock-names = "saradc", "apb_pclk";
 429                 resets = <&cru SRST_SARADC>;
 430                 reset-names = "saradc-apb";
 431                 status = "disabled";
 432         };
 433
 434         spi0: spi@20070000 {
 435                 compatible = "rockchip,rk3066-spi";
 436                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
 437                 clock-names = "spiclk", "apb_pclk";
 438                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 439                 reg = <0x20070000 0x1000>;
 440                 #address-cells = <1>;
 441                 #size-cells = <0>;
 442                 dmas = <&dmac2 10>, <&dmac2 11>;
 443                 dma-names = "tx", "rx";
 444                 status = "disabled";
 445         };
 446
 447         spi1: spi@20074000 {
 448                 compatible = "rockchip,rk3066-spi";
 449                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
 450                 clock-names = "spiclk", "apb_pclk";
 451                 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 452                 reg = <0x20074000 0x1000>;
 453                 #address-cells = <1>;
 454                 #size-cells = <0>;
 455                 dmas = <&dmac2 12>, <&dmac2 13>;
 456                 dma-names = "tx", "rx";
 457                 status = "disabled";
 458         };
 459
 460         dmac2: dma-controller@20078000 {
 461                 compatible = "arm,pl330", "arm,primecell";
 462                 reg = <0x20078000 0x4000>;
 463                 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
 464                              <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 465                 #dma-cells = <1>;
 466                 arm,pl330-broken-no-flushp;
 467                 arm,pl330-periph-burst;
 468                 clocks = <&cru ACLK_DMA2>;
 469                 clock-names = "apb_pclk";
 470         };
 471 };