arch/arm/boot/dts/rk3288-veyron.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Google Veyron (and derivatives) board device tree source
   4  *
   5  * Copyright 2015 Google, Inc
   6  */
   7
   8 #include <dt-bindings/clock/rockchip,rk808.h>
   9 #include <dt-bindings/input/input.h>
  10 #include "rk3288.dtsi"
  11
  12 / {
  13         chosen {
  14                 stdout-path = "serial2:115200n8";
  15         };
  16
  17         /*
  18          * The default coreboot on veyron devices ignores memory@0 nodes
  19          * and would instead create another memory node.
  20          */
  21         memory {
  22                 device_type = "memory";
  23                 reg = <0x0 0x0 0x0 0x80000000>;
  24         };
  25
  26         gpio_keys: gpio-keys {
  27                 compatible = "gpio-keys";
  28                 #address-cells = <1>;
  29                 #size-cells = <0>;
  30
  31                 pinctrl-names = "default";
  32                 pinctrl-0 = <&pwr_key_l>;
  33                 power {
  34                         label = "Power";
  35                         gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>;
  36                         linux,code = <KEY_POWER>;
  37                         debounce-interval = <100>;
  38                         wakeup-source;
  39                 };
  40         };
  41
  42         gpio-restart {
  43                 compatible = "gpio-restart";
  44                 gpios = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>;
  45                 pinctrl-names = "default";
  46                 pinctrl-0 = <&ap_warm_reset_h>;
  47                 priority = <200>;
  48         };
  49
  50         emmc_pwrseq: emmc-pwrseq {
  51                 compatible = "mmc-pwrseq-emmc";
  52                 pinctrl-0 = <&emmc_reset>;
  53                 pinctrl-names = "default";
  54                 reset-gpios = <&gpio2 RK_PB1 GPIO_ACTIVE_HIGH>;
  55         };
  56
  57         sdio_pwrseq: sdio-pwrseq {
  58                 compatible = "mmc-pwrseq-simple";
  59                 clocks = <&rk808 RK808_CLKOUT1>;
  60                 clock-names = "ext_clock";
  61                 pinctrl-names = "default";
  62                 pinctrl-0 = <&bt_enable_l>, <&wifi_enable_h>;
  63
  64                 /*
  65                  * On the module itself this is one of these (depending
  66                  * on the actual card populated):
  67                  * - SDIO_RESET_L_WL_REG_ON
  68                  * - PDN (power down when low)
  69                  */
  70                 reset-gpios = <&gpio4 RK_PD4 GPIO_ACTIVE_LOW>;
  71         };
  72
  73         vcc_5v: vcc-5v {
  74                 compatible = "regulator-fixed";
  75                 regulator-name = "vcc_5v";
  76                 regulator-always-on;
  77                 regulator-boot-on;
  78                 regulator-min-microvolt = <5000000>;
  79                 regulator-max-microvolt = <5000000>;
  80         };
  81
  82         vcc33_sys: vcc33-sys {
  83                 compatible = "regulator-fixed";
  84                 regulator-name = "vcc33_sys";
  85                 regulator-always-on;
  86                 regulator-boot-on;
  87                 regulator-min-microvolt = <3300000>;
  88                 regulator-max-microvolt = <3300000>;
  89         };
  90
  91         vcc50_hdmi: vcc50-hdmi {
  92                 compatible = "regulator-fixed";
  93                 regulator-name = "vcc50_hdmi";
  94                 regulator-always-on;
  95                 regulator-boot-on;
  96                 vin-supply = <&vcc_5v>;
  97         };
  98
  99         vdd_logic: vdd-logic {
 100                 compatible = "pwm-regulator";
 101                 regulator-name = "vdd_logic";
 102
 103                 pwms = <&pwm1 0 1994 0>;
 104                 pwm-supply = <&vcc33_sys>;
 105
 106                 pwm-dutycycle-range = <0x7b 0>;
 107                 pwm-dutycycle-unit = <0x94>;
 108
 109                 regulator-always-on;
 110                 regulator-boot-on;
 111                 regulator-min-microvolt = <950000>;
 112                 regulator-max-microvolt = <1350000>;
 113                 regulator-ramp-delay = <4000>;
 114         };
 115 };
 116
 117 &cpu0 {
 118         cpu0-supply = <&vdd_cpu>;
 119 };
 120
 121 /* rk3288-c used in Veyron Chrome-devices has slightly changed OPPs */
 122 &cpu_opp_table {
 123         /delete-node/ opp-312000000;
 124
 125         opp-1512000000 {
 126                 opp-microvolt = <1250000>;
 127         };
 128         opp-1608000000 {
 129                 opp-microvolt = <1300000>;
 130         };
 131         opp-1704000000 {
 132                 opp-hz = /bits/ 64 <1704000000>;
 133                 opp-microvolt = <1350000>;
 134         };
 135         opp-1800000000 {
 136                 opp-hz = /bits/ 64 <1800000000>;
 137                 opp-microvolt = <1400000>;
 138         };
 139 };
 140
 141 &emmc {
 142         status = "okay";
 143
 144         bus-width = <8>;
 145         cap-mmc-highspeed;
 146         rockchip,default-sample-phase = <158>;
 147         disable-wp;
 148         mmc-hs200-1_8v;
 149         mmc-pwrseq = <&emmc_pwrseq>;
 150         non-removable;
 151         pinctrl-names = "default";
 152         pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
 153 };
 154
 155 &gpu {
 156         mali-supply = <&vdd_gpu>;
 157         status = "okay";
 158 };
 159
 160 &hdmi {
 161         ddc-i2c-bus = <&i2c5>;
 162         status = "okay";
 163 };
 164
 165 &i2c0 {
 166         status = "okay";
 167
 168         clock-frequency = <400000>;
 169         i2c-scl-falling-time-ns = <50>;         /* 2.5ns measured */
 170         i2c-scl-rising-time-ns = <100>;         /* 45ns measured */
 171
 172         rk808: pmic@1b {
 173                 compatible = "rockchip,rk808";
 174                 reg = <0x1b>;
 175                 clock-output-names = "xin32k", "wifibt_32kin";
 176                 interrupt-parent = <&gpio0>;
 177                 interrupts = <RK_PA4 IRQ_TYPE_LEVEL_LOW>;
 178                 pinctrl-names = "default";
 179                 pinctrl-0 = <&pmic_int_l>;
 180                 rockchip,system-power-controller;
 181                 wakeup-source;
 182                 #clock-cells = <1>;
 183
 184                 vcc1-supply = <&vcc33_sys>;
 185                 vcc2-supply = <&vcc33_sys>;
 186                 vcc3-supply = <&vcc33_sys>;
 187                 vcc4-supply = <&vcc33_sys>;
 188                 vcc6-supply = <&vcc_5v>;
 189                 vcc7-supply = <&vcc33_sys>;
 190                 vcc8-supply = <&vcc33_sys>;
 191                 vcc12-supply = <&vcc_18>;
 192                 vddio-supply = <&vcc33_io>;
 193
 194                 regulators {
 195                         vdd_cpu: DCDC_REG1 {
 196                                 regulator-name = "vdd_arm";
 197                                 regulator-always-on;
 198                                 regulator-boot-on;
 199                                 regulator-min-microvolt = <750000>;
 200                                 regulator-max-microvolt = <1450000>;
 201                                 regulator-ramp-delay = <6001>;
 202                                 regulator-state-mem {
 203                                         regulator-off-in-suspend;
 204                                 };
 205                         };
 206
 207                         vdd_gpu: DCDC_REG2 {
 208                                 regulator-name = "vdd_gpu";
 209                                 regulator-always-on;
 210                                 regulator-boot-on;
 211                                 regulator-min-microvolt = <800000>;
 212                                 regulator-max-microvolt = <1250000>;
 213                                 regulator-ramp-delay = <6001>;
 214                                 regulator-state-mem {
 215                                         regulator-on-in-suspend;
 216                                         regulator-suspend-microvolt = <1000000>;
 217                                 };
 218                         };
 219
 220                         vcc135_ddr: DCDC_REG3 {
 221                                 regulator-name = "vcc135_ddr";
 222                                 regulator-always-on;
 223                                 regulator-boot-on;
 224                                 regulator-state-mem {
 225                                         regulator-on-in-suspend;
 226                                 };
 227                         };
 228
 229                         /*
 230                          * vcc_18 has several aliases.  (vcc18_flashio and
 231                          * vcc18_wl).  We'll add those aliases here just to
 232                          * make it easier to follow the schematic.  The signals
 233                          * are actually hooked together and only separated for
 234                          * power measurement purposes).
 235                          */
 236                         vcc18_wl: vcc18_flashio: vcc_18: DCDC_REG4 {
 237                                 regulator-name = "vcc_18";
 238                                 regulator-always-on;
 239                                 regulator-boot-on;
 240                                 regulator-min-microvolt = <1800000>;
 241                                 regulator-max-microvolt = <1800000>;
 242                                 regulator-state-mem {
 243                                         regulator-on-in-suspend;
 244                                         regulator-suspend-microvolt = <1800000>;
 245                                 };
 246                         };
 247
 248                         /*
 249                          * Note that both vcc33_io and vcc33_pmuio are always
 250                          * powered together. To simplify the logic in the dts
 251                          * we just refer to vcc33_io every time something is
 252                          * powered from vcc33_pmuio. In fact, on later boards
 253                          * (such as danger) they're the same net.
 254                          */
 255                         vcc33_io: LDO_REG1 {
 256                                 regulator-name = "vcc33_io";
 257                                 regulator-always-on;
 258                                 regulator-boot-on;
 259                                 regulator-min-microvolt = <3300000>;
 260                                 regulator-max-microvolt = <3300000>;
 261                                 regulator-state-mem {
 262                                         regulator-on-in-suspend;
 263                                         regulator-suspend-microvolt = <3300000>;
 264                                 };
 265                         };
 266
 267                         vdd_10: LDO_REG3 {
 268                                 regulator-name = "vdd_10";
 269                                 regulator-always-on;
 270                                 regulator-boot-on;
 271                                 regulator-min-microvolt = <1000000>;
 272                                 regulator-max-microvolt = <1000000>;
 273                                 regulator-state-mem {
 274                                         regulator-on-in-suspend;
 275                                         regulator-suspend-microvolt = <1000000>;
 276                                 };
 277                         };
 278
 279                         vdd10_lcd_pwren_h: LDO_REG7 {
 280                                 regulator-name = "vdd10_lcd_pwren_h";
 281                                 regulator-always-on;
 282                                 regulator-boot-on;
 283                                 regulator-min-microvolt = <2500000>;
 284                                 regulator-max-microvolt = <2500000>;
 285                                 regulator-state-mem {
 286                                         regulator-off-in-suspend;
 287                                 };
 288                         };
 289
 290                         vcc33_lcd: SWITCH_REG1 {
 291                                 regulator-name = "vcc33_lcd";
 292                                 regulator-always-on;
 293                                 regulator-boot-on;
 294                                 regulator-state-mem {
 295                                         regulator-off-in-suspend;
 296                                 };
 297                         };
 298                 };
 299         };
 300 };
 301
 302 &i2c1 {
 303         status = "okay";
 304
 305         clock-frequency = <400000>;
 306         i2c-scl-falling-time-ns = <50>;         /* 2.5ns measured */
 307         i2c-scl-rising-time-ns = <100>;         /* 40ns measured */
 308
 309         tpm: tpm@20 {
 310                 compatible = "infineon,slb9645tt";
 311                 reg = <0x20>;
 312                 powered-while-suspended;
 313         };
 314 };
 315
 316 &i2c2 {
 317         status = "okay";
 318
 319         /* 100kHz since 4.7k resistors don't rise fast enough */
 320         clock-frequency = <100000>;
 321         i2c-scl-falling-time-ns = <50>;         /* 10ns measured */
 322         i2c-scl-rising-time-ns = <800>;         /* 600ns measured */
 323 };
 324
 325 &i2c4 {
 326         status = "okay";
 327
 328         clock-frequency = <400000>;
 329         i2c-scl-falling-time-ns = <50>;         /* 11ns measured */
 330         i2c-scl-rising-time-ns = <300>;         /* 225ns measured */
 331 };
 332
 333 &i2c5 {
 334         status = "okay";
 335
 336         clock-frequency = <100000>;
 337         i2c-scl-falling-time-ns = <300>;
 338         i2c-scl-rising-time-ns = <1000>;
 339 };
 340
 341 &io_domains {
 342         status = "okay";
 343
 344         bb-supply = <&vcc33_io>;
 345         dvp-supply = <&vcc_18>;
 346         flash0-supply = <&vcc18_flashio>;
 347         gpio1830-supply = <&vcc33_io>;
 348         gpio30-supply = <&vcc33_io>;
 349         lcdc-supply = <&vcc33_lcd>;
 350         wifi-supply = <&vcc18_wl>;
 351 };
 352
 353 &pwm1 {
 354         status = "okay";
 355 };
 356
 357 &sdio0 {
 358         status = "okay";
 359
 360         bus-width = <4>;
 361         cap-sd-highspeed;
 362         cap-sdio-irq;
 363         keep-power-in-suspend;
 364         mmc-pwrseq = <&sdio_pwrseq>;
 365         non-removable;
 366         pinctrl-names = "default";
 367         pinctrl-0 = <&sdio0_clk &sdio0_cmd &sdio0_bus4>;
 368         sd-uhs-sdr12;
 369         sd-uhs-sdr25;
 370         sd-uhs-sdr50;
 371         sd-uhs-sdr104;
 372         vmmc-supply = <&vcc33_sys>;
 373         vqmmc-supply = <&vcc18_wl>;
 374 };
 375
 376 &spi2 {
 377         status = "okay";
 378
 379         rx-sample-delay-ns = <12>;
 380
 381         flash@0 {
 382                 compatible = "jedec,spi-nor";
 383                 spi-max-frequency = <50000000>;
 384                 reg = <0>;
 385         };
 386 };
 387
 388 &tsadc {
 389         status = "okay";
 390
 391         rockchip,hw-tshut-mode = <1>; /* tshut mode 0:CRU 1:GPIO */
 392         rockchip,hw-tshut-polarity = <1>; /* tshut polarity 0:LOW 1:HIGH */
 393 };
 394
 395 &uart0 {
 396         status = "okay";
 397
 398         /* Pins don't include flow control by default; add that in */
 399         pinctrl-names = "default";
 400         pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 401 };
 402
 403 &uart1 {
 404         status = "okay";
 405 };
 406
 407 &uart2 {
 408         status = "okay";
 409 };
 410
 411 &usbphy {
 412         status = "okay";
 413 };
 414
 415 &usb_host0_ehci {
 416         status = "okay";
 417
 418         needs-reset-on-resume;
 419 };
 420
 421 &usb_host1 {
 422         status = "okay";
 423 };
 424
 425 &usb_otg {
 426         status = "okay";
 427
 428         assigned-clocks = <&cru SCLK_USBPHY480M_SRC>;
 429         assigned-clock-parents = <&usbphy0>;
 430         dr_mode = "host";
 431 };
 432
 433 &vopb {
 434         status = "okay";
 435 };
 436
 437 &vopb_mmu {
 438         status = "okay";
 439 };
 440
 441 &wdt {
 442         status = "okay";
 443 };
 444
 445 &pinctrl {
 446         pinctrl-names = "default", "sleep";
 447         pinctrl-0 = <
 448                 /* Common for sleep and wake, but no owners */
 449                 &global_pwroff
 450         >;
 451         pinctrl-1 = <
 452                 /* Common for sleep and wake, but no owners */
 453                 &global_pwroff
 454         >;
 455
 456         pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma {
 457                 bias-disable;
 458                 drive-strength = <8>;
 459         };
 460
 461         pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma {
 462                 bias-pull-up;
 463                 drive-strength = <8>;
 464         };
 465
 466         pcfg_output_high: pcfg-output-high {
 467                 output-high;
 468         };
 469
 470         pcfg_output_low: pcfg-output-low {
 471                 output-low;
 472         };
 473
 474         buttons {
 475                 pwr_key_l: pwr-key-l {
 476                         rockchip,pins = <0 5 RK_FUNC_GPIO &pcfg_pull_up>;
 477                 };
 478         };
 479
 480         emmc {
 481                 emmc_reset: emmc-reset {
 482                         rockchip,pins = <2 9 RK_FUNC_GPIO &pcfg_pull_none>;
 483                 };
 484
 485                 /*
 486                  * We run eMMC at max speed; bump up drive strength.
 487                  * We also have external pulls, so disable the internal ones.
 488                  */
 489                 emmc_clk: emmc-clk {
 490                         rockchip,pins = <3 18 RK_FUNC_2 &pcfg_pull_none_drv_8ma>;
 491                 };
 492
 493                 emmc_cmd: emmc-cmd {
 494                         rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_none_drv_8ma>;
 495                 };
 496
 497                 emmc_bus8: emmc-bus8 {
 498                         rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_none_drv_8ma>,
 499                                         <3 1 RK_FUNC_2 &pcfg_pull_none_drv_8ma>,
 500                                         <3 2 RK_FUNC_2 &pcfg_pull_none_drv_8ma>,
 501                                         <3 3 RK_FUNC_2 &pcfg_pull_none_drv_8ma>,
 502                                         <3 4 RK_FUNC_2 &pcfg_pull_none_drv_8ma>,
 503                                         <3 5 RK_FUNC_2 &pcfg_pull_none_drv_8ma>,
 504                                         <3 6 RK_FUNC_2 &pcfg_pull_none_drv_8ma>,
 505                                         <3 7 RK_FUNC_2 &pcfg_pull_none_drv_8ma>;
 506                 };
 507         };
 508
 509         pmic {
 510                 pmic_int_l: pmic-int-l {
 511                         rockchip,pins = <RK_GPIO0 4 RK_FUNC_GPIO &pcfg_pull_up>;
 512                 };
 513         };
 514
 515         reboot {
 516                 ap_warm_reset_h: ap-warm-reset-h {
 517                         rockchip,pins = <RK_GPIO0 13 RK_FUNC_GPIO &pcfg_pull_none>;
 518                 };
 519         };
 520
 521         recovery-switch {
 522                 rec_mode_l: rec-mode-l {
 523                         rockchip,pins = <0 9 RK_FUNC_GPIO &pcfg_pull_up>;
 524                 };
 525         };
 526
 527         sdio0 {
 528                 wifi_enable_h: wifienable-h {
 529                         rockchip,pins = <4 28 RK_FUNC_GPIO &pcfg_pull_none>;
 530                 };
 531
 532                 /* NOTE: mislabelled on schematic; should be bt_enable_h */
 533                 bt_enable_l: bt-enable-l {
 534                         rockchip,pins = <4 29 RK_FUNC_GPIO &pcfg_pull_none>;
 535                 };
 536
 537                 /*
 538                  * We run sdio0 at max speed; bump up drive strength.
 539                  * We also have external pulls, so disable the internal ones.
 540                  */
 541                 sdio0_bus4: sdio0-bus4 {
 542                         rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_none_drv_8ma>,
 543                                         <4 21 RK_FUNC_1 &pcfg_pull_none_drv_8ma>,
 544                                         <4 22 RK_FUNC_1 &pcfg_pull_none_drv_8ma>,
 545                                         <4 23 RK_FUNC_1 &pcfg_pull_none_drv_8ma>;
 546                 };
 547
 548                 sdio0_cmd: sdio0-cmd {
 549                         rockchip,pins = <4 24 RK_FUNC_1 &pcfg_pull_none_drv_8ma>;
 550                 };
 551
 552                 sdio0_clk: sdio0-clk {
 553                         rockchip,pins = <4 25 RK_FUNC_1 &pcfg_pull_none_drv_8ma>;
 554                 };
 555         };
 556
 557         tpm {
 558                 tpm_int_h: tpm-int-h {
 559                         rockchip,pins = <7 4 RK_FUNC_GPIO &pcfg_pull_none>;
 560                 };
 561         };
 562
 563         write-protect {
 564                 fw_wp_ap: fw-wp-ap {
 565                         rockchip,pins = <7 6 RK_FUNC_GPIO &pcfg_pull_none>;
 566                 };
 567         };
 568 };