arch/arm/boot/dts/rk3188.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Copyright (c) 2013 MundoReader S.L.
   4  * Author: Heiko Stuebner <heiko@sntech.de>
   5  */
   6
   7 #include <dt-bindings/gpio/gpio.h>
   8 #include <dt-bindings/pinctrl/rockchip.h>
   9 #include <dt-bindings/clock/rk3188-cru.h>
  10 #include <dt-bindings/power/rk3188-power.h>
  11 #include "rk3xxx.dtsi"
  12
  13 / {
  14         compatible = "rockchip,rk3188";
  15
  16         cpus {
  17                 #address-cells = <1>;
  18                 #size-cells = <0>;
  19                 enable-method = "rockchip,rk3066-smp";
  20
  21                 cpu0: cpu@0 {
  22                         device_type = "cpu";
  23                         compatible = "arm,cortex-a9";
  24                         next-level-cache = <&L2>;
  25                         reg = <0x0>;
  26                         clock-latency = <40000>;
  27                         clocks = <&cru ARMCLK>;
  28                         operating-points-v2 = <&cpu0_opp_table>;
  29                         resets = <&cru SRST_CORE0>;
  30                 };
  31                 cpu1: cpu@1 {
  32                         device_type = "cpu";
  33                         compatible = "arm,cortex-a9";
  34                         next-level-cache = <&L2>;
  35                         reg = <0x1>;
  36                         operating-points-v2 = <&cpu0_opp_table>;
  37                         resets = <&cru SRST_CORE1>;
  38                 };
  39                 cpu2: cpu@2 {
  40                         device_type = "cpu";
  41                         compatible = "arm,cortex-a9";
  42                         next-level-cache = <&L2>;
  43                         reg = <0x2>;
  44                         operating-points-v2 = <&cpu0_opp_table>;
  45                         resets = <&cru SRST_CORE2>;
  46                 };
  47                 cpu3: cpu@3 {
  48                         device_type = "cpu";
  49                         compatible = "arm,cortex-a9";
  50                         next-level-cache = <&L2>;
  51                         reg = <0x3>;
  52                         operating-points-v2 = <&cpu0_opp_table>;
  53                         resets = <&cru SRST_CORE3>;
  54                 };
  55         };
  56
  57         cpu0_opp_table: opp_table0 {
  58                 compatible = "operating-points-v2";
  59                 opp-shared;
  60
  61                 opp-312000000 {
  62                         opp-hz = /bits/ 64 <312000000>;
  63                         opp-microvolt = <875000>;
  64                         clock-latency-ns = <40000>;
  65                 };
  66                 opp-504000000 {
  67                         opp-hz = /bits/ 64 <504000000>;
  68                         opp-microvolt = <925000>;
  69                 };
  70                 opp-600000000 {
  71                         opp-hz = /bits/ 64 <600000000>;
  72                         opp-microvolt = <950000>;
  73                         opp-suspend;
  74                 };
  75                 opp-816000000 {
  76                         opp-hz = /bits/ 64 <816000000>;
  77                         opp-microvolt = <975000>;
  78                 };
  79                 opp-1008000000 {
  80                         opp-hz = /bits/ 64 <1008000000>;
  81                         opp-microvolt = <1075000>;
  82                 };
  83                 opp-1200000000 {
  84                         opp-hz = /bits/ 64 <1200000000>;
  85                         opp-microvolt = <1150000>;
  86                 };
  87                 opp-1416000000 {
  88                         opp-hz = /bits/ 64 <1416000000>;
  89                         opp-microvolt = <1250000>;
  90                 };
  91                 opp-1608000000 {
  92                         opp-hz = /bits/ 64 <1608000000>;
  93                         opp-microvolt = <1350000>;
  94                 };
  95         };
  96
  97         display-subsystem {
  98                 compatible = "rockchip,display-subsystem";
  99                 ports = <&vop0_out>, <&vop1_out>;
 100         };
 101
 102         sram: sram@10080000 {
 103                 compatible = "mmio-sram";
 104                 reg = <0x10080000 0x8000>;
 105                 #address-cells = <1>;
 106                 #size-cells = <1>;
 107                 ranges = <0 0x10080000 0x8000>;
 108
 109                 smp-sram@0 {
 110                         compatible = "rockchip,rk3066-smp-sram";
 111                         reg = <0x0 0x50>;
 112                 };
 113         };
 114
 115         vop0: vop@1010c000 {
 116                 compatible = "rockchip,rk3188-vop";
 117                 reg = <0x1010c000 0x1000>;
 118                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 119                 clocks = <&cru ACLK_LCDC0>, <&cru DCLK_LCDC0>, <&cru HCLK_LCDC0>;
 120                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
 121                 power-domains = <&power RK3188_PD_VIO>;
 122                 resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>;
 123                 reset-names = "axi", "ahb", "dclk";
 124                 status = "disabled";
 125
 126                 vop0_out: port {
 127                         #address-cells = <1>;
 128                         #size-cells = <0>;
 129                 };
 130         };
 131
 132         vop1: vop@1010e000 {
 133                 compatible = "rockchip,rk3188-vop";
 134                 reg = <0x1010e000 0x1000>;
 135                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 136                 clocks = <&cru ACLK_LCDC1>, <&cru DCLK_LCDC1>, <&cru HCLK_LCDC1>;
 137                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
 138                 power-domains = <&power RK3188_PD_VIO>;
 139                 resets = <&cru SRST_LCDC1_AXI>, <&cru SRST_LCDC1_AHB>, <&cru SRST_LCDC1_DCLK>;
 140                 reset-names = "axi", "ahb", "dclk";
 141                 status = "disabled";
 142
 143                 vop1_out: port {
 144                         #address-cells = <1>;
 145                         #size-cells = <0>;
 146                 };
 147         };
 148
 149         timer3: timer@2000e000 {
 150                 compatible = "rockchip,rk3188-timer", "rockchip,rk3288-timer";
 151                 reg = <0x2000e000 0x20>;
 152                 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 153                 clocks = <&cru SCLK_TIMER3>, <&cru PCLK_TIMER3>;
 154                 clock-names = "timer", "pclk";
 155         };
 156
 157         timer6: timer@200380a0 {
 158                 compatible = "rockchip,rk3188-timer", "rockchip,rk3288-timer";
 159                 reg = <0x200380a0 0x20>;
 160                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 161                 clocks = <&cru SCLK_TIMER6>, <&cru PCLK_TIMER0>;
 162                 clock-names = "timer", "pclk";
 163         };
 164
 165         i2s0: i2s@1011a000 {
 166                 compatible = "rockchip,rk3188-i2s", "rockchip,rk3066-i2s";
 167                 reg = <0x1011a000 0x2000>;
 168                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 169                 pinctrl-names = "default";
 170                 pinctrl-0 = <&i2s0_bus>;
 171                 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0>;
 172                 clock-names = "i2s_clk", "i2s_hclk";
 173                 dmas = <&dmac1_s 6>, <&dmac1_s 7>;
 174                 dma-names = "tx", "rx";
 175                 rockchip,playback-channels = <2>;
 176                 rockchip,capture-channels = <2>;
 177                 #sound-dai-cells = <0>;
 178                 status = "disabled";
 179         };
 180
 181         spdif: sound@1011e000 {
 182                 compatible = "rockchip,rk3188-spdif", "rockchip,rk3066-spdif";
 183                 reg = <0x1011e000 0x2000>;
 184                 #sound-dai-cells = <0>;
 185                 clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF>;
 186                 clock-names = "mclk", "hclk";
 187                 dmas = <&dmac1_s 8>;
 188                 dma-names = "tx";
 189                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 190                 pinctrl-names = "default";
 191                 pinctrl-0 = <&spdif_tx>;
 192                 status = "disabled";
 193         };
 194
 195         cru: clock-controller@20000000 {
 196                 compatible = "rockchip,rk3188-cru";
 197                 reg = <0x20000000 0x1000>;
 198                 rockchip,grf = <&grf>;
 199
 200                 #clock-cells = <1>;
 201                 #reset-cells = <1>;
 202         };
 203
 204         efuse: efuse@20010000 {
 205                 compatible = "rockchip,rk3188-efuse";
 206                 reg = <0x20010000 0x4000>;
 207                 #address-cells = <1>;
 208                 #size-cells = <1>;
 209                 clocks = <&cru PCLK_EFUSE>;
 210                 clock-names = "pclk_efuse";
 211
 212                 cpu_leakage: cpu_leakage@17 {
 213                         reg = <0x17 0x1>;
 214                 };
 215         };
 216
 217         usbphy: phy {
 218                 compatible = "rockchip,rk3188-usb-phy", "rockchip,rk3288-usb-phy";
 219                 rockchip,grf = <&grf>;
 220                 #address-cells = <1>;
 221                 #size-cells = <0>;
 222                 status = "disabled";
 223
 224                 usbphy0: usb-phy@10c {
 225                         #phy-cells = <0>;
 226                         reg = <0x10c>;
 227                         clocks = <&cru SCLK_OTGPHY0>;
 228                         clock-names = "phyclk";
 229                         #clock-cells = <0>;
 230                 };
 231
 232                 usbphy1: usb-phy@11c {
 233                         #phy-cells = <0>;
 234                         reg = <0x11c>;
 235                         clocks = <&cru SCLK_OTGPHY1>;
 236                         clock-names = "phyclk";
 237                         #clock-cells = <0>;
 238                 };
 239         };
 240
 241         pinctrl: pinctrl {
 242                 compatible = "rockchip,rk3188-pinctrl";
 243                 rockchip,grf = <&grf>;
 244                 rockchip,pmu = <&pmu>;
 245
 246                 #address-cells = <1>;
 247                 #size-cells = <1>;
 248                 ranges;
 249
 250                 gpio0: gpio0@2000a000 {
 251                         compatible = "rockchip,rk3188-gpio-bank0";
 252                         reg = <0x2000a000 0x100>;
 253                         interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
 254                         clocks = <&cru PCLK_GPIO0>;
 255
 256                         gpio-controller;
 257                         #gpio-cells = <2>;
 258
 259                         interrupt-controller;
 260                         #interrupt-cells = <2>;
 261                 };
 262
 263                 gpio1: gpio1@2003c000 {
 264                         compatible = "rockchip,gpio-bank";
 265                         reg = <0x2003c000 0x100>;
 266                         interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 267                         clocks = <&cru PCLK_GPIO1>;
 268
 269                         gpio-controller;
 270                         #gpio-cells = <2>;
 271
 272                         interrupt-controller;
 273                         #interrupt-cells = <2>;
 274                 };
 275
 276                 gpio2: gpio2@2003e000 {
 277                         compatible = "rockchip,gpio-bank";
 278                         reg = <0x2003e000 0x100>;
 279                         interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 280                         clocks = <&cru PCLK_GPIO2>;
 281
 282                         gpio-controller;
 283                         #gpio-cells = <2>;
 284
 285                         interrupt-controller;
 286                         #interrupt-cells = <2>;
 287                 };
 288
 289                 gpio3: gpio3@20080000 {
 290                         compatible = "rockchip,gpio-bank";
 291                         reg = <0x20080000 0x100>;
 292                         interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 293                         clocks = <&cru PCLK_GPIO3>;
 294
 295                         gpio-controller;
 296                         #gpio-cells = <2>;
 297
 298                         interrupt-controller;
 299                         #interrupt-cells = <2>;
 300                 };
 301
 302                 pcfg_pull_up: pcfg_pull_up {
 303                         bias-pull-up;
 304                 };
 305
 306                 pcfg_pull_down: pcfg_pull_down {
 307                         bias-pull-down;
 308                 };
 309
 310                 pcfg_pull_none: pcfg_pull_none {
 311                         bias-disable;
 312                 };
 313
 314                 emmc {
 315                         emmc_clk: emmc-clk {
 316                                 rockchip,pins = <0 RK_PD0 2 &pcfg_pull_none>;
 317                         };
 318
 319                         emmc_cmd: emmc-cmd {
 320                                 rockchip,pins = <0 RK_PD2 2 &pcfg_pull_up>;
 321                         };
 322
 323                         emmc_rst: emmc-rst {
 324                                 rockchip,pins = <0 RK_PD3 2 &pcfg_pull_none>;
 325                         };
 326
 327                         /*
 328                          * The data pins are shared between nandc and emmc and
 329                          * not accessible through pinctrl. Also they should've
 330                          * been already set correctly by firmware, as
 331                          * flash/emmc is the boot-device.
 332                          */
 333                 };
 334
 335                 emac {
 336                         emac_xfer: emac-xfer {
 337                                 rockchip,pins = <3 RK_PC0 2 &pcfg_pull_none>, /* tx_en */
 338                                                 <3 RK_PC1 2 &pcfg_pull_none>, /* txd1 */
 339                                                 <3 RK_PC2 2 &pcfg_pull_none>, /* txd0 */
 340                                                 <3 RK_PC3 2 &pcfg_pull_none>, /* rxd0 */
 341                                                 <3 RK_PC4 2 &pcfg_pull_none>, /* rxd1 */
 342                                                 <3 RK_PC5 2 &pcfg_pull_none>, /* mac_clk */
 343                                                 <3 RK_PC6 2 &pcfg_pull_none>, /* rx_err */
 344                                                 <3 RK_PC7 2 &pcfg_pull_none>; /* crs_dvalid */
 345                         };
 346
 347                         emac_mdio: emac-mdio {
 348                                 rockchip,pins = <3 RK_PD0 2 &pcfg_pull_none>,
 349                                                 <3 RK_PD1 2 &pcfg_pull_none>;
 350                         };
 351                 };
 352
 353                 i2c0 {
 354                         i2c0_xfer: i2c0-xfer {
 355                                 rockchip,pins = <1 RK_PD0 1 &pcfg_pull_none>,
 356                                                 <1 RK_PD1 1 &pcfg_pull_none>;
 357                         };
 358                 };
 359
 360                 i2c1 {
 361                         i2c1_xfer: i2c1-xfer {
 362                                 rockchip,pins = <1 RK_PD2 1 &pcfg_pull_none>,
 363                                                 <1 RK_PD3 1 &pcfg_pull_none>;
 364                         };
 365                 };
 366
 367                 i2c2 {
 368                         i2c2_xfer: i2c2-xfer {
 369                                 rockchip,pins = <1 RK_PD4 1 &pcfg_pull_none>,
 370                                                 <1 RK_PD5 1 &pcfg_pull_none>;
 371                         };
 372                 };
 373
 374                 i2c3 {
 375                         i2c3_xfer: i2c3-xfer {
 376                                 rockchip,pins = <3 RK_PB6 2 &pcfg_pull_none>,
 377                                                 <3 RK_PB7 2 &pcfg_pull_none>;
 378                         };
 379                 };
 380
 381                 i2c4 {
 382                         i2c4_xfer: i2c4-xfer {
 383                                 rockchip,pins = <1 RK_PD6 1 &pcfg_pull_none>,
 384                                                 <1 RK_PD7 1 &pcfg_pull_none>;
 385                         };
 386                 };
 387
 388                 lcdc1 {
 389                         lcdc1_dclk: lcdc1-dclk {
 390                                 rockchip,pins = <2 RK_PD0 1 &pcfg_pull_none>;
 391                         };
 392
 393                         lcdc1_den: lcdc1-den {
 394                                 rockchip,pins = <2 RK_PD1 1 &pcfg_pull_none>;
 395                         };
 396
 397                         lcdc1_hsync: lcdc1-hsync {
 398                                 rockchip,pins = <2 RK_PD2 1 &pcfg_pull_none>;
 399                         };
 400
 401                         lcdc1_vsync: lcdc1-vsync {
 402                                 rockchip,pins = <2 RK_PD3 1 &pcfg_pull_none>;
 403                         };
 404
 405                         lcdc1_rgb24: ldcd1-rgb24 {
 406                                 rockchip,pins = <2 RK_PA0 1 &pcfg_pull_none>,
 407                                                 <2 RK_PA1 1 &pcfg_pull_none>,
 408                                                 <2 RK_PA2 1 &pcfg_pull_none>,
 409                                                 <2 RK_PA3 1 &pcfg_pull_none>,
 410                                                 <2 RK_PA4 1 &pcfg_pull_none>,
 411                                                 <2 RK_PA5 1 &pcfg_pull_none>,
 412                                                 <2 RK_PA6 1 &pcfg_pull_none>,
 413                                                 <2 RK_PA7 1 &pcfg_pull_none>,
 414                                                 <2 RK_PB0 1 &pcfg_pull_none>,
 415                                                 <2 RK_PB1 1 &pcfg_pull_none>,
 416                                                 <2 RK_PB2 1 &pcfg_pull_none>,
 417                                                 <2 RK_PB3 1 &pcfg_pull_none>,
 418                                                 <2 RK_PB4 1 &pcfg_pull_none>,
 419                                                 <2 RK_PB5 1 &pcfg_pull_none>,
 420                                                 <2 RK_PB6 1 &pcfg_pull_none>,
 421                                                 <2 RK_PB7 1 &pcfg_pull_none>,
 422                                                 <2 RK_PC0 1 &pcfg_pull_none>,
 423                                                 <2 RK_PC1 1 &pcfg_pull_none>,
 424                                                 <2 RK_PC2 1 &pcfg_pull_none>,
 425                                                 <2 RK_PC3 1 &pcfg_pull_none>,
 426                                                 <2 RK_PC4 1 &pcfg_pull_none>,
 427                                                 <2 RK_PC5 1 &pcfg_pull_none>,
 428                                                 <2 RK_PC6 1 &pcfg_pull_none>,
 429                                                 <2 RK_PC7 1 &pcfg_pull_none>;
 430                         };
 431                 };
 432
 433                 pwm0 {
 434                         pwm0_out: pwm0-out {
 435                                 rockchip,pins = <3 RK_PD3 1 &pcfg_pull_none>;
 436                         };
 437                 };
 438
 439                 pwm1 {
 440                         pwm1_out: pwm1-out {
 441                                 rockchip,pins = <3 RK_PD4 1 &pcfg_pull_none>;
 442                         };
 443                 };
 444
 445                 pwm2 {
 446                         pwm2_out: pwm2-out {
 447                                 rockchip,pins = <3 RK_PD5 1 &pcfg_pull_none>;
 448                         };
 449                 };
 450
 451                 pwm3 {
 452                         pwm3_out: pwm3-out {
 453                                 rockchip,pins = <3 RK_PD6 1 &pcfg_pull_none>;
 454                         };
 455                 };
 456
 457                 spi0 {
 458                         spi0_clk: spi0-clk {
 459                                 rockchip,pins = <1 RK_PA6 2 &pcfg_pull_up>;
 460                         };
 461                         spi0_cs0: spi0-cs0 {
 462                                 rockchip,pins = <1 RK_PA7 2 &pcfg_pull_up>;
 463                         };
 464                         spi0_tx: spi0-tx {
 465                                 rockchip,pins = <1 RK_PA5 2 &pcfg_pull_up>;
 466                         };
 467                         spi0_rx: spi0-rx {
 468                                 rockchip,pins = <1 RK_PA4 2 &pcfg_pull_up>;
 469                         };
 470                         spi0_cs1: spi0-cs1 {
 471                                 rockchip,pins = <1 RK_PB7 1 &pcfg_pull_up>;
 472                         };
 473                 };
 474
 475                 spi1 {
 476                         spi1_clk: spi1-clk {
 477                                 rockchip,pins = <0 RK_PD6 1 &pcfg_pull_up>;
 478                         };
 479                         spi1_cs0: spi1-cs0 {
 480                                 rockchip,pins = <0 RK_PD7 1 &pcfg_pull_up>;
 481                         };
 482                         spi1_rx: spi1-rx {
 483                                 rockchip,pins = <0 RK_PD4 1 &pcfg_pull_up>;
 484                         };
 485                         spi1_tx: spi1-tx {
 486                                 rockchip,pins = <0 RK_PD5 1 &pcfg_pull_up>;
 487                         };
 488                         spi1_cs1: spi1-cs1 {
 489                                 rockchip,pins = <1 RK_PB6 2 &pcfg_pull_up>;
 490                         };
 491                 };
 492
 493                 uart0 {
 494                         uart0_xfer: uart0-xfer {
 495                                 rockchip,pins = <1 RK_PA0 1 &pcfg_pull_up>,
 496                                                 <1 RK_PA1 1 &pcfg_pull_none>;
 497                         };
 498
 499                         uart0_cts: uart0-cts {
 500                                 rockchip,pins = <1 RK_PA2 1 &pcfg_pull_none>;
 501                         };
 502
 503                         uart0_rts: uart0-rts {
 504                                 rockchip,pins = <1 RK_PA3 1 &pcfg_pull_none>;
 505                         };
 506                 };
 507
 508                 uart1 {
 509                         uart1_xfer: uart1-xfer {
 510                                 rockchip,pins = <1 RK_PA4 1 &pcfg_pull_up>,
 511                                                 <1 RK_PA5 1 &pcfg_pull_none>;
 512                         };
 513
 514                         uart1_cts: uart1-cts {
 515                                 rockchip,pins = <1 RK_PA6 1 &pcfg_pull_none>;
 516                         };
 517
 518                         uart1_rts: uart1-rts {
 519                                 rockchip,pins = <1 RK_PA7 1 &pcfg_pull_none>;
 520                         };
 521                 };
 522
 523                 uart2 {
 524                         uart2_xfer: uart2-xfer {
 525                                 rockchip,pins = <1 RK_PB0 1 &pcfg_pull_up>,
 526                                                 <1 RK_PB1 1 &pcfg_pull_none>;
 527                         };
 528                         /* no rts / cts for uart2 */
 529                 };
 530
 531                 uart3 {
 532                         uart3_xfer: uart3-xfer {
 533                                 rockchip,pins = <1 RK_PB2 1 &pcfg_pull_up>,
 534                                                 <1 RK_PB3 1 &pcfg_pull_none>;
 535                         };
 536
 537                         uart3_cts: uart3-cts {
 538                                 rockchip,pins = <1 RK_PB4 1 &pcfg_pull_none>;
 539                         };
 540
 541                         uart3_rts: uart3-rts {
 542                                 rockchip,pins = <1 RK_PB5 1 &pcfg_pull_none>;
 543                         };
 544                 };
 545
 546                 sd0 {
 547                         sd0_clk: sd0-clk {
 548                                 rockchip,pins = <3 RK_PA2 1 &pcfg_pull_none>;
 549                         };
 550
 551                         sd0_cmd: sd0-cmd {
 552                                 rockchip,pins = <3 RK_PA3 1 &pcfg_pull_none>;
 553                         };
 554
 555                         sd0_cd: sd0-cd {
 556                                 rockchip,pins = <3 RK_PB0 1 &pcfg_pull_none>;
 557                         };
 558
 559                         sd0_wp: sd0-wp {
 560                                 rockchip,pins = <3 RK_PB1 1 &pcfg_pull_none>;
 561                         };
 562
 563                         sd0_pwr: sd0-pwr {
 564                                 rockchip,pins = <3 RK_PA1 1 &pcfg_pull_none>;
 565                         };
 566
 567                         sd0_bus1: sd0-bus-width1 {
 568                                 rockchip,pins = <3 RK_PA4 1 &pcfg_pull_none>;
 569                         };
 570
 571                         sd0_bus4: sd0-bus-width4 {
 572                                 rockchip,pins = <3 RK_PA4 1 &pcfg_pull_none>,
 573                                                 <3 RK_PA5 1 &pcfg_pull_none>,
 574                                                 <3 RK_PA6 1 &pcfg_pull_none>,
 575                                                 <3 RK_PA7 1 &pcfg_pull_none>;
 576                         };
 577                 };
 578
 579                 sd1 {
 580                         sd1_clk: sd1-clk {
 581                                 rockchip,pins = <3 RK_PC5 1 &pcfg_pull_none>;
 582                         };
 583
 584                         sd1_cmd: sd1-cmd {
 585                                 rockchip,pins = <3 RK_PC0 1 &pcfg_pull_none>;
 586                         };
 587
 588                         sd1_cd: sd1-cd {
 589                                 rockchip,pins = <3 RK_PC6 1 &pcfg_pull_none>;
 590                         };
 591
 592                         sd1_wp: sd1-wp {
 593                                 rockchip,pins = <3 RK_PC7 1 &pcfg_pull_none>;
 594                         };
 595
 596                         sd1_bus1: sd1-bus-width1 {
 597                                 rockchip,pins = <3 RK_PC1 1 &pcfg_pull_none>;
 598                         };
 599
 600                         sd1_bus4: sd1-bus-width4 {
 601                                 rockchip,pins = <3 RK_PC1 1 &pcfg_pull_none>,
 602                                                 <3 RK_PC2 1 &pcfg_pull_none>,
 603                                                 <3 RK_PC3 1 &pcfg_pull_none>,
 604                                                 <3 RK_PC4 1 &pcfg_pull_none>;
 605                         };
 606                 };
 607
 608                 i2s0 {
 609                         i2s0_bus: i2s0-bus {
 610                                 rockchip,pins = <1 RK_PC0 1 &pcfg_pull_none>,
 611                                                 <1 RK_PC1 1 &pcfg_pull_none>,
 612                                                 <1 RK_PC2 1 &pcfg_pull_none>,
 613                                                 <1 RK_PC3 1 &pcfg_pull_none>,
 614                                                 <1 RK_PC4 1 &pcfg_pull_none>,
 615                                                 <1 RK_PC5 1 &pcfg_pull_none>;
 616                         };
 617                 };
 618
 619                 spdif {
 620                         spdif_tx: spdif-tx {
 621                                 rockchip,pins = <1 RK_PB6 1 &pcfg_pull_none>;
 622                         };
 623                 };
 624         };
 625 };
 626
 627 &emac {
 628         compatible = "rockchip,rk3188-emac";
 629 };
 630
 631 &global_timer {
 632         interrupts = <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
 633         status = "disabled";
 634 };
 635
 636 &local_timer {
 637         interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
 638 };
 639
 640 &gpu {
 641         compatible = "rockchip,rk3188-mali", "arm,mali-400";
 642         interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
 643                      <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
 644                      <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
 645                      <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
 646                      <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
 647                      <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
 648                      <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
 649                      <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
 650                      <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
 651                      <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 652         interrupt-names = "gp",
 653                           "gpmmu",
 654                           "pp0",
 655                           "ppmmu0",
 656                           "pp1",
 657                           "ppmmu1",
 658                           "pp2",
 659                           "ppmmu2",
 660                           "pp3",
 661                           "ppmmu3";
 662         power-domains = <&power RK3188_PD_GPU>;
 663 };
 664
 665 &i2c0 {
 666         compatible = "rockchip,rk3188-i2c";
 667         pinctrl-names = "default";
 668         pinctrl-0 = <&i2c0_xfer>;
 669 };
 670
 671 &i2c1 {
 672         compatible = "rockchip,rk3188-i2c";
 673         pinctrl-names = "default";
 674         pinctrl-0 = <&i2c1_xfer>;
 675 };
 676
 677 &i2c2 {
 678         compatible = "rockchip,rk3188-i2c";
 679         pinctrl-names = "default";
 680         pinctrl-0 = <&i2c2_xfer>;
 681 };
 682
 683 &i2c3 {
 684         compatible = "rockchip,rk3188-i2c";
 685         pinctrl-names = "default";
 686         pinctrl-0 = <&i2c3_xfer>;
 687 };
 688
 689 &i2c4 {
 690         compatible = "rockchip,rk3188-i2c";
 691         pinctrl-names = "default";
 692         pinctrl-0 = <&i2c4_xfer>;
 693 };
 694
 695 &pmu {
 696         power: power-controller {
 697                 compatible = "rockchip,rk3188-power-controller";
 698                 #power-domain-cells = <1>;
 699                 #address-cells = <1>;
 700                 #size-cells = <0>;
 701
 702                 pd_vio@RK3188_PD_VIO {
 703                         reg = <RK3188_PD_VIO>;
 704                         clocks = <&cru ACLK_LCDC0>,
 705                                  <&cru ACLK_LCDC1>,
 706                                  <&cru DCLK_LCDC0>,
 707                                  <&cru DCLK_LCDC1>,
 708                                  <&cru HCLK_LCDC0>,
 709                                  <&cru HCLK_LCDC1>,
 710                                  <&cru SCLK_CIF0>,
 711                                  <&cru ACLK_CIF0>,
 712                                  <&cru HCLK_CIF0>,
 713                                  <&cru ACLK_IPP>,
 714                                  <&cru HCLK_IPP>,
 715                                  <&cru ACLK_RGA>,
 716                                  <&cru HCLK_RGA>;
 717                         pm_qos = <&qos_lcdc0>,
 718                                  <&qos_lcdc1>,
 719                                  <&qos_cif0>,
 720                                  <&qos_ipp>,
 721                                  <&qos_rga>;
 722                 };
 723
 724                 pd_video@RK3188_PD_VIDEO {
 725                         reg = <RK3188_PD_VIDEO>;
 726                         clocks = <&cru ACLK_VDPU>,
 727                                  <&cru ACLK_VEPU>,
 728                                  <&cru HCLK_VDPU>,
 729                                  <&cru HCLK_VEPU>;
 730                         pm_qos = <&qos_vpu>;
 731                 };
 732
 733                 pd_gpu@RK3188_PD_GPU {
 734                         reg = <RK3188_PD_GPU>;
 735                         clocks = <&cru ACLK_GPU>;
 736                         pm_qos = <&qos_gpu>;
 737                 };
 738         };
 739 };
 740
 741 &pwm0 {
 742         pinctrl-names = "default";
 743         pinctrl-0 = <&pwm0_out>;
 744 };
 745
 746 &pwm1 {
 747         pinctrl-names = "default";
 748         pinctrl-0 = <&pwm1_out>;
 749 };
 750
 751 &pwm2 {
 752         pinctrl-names = "default";
 753         pinctrl-0 = <&pwm2_out>;
 754 };
 755
 756 &pwm3 {
 757         pinctrl-names = "default";
 758         pinctrl-0 = <&pwm3_out>;
 759 };
 760
 761 &spi0 {
 762         compatible = "rockchip,rk3188-spi", "rockchip,rk3066-spi";
 763         pinctrl-names = "default";
 764         pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
 765 };
 766
 767 &spi1 {
 768         compatible = "rockchip,rk3188-spi", "rockchip,rk3066-spi";
 769         pinctrl-names = "default";
 770         pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
 771 };
 772
 773 &uart0 {
 774         compatible = "rockchip,rk3188-uart", "snps,dw-apb-uart";
 775         pinctrl-names = "default";
 776         pinctrl-0 = <&uart0_xfer>;
 777 };
 778
 779 &uart1 {
 780         compatible = "rockchip,rk3188-uart", "snps,dw-apb-uart";
 781         pinctrl-names = "default";
 782         pinctrl-0 = <&uart1_xfer>;
 783 };
 784
 785 &uart2 {
 786         compatible = "rockchip,rk3188-uart", "snps,dw-apb-uart";
 787         pinctrl-names = "default";
 788         pinctrl-0 = <&uart2_xfer>;
 789 };
 790
 791 &uart3 {
 792         compatible = "rockchip,rk3188-uart", "snps,dw-apb-uart";
 793         pinctrl-names = "default";
 794         pinctrl-0 = <&uart3_xfer>;
 795 };
 796
 797 &wdt {
 798         compatible = "rockchip,rk3188-wdt", "snps,dw-wdt";
 799 };