1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 #include <dt-bindings/gpio/gpio.h>
4 #include <dt-bindings/interrupt-controller/irq.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/pinctrl/rockchip.h>
7 #include <dt-bindings/clock/rk3036-cru.h>
8 #include <dt-bindings/soc/rockchip,boot-mode.h>
9 #include <dt-bindings/power/rk3036-power.h>
15 compatible = "rockchip,rk3036";
17 interrupt-parent = <&gic>;
35 enable-method = "rockchip,rk3036-smp";
39 compatible = "arm,cortex-a7";
41 resets = <&cru SRST_CORE0>;
46 clock-latency = <40000>;
47 clocks = <&cru ARMCLK>;
52 compatible = "arm,cortex-a7";
54 resets = <&cru SRST_CORE1>;
59 compatible = "arm,cortex-a7-pmu";
60 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
61 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
62 interrupt-affinity = <&cpu0>, <&cpu1>;
66 compatible = "rockchip,display-subsystem";
71 compatible = "arm,armv7-timer";
72 arm,cpu-registers-not-fw-configured;
73 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
74 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
75 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
76 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
77 clock-frequency = <24000000>;
81 compatible = "fixed-clock";
82 clock-frequency = <24000000>;
83 clock-output-names = "xin24m";
87 bus_intmem: sram@10080000 {
88 compatible = "mmio-sram";
89 reg = <0x10080000 0x2000>;
92 ranges = <0 0x10080000 0x2000>;
95 compatible = "rockchip,rk3066-smp-sram";
101 compatible = "rockchip,rk3036-mali", "arm,mali-400";
102 reg = <0x10090000 0x10000>;
103 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
104 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
105 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
106 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
107 interrupt-names = "gp",
111 assigned-clocks = <&cru SCLK_GPU>;
112 assigned-clock-rates = <100000000>;
113 clocks = <&cru SCLK_GPU>, <&cru SCLK_GPU>;
114 clock-names = "bus", "core";
115 power-domains = <&power RK3036_PD_GPU>;
116 resets = <&cru SRST_GPU>;
121 compatible = "rockchip,rk3036-vop";
122 reg = <0x10118000 0x19c>;
123 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
124 clocks = <&cru ACLK_LCDC>, <&cru SCLK_LCDC>, <&cru HCLK_LCDC>;
125 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
126 resets = <&cru SRST_LCDC1_A>, <&cru SRST_LCDC1_H>, <&cru SRST_LCDC1_D>;
127 reset-names = "axi", "ahb", "dclk";
129 power-domains = <&power RK3036_PD_VIO>;
133 #address-cells = <1>;
135 vop_out_hdmi: endpoint@0 {
137 remote-endpoint = <&hdmi_in_vop>;
142 vop_mmu: iommu@10118300 {
143 compatible = "rockchip,iommu";
144 reg = <0x10118300 0x100>;
145 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
146 clocks = <&cru ACLK_LCDC>, <&cru HCLK_LCDC>;
147 clock-names = "aclk", "iface";
148 power-domains = <&power RK3036_PD_VIO>;
153 qos_gpu: qos@1012d000 {
154 compatible = "rockchip,rk3036-qos", "syscon";
155 reg = <0x1012d000 0x20>;
158 qos_vpu: qos@1012e000 {
159 compatible = "rockchip,rk3036-qos", "syscon";
160 reg = <0x1012e000 0x20>;
163 qos_vio: qos@1012f000 {
164 compatible = "rockchip,rk3036-qos", "syscon";
165 reg = <0x1012f000 0x20>;
168 gic: interrupt-controller@10139000 {
169 compatible = "arm,gic-400";
170 interrupt-controller;
171 #interrupt-cells = <3>;
172 #address-cells = <0>;
174 reg = <0x10139000 0x1000>,
178 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
181 usb_otg: usb@10180000 {
182 compatible = "rockchip,rk3036-usb", "rockchip,rk3066-usb",
184 reg = <0x10180000 0x40000>;
185 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
186 clocks = <&cru HCLK_OTG0>;
189 g-np-tx-fifo-size = <16>;
190 g-rx-fifo-size = <275>;
191 g-tx-fifo-size = <256 128 128 64 64 32>;
195 usb_host: usb@101c0000 {
196 compatible = "rockchip,rk3036-usb", "rockchip,rk3066-usb",
198 reg = <0x101c0000 0x40000>;
199 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
200 clocks = <&cru HCLK_OTG1>;
206 emac: ethernet@10200000 {
207 compatible = "rockchip,rk3036-emac", "snps,arc-emac";
208 reg = <0x10200000 0x4000>;
209 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
210 #address-cells = <1>;
212 rockchip,grf = <&grf>;
213 clocks = <&cru HCLK_MAC>, <&cru SCLK_MACREF>, <&cru SCLK_MAC>;
214 clock-names = "hclk", "macref", "macclk";
216 * Fix the emac parent clock is DPLL instead of APLL.
217 * since that will cause some unstable things if the cpufreq
218 * is working. (e.g: the accurate 50MHz what mac_ref need)
220 assigned-clocks = <&cru SCLK_MACPLL>;
221 assigned-clock-parents = <&cru PLL_DPLL>;
227 sdmmc: mmc@10214000 {
228 compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc";
229 reg = <0x10214000 0x4000>;
230 clock-frequency = <37500000>;
231 max-frequency = <37500000>;
232 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
233 clock-names = "biu", "ciu";
234 fifo-depth = <0x100>;
235 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
236 resets = <&cru SRST_MMC0>;
237 reset-names = "reset";
242 compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc";
243 reg = <0x10218000 0x4000>;
244 max-frequency = <37500000>;
245 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
246 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
247 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
248 fifo-depth = <0x100>;
249 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
250 resets = <&cru SRST_SDIO>;
251 reset-names = "reset";
256 compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc";
257 reg = <0x1021c000 0x4000>;
258 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
261 clock-frequency = <37500000>;
262 max-frequency = <37500000>;
263 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
264 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
265 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
266 rockchip,default-sample-phase = <158>;
270 fifo-depth = <0x100>;
273 pinctrl-names = "default";
274 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
275 resets = <&cru SRST_EMMC>;
276 reset-names = "reset";
281 compatible = "rockchip,rk3036-i2s", "rockchip,rk3066-i2s";
282 reg = <0x10220000 0x4000>;
283 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
284 clock-names = "i2s_clk", "i2s_hclk";
285 clocks = <&cru SCLK_I2S>, <&cru HCLK_I2S>;
286 dmas = <&pdma 0>, <&pdma 1>;
287 dma-names = "tx", "rx";
288 pinctrl-names = "default";
289 pinctrl-0 = <&i2s_bus>;
290 #sound-dai-cells = <0>;
294 nfc: nand-controller@10500000 {
295 compatible = "rockchip,rk3036-nfc",
296 "rockchip,rk2928-nfc";
297 reg = <0x10500000 0x4000>;
298 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
299 clocks = <&cru HCLK_NANDC>, <&cru SCLK_NANDC>;
300 clock-names = "ahb", "nfc";
301 assigned-clocks = <&cru SCLK_NANDC>;
302 assigned-clock-rates = <150000000>;
303 pinctrl-0 = <&flash_ale &flash_bus8 &flash_cle &flash_csn0
304 &flash_rdn &flash_rdy &flash_wrn>;
305 pinctrl-names = "default";
309 cru: clock-controller@20000000 {
310 compatible = "rockchip,rk3036-cru";
311 reg = <0x20000000 0x1000>;
312 rockchip,grf = <&grf>;
315 assigned-clocks = <&cru PLL_GPLL>;
316 assigned-clock-rates = <594000000>;
319 grf: syscon@20008000 {
320 compatible = "rockchip,rk3036-grf", "syscon", "simple-mfd";
321 reg = <0x20008000 0x1000>;
323 power: power-controller {
324 compatible = "rockchip,rk3036-power-controller";
325 #power-domain-cells = <1>;
326 #address-cells = <1>;
329 power-domain@RK3036_PD_VIO {
330 reg = <RK3036_PD_VIO>;
331 clocks = <&cru ACLK_LCDC>,
335 #power-domain-cells = <0>;
338 power-domain@RK3036_PD_VPU {
339 reg = <RK3036_PD_VPU>;
340 clocks = <&cru ACLK_VCODEC>,
343 #power-domain-cells = <0>;
346 power-domain@RK3036_PD_GPU {
347 reg = <RK3036_PD_GPU>;
348 clocks = <&cru SCLK_GPU>;
350 #power-domain-cells = <0>;
355 compatible = "syscon-reboot-mode";
357 mode-normal = <BOOT_NORMAL>;
358 mode-recovery = <BOOT_RECOVERY>;
359 mode-bootloader = <BOOT_FASTBOOT>;
360 mode-loader = <BOOT_BL_DOWNLOAD>;
364 acodec: acodec-ana@20030000 {
365 compatible = "rk3036-codec";
366 reg = <0x20030000 0x4000>;
367 rockchip,grf = <&grf>;
368 clock-names = "acodec_pclk";
369 clocks = <&cru PCLK_ACODEC>;
373 hdmi: hdmi@20034000 {
374 compatible = "rockchip,rk3036-inno-hdmi";
375 reg = <0x20034000 0x4000>;
376 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
377 clocks = <&cru PCLK_HDMI>;
378 clock-names = "pclk";
379 rockchip,grf = <&grf>;
380 pinctrl-names = "default";
381 pinctrl-0 = <&hdmi_ctl>;
385 #address-cells = <1>;
387 hdmi_in_vop: endpoint@0 {
389 remote-endpoint = <&vop_out_hdmi>;
394 timer: timer@20044000 {
395 compatible = "rockchip,rk3036-timer", "rockchip,rk3288-timer";
396 reg = <0x20044000 0x20>;
397 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
398 clocks = <&xin24m>, <&cru PCLK_TIMER>;
399 clock-names = "timer", "pclk";
403 compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm";
404 reg = <0x20050000 0x10>;
406 clocks = <&cru PCLK_PWM>;
407 pinctrl-names = "default";
408 pinctrl-0 = <&pwm0_pin>;
413 compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm";
414 reg = <0x20050010 0x10>;
416 clocks = <&cru PCLK_PWM>;
417 pinctrl-names = "default";
418 pinctrl-0 = <&pwm1_pin>;
423 compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm";
424 reg = <0x20050020 0x10>;
426 clocks = <&cru PCLK_PWM>;
427 pinctrl-names = "default";
428 pinctrl-0 = <&pwm2_pin>;
433 compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm";
434 reg = <0x20050030 0x10>;
436 clocks = <&cru PCLK_PWM>;
437 pinctrl-names = "default";
438 pinctrl-0 = <&pwm3_pin>;
443 compatible = "rockchip,rk3036-i2c", "rockchip,rk3288-i2c";
444 reg = <0x20056000 0x1000>;
445 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
446 #address-cells = <1>;
449 clocks = <&cru PCLK_I2C1>;
450 pinctrl-names = "default";
451 pinctrl-0 = <&i2c1_xfer>;
456 compatible = "rockchip,rk3036-i2c", "rockchip,rk3288-i2c";
457 reg = <0x2005a000 0x1000>;
458 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
459 #address-cells = <1>;
462 clocks = <&cru PCLK_I2C2>;
463 pinctrl-names = "default";
464 pinctrl-0 = <&i2c2_xfer>;
468 uart0: serial@20060000 {
469 compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart";
470 reg = <0x20060000 0x100>;
471 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
474 clock-frequency = <24000000>;
475 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
476 clock-names = "baudclk", "apb_pclk";
477 pinctrl-names = "default";
478 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
482 uart1: serial@20064000 {
483 compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart";
484 reg = <0x20064000 0x100>;
485 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
488 clock-frequency = <24000000>;
489 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
490 clock-names = "baudclk", "apb_pclk";
491 pinctrl-names = "default";
492 pinctrl-0 = <&uart1_xfer>;
496 uart2: serial@20068000 {
497 compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart";
498 reg = <0x20068000 0x100>;
499 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
502 clock-frequency = <24000000>;
503 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
504 clock-names = "baudclk", "apb_pclk";
505 pinctrl-names = "default";
506 pinctrl-0 = <&uart2_xfer>;
511 compatible = "rockchip,rk3036-i2c", "rockchip,rk3288-i2c";
512 reg = <0x20072000 0x1000>;
513 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
514 #address-cells = <1>;
517 clocks = <&cru PCLK_I2C0>;
518 pinctrl-names = "default";
519 pinctrl-0 = <&i2c0_xfer>;
524 compatible = "rockchip,rockchip-spi";
525 reg = <0x20074000 0x1000>;
526 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
527 clocks = <&cru PCLK_SPI>, <&cru SCLK_SPI>;
528 clock-names = "apb-pclk","spi_pclk";
529 dmas = <&pdma 8>, <&pdma 9>;
530 dma-names = "tx", "rx";
531 pinctrl-names = "default";
532 pinctrl-0 = <&spi_txd &spi_rxd &spi_clk &spi_cs0>;
533 #address-cells = <1>;
538 pdma: pdma@20078000 {
539 compatible = "arm,pl330", "arm,primecell";
540 reg = <0x20078000 0x4000>;
541 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
542 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
544 arm,pl330-broken-no-flushp;
545 arm,pl330-periph-burst;
546 clocks = <&cru ACLK_DMAC2>;
547 clock-names = "apb_pclk";
551 compatible = "rockchip,rk3036-pinctrl";
552 rockchip,grf = <&grf>;
553 #address-cells = <1>;
557 gpio0: gpio0@2007c000 {
558 compatible = "rockchip,gpio-bank";
559 reg = <0x2007c000 0x100>;
560 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
561 clocks = <&cru PCLK_GPIO0>;
566 interrupt-controller;
567 #interrupt-cells = <2>;
570 gpio1: gpio1@20080000 {
571 compatible = "rockchip,gpio-bank";
572 reg = <0x20080000 0x100>;
573 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
574 clocks = <&cru PCLK_GPIO1>;
579 interrupt-controller;
580 #interrupt-cells = <2>;
583 gpio2: gpio2@20084000 {
584 compatible = "rockchip,gpio-bank";
585 reg = <0x20084000 0x100>;
586 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
587 clocks = <&cru PCLK_GPIO2>;
592 interrupt-controller;
593 #interrupt-cells = <2>;
596 pcfg_pull_default: pcfg_pull_default {
597 bias-pull-pin-default;
600 pcfg_pull_none: pcfg-pull-none {
606 rockchip,pins = <0 RK_PA0 2 &pcfg_pull_none>;
612 rockchip,pins = <0 RK_PA1 2 &pcfg_pull_none>;
618 rockchip,pins = <0 RK_PA1 2 &pcfg_pull_none>;
624 rockchip,pins = <0 RK_PD3 1 &pcfg_pull_none>;
629 sdmmc_clk: sdmmc-clk {
630 rockchip,pins = <1 RK_PC0 1 &pcfg_pull_none>;
633 sdmmc_cmd: sdmmc-cmd {
634 rockchip,pins = <1 RK_PB7 1 &pcfg_pull_default>;
638 rockchip,pins = <1 RK_PC1 1 &pcfg_pull_default>;
641 sdmmc_bus1: sdmmc-bus1 {
642 rockchip,pins = <1 RK_PC2 1 &pcfg_pull_default>;
645 sdmmc_bus4: sdmmc-bus4 {
646 rockchip,pins = <1 RK_PC2 1 &pcfg_pull_default>,
647 <1 RK_PC3 1 &pcfg_pull_default>,
648 <1 RK_PC4 1 &pcfg_pull_default>,
649 <1 RK_PC5 1 &pcfg_pull_default>;
654 sdio_bus1: sdio-bus1 {
655 rockchip,pins = <0 RK_PB3 1 &pcfg_pull_default>;
658 sdio_bus4: sdio-bus4 {
659 rockchip,pins = <0 RK_PB3 1 &pcfg_pull_default>,
660 <0 RK_PB4 1 &pcfg_pull_default>,
661 <0 RK_PB5 1 &pcfg_pull_default>,
662 <0 RK_PB6 1 &pcfg_pull_default>;
666 rockchip,pins = <0 RK_PB0 1 &pcfg_pull_default>;
670 rockchip,pins = <0 RK_PB1 1 &pcfg_pull_none>;
676 * We run eMMC at max speed; bump up drive strength.
677 * We also have external pulls, so disable the internal ones.
680 rockchip,pins = <2 RK_PA4 2 &pcfg_pull_none>;
684 rockchip,pins = <2 RK_PA1 2 &pcfg_pull_default>;
687 emmc_bus8: emmc-bus8 {
688 rockchip,pins = <1 RK_PD0 2 &pcfg_pull_default>,
689 <1 RK_PD1 2 &pcfg_pull_default>,
690 <1 RK_PD2 2 &pcfg_pull_default>,
691 <1 RK_PD3 2 &pcfg_pull_default>,
692 <1 RK_PD4 2 &pcfg_pull_default>,
693 <1 RK_PD5 2 &pcfg_pull_default>,
694 <1 RK_PD6 2 &pcfg_pull_default>,
695 <1 RK_PD7 2 &pcfg_pull_default>;
700 flash_ale: flash-ale {
701 rockchip,pins = <2 RK_PA0 1 &pcfg_pull_default>;
704 flash_bus8: flash-bus8 {
705 rockchip,pins = <1 RK_PD0 1 &pcfg_pull_default>,
706 <1 RK_PD1 1 &pcfg_pull_default>,
707 <1 RK_PD2 1 &pcfg_pull_default>,
708 <1 RK_PD3 1 &pcfg_pull_default>,
709 <1 RK_PD4 1 &pcfg_pull_default>,
710 <1 RK_PD5 1 &pcfg_pull_default>,
711 <1 RK_PD6 1 &pcfg_pull_default>,
712 <1 RK_PD7 1 &pcfg_pull_default>;
715 flash_cle: flash-cle {
716 rockchip,pins = <2 RK_PA1 1 &pcfg_pull_default>;
719 flash_csn0: flash-csn0 {
720 rockchip,pins = <2 RK_PA6 1 &pcfg_pull_default>;
723 flash_rdn: flash-rdn {
724 rockchip,pins = <2 RK_PA3 1 &pcfg_pull_default>;
727 flash_rdy: flash-rdy {
728 rockchip,pins = <2 RK_PA4 1 &pcfg_pull_default>;
731 flash_wrn: flash-wrn {
732 rockchip,pins = <2 RK_PA2 1 &pcfg_pull_default>;
737 emac_xfer: emac-xfer {
738 rockchip,pins = <2 RK_PB2 1 &pcfg_pull_default>, /* crs_dvalid */
739 <2 RK_PB5 1 &pcfg_pull_default>, /* tx_en */
740 <2 RK_PB6 1 &pcfg_pull_default>, /* mac_clk */
741 <2 RK_PB7 1 &pcfg_pull_default>, /* rx_err */
742 <2 RK_PC0 1 &pcfg_pull_default>, /* rxd1 */
743 <2 RK_PC1 1 &pcfg_pull_default>, /* rxd0 */
744 <2 RK_PC2 1 &pcfg_pull_default>, /* txd1 */
745 <2 RK_PC3 1 &pcfg_pull_default>; /* txd0 */
748 emac_mdio: emac-mdio {
749 rockchip,pins = <2 RK_PB4 1 &pcfg_pull_default>, /* mac_md */
750 <2 RK_PD1 1 &pcfg_pull_default>; /* mac_mdclk */
755 i2c0_xfer: i2c0-xfer {
756 rockchip,pins = <0 RK_PA0 1 &pcfg_pull_none>,
757 <0 RK_PA1 1 &pcfg_pull_none>;
762 i2c1_xfer: i2c1-xfer {
763 rockchip,pins = <0 RK_PA2 1 &pcfg_pull_none>,
764 <0 RK_PA3 1 &pcfg_pull_none>;
769 i2c2_xfer: i2c2-xfer {
770 rockchip,pins = <2 RK_PC4 1 &pcfg_pull_none>,
771 <2 RK_PC5 1 &pcfg_pull_none>;
777 rockchip,pins = <1 RK_PA0 1 &pcfg_pull_default>,
778 <1 RK_PA1 1 &pcfg_pull_default>,
779 <1 RK_PA2 1 &pcfg_pull_default>,
780 <1 RK_PA3 1 &pcfg_pull_default>,
781 <1 RK_PA4 1 &pcfg_pull_default>,
782 <1 RK_PA5 1 &pcfg_pull_default>;
788 rockchip,pins = <1 RK_PB0 1 &pcfg_pull_none>,
789 <1 RK_PB1 1 &pcfg_pull_none>,
790 <1 RK_PB2 1 &pcfg_pull_none>,
791 <1 RK_PB3 1 &pcfg_pull_none>;
796 uart0_xfer: uart0-xfer {
797 rockchip,pins = <0 RK_PC0 1 &pcfg_pull_default>,
798 <0 RK_PC1 1 &pcfg_pull_none>;
801 uart0_cts: uart0-cts {
802 rockchip,pins = <0 RK_PC2 1 &pcfg_pull_default>;
805 uart0_rts: uart0-rts {
806 rockchip,pins = <0 RK_PC3 1 &pcfg_pull_none>;
811 uart1_xfer: uart1-xfer {
812 rockchip,pins = <2 RK_PC6 1 &pcfg_pull_default>,
813 <2 RK_PC7 1 &pcfg_pull_none>;
815 /* no rts / cts for uart1 */
819 uart2_xfer: uart2-xfer {
820 rockchip,pins = <1 RK_PC2 2 &pcfg_pull_default>,
821 <1 RK_PC3 2 &pcfg_pull_none>;
823 /* no rts / cts for uart2 */
828 rockchip,pins = <1 RK_PD5 3 &pcfg_pull_default>;
832 rockchip,pins = <1 RK_PD4 3 &pcfg_pull_default>;
836 rockchip,pins = <2 RK_PA0 2 &pcfg_pull_default>;
840 rockchip,pins = <1 RK_PD6 3 &pcfg_pull_default>;
845 rockchip,pins = <1 RK_PD7 3 &pcfg_pull_default>;