1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 #include <dt-bindings/gpio/gpio.h>
4 #include <dt-bindings/interrupt-controller/irq.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/pinctrl/rockchip.h>
7 #include <dt-bindings/clock/rk3036-cru.h>
8 #include <dt-bindings/soc/rockchip,boot-mode.h>
14 compatible = "rockchip,rk3036";
16 interrupt-parent = <&gic>;
34 enable-method = "rockchip,rk3036-smp";
38 compatible = "arm,cortex-a7";
40 resets = <&cru SRST_CORE0>;
45 clock-latency = <40000>;
46 clocks = <&cru ARMCLK>;
51 compatible = "arm,cortex-a7";
53 resets = <&cru SRST_CORE1>;
58 compatible = "arm,cortex-a7-pmu";
59 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
60 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
61 interrupt-affinity = <&cpu0>, <&cpu1>;
65 compatible = "rockchip,display-subsystem";
70 compatible = "arm,armv7-timer";
71 arm,cpu-registers-not-fw-configured;
72 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
73 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
74 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
75 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
76 clock-frequency = <24000000>;
80 compatible = "fixed-clock";
81 clock-frequency = <24000000>;
82 clock-output-names = "xin24m";
86 bus_intmem: sram@10080000 {
87 compatible = "mmio-sram";
88 reg = <0x10080000 0x2000>;
91 ranges = <0 0x10080000 0x2000>;
94 compatible = "rockchip,rk3066-smp-sram";
100 compatible = "rockchip,rk3036-mali", "arm,mali-400";
101 reg = <0x10090000 0x10000>;
102 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
103 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
104 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
105 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
106 interrupt-names = "gp",
110 assigned-clocks = <&cru SCLK_GPU>;
111 assigned-clock-rates = <100000000>;
112 clocks = <&cru SCLK_GPU>, <&cru SCLK_GPU>;
113 clock-names = "bus", "core";
114 resets = <&cru SRST_GPU>;
119 compatible = "rockchip,rk3036-vop";
120 reg = <0x10118000 0x19c>;
121 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
122 clocks = <&cru ACLK_LCDC>, <&cru SCLK_LCDC>, <&cru HCLK_LCDC>;
123 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
124 resets = <&cru SRST_LCDC1_A>, <&cru SRST_LCDC1_H>, <&cru SRST_LCDC1_D>;
125 reset-names = "axi", "ahb", "dclk";
130 #address-cells = <1>;
132 vop_out_hdmi: endpoint@0 {
134 remote-endpoint = <&hdmi_in_vop>;
139 vop_mmu: iommu@10118300 {
140 compatible = "rockchip,iommu";
141 reg = <0x10118300 0x100>;
142 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
143 interrupt-names = "vop_mmu";
144 clocks = <&cru ACLK_LCDC>, <&cru HCLK_LCDC>;
145 clock-names = "aclk", "iface";
150 gic: interrupt-controller@10139000 {
151 compatible = "arm,gic-400";
152 interrupt-controller;
153 #interrupt-cells = <3>;
154 #address-cells = <0>;
156 reg = <0x10139000 0x1000>,
160 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
163 usb_otg: usb@10180000 {
164 compatible = "rockchip,rk3036-usb", "rockchip,rk3066-usb",
166 reg = <0x10180000 0x40000>;
167 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
168 clocks = <&cru HCLK_OTG0>;
171 g-np-tx-fifo-size = <16>;
172 g-rx-fifo-size = <275>;
173 g-tx-fifo-size = <256 128 128 64 64 32>;
177 usb_host: usb@101c0000 {
178 compatible = "rockchip,rk3036-usb", "rockchip,rk3066-usb",
180 reg = <0x101c0000 0x40000>;
181 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
182 clocks = <&cru HCLK_OTG1>;
188 emac: ethernet@10200000 {
189 compatible = "rockchip,rk3036-emac", "snps,arc-emac";
190 reg = <0x10200000 0x4000>;
191 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
192 #address-cells = <1>;
194 rockchip,grf = <&grf>;
195 clocks = <&cru HCLK_MAC>, <&cru SCLK_MACREF>, <&cru SCLK_MAC>;
196 clock-names = "hclk", "macref", "macclk";
198 * Fix the emac parent clock is DPLL instead of APLL.
199 * since that will cause some unstable things if the cpufreq
200 * is working. (e.g: the accurate 50MHz what mac_ref need)
202 assigned-clocks = <&cru SCLK_MACPLL>;
203 assigned-clock-parents = <&cru PLL_DPLL>;
209 sdmmc: mmc@10214000 {
210 compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc";
211 reg = <0x10214000 0x4000>;
212 clock-frequency = <37500000>;
213 max-frequency = <37500000>;
214 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
215 clock-names = "biu", "ciu";
216 fifo-depth = <0x100>;
217 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
218 resets = <&cru SRST_MMC0>;
219 reset-names = "reset";
224 compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc";
225 reg = <0x10218000 0x4000>;
226 max-frequency = <37500000>;
227 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
228 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
229 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
230 fifo-depth = <0x100>;
231 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
232 resets = <&cru SRST_SDIO>;
233 reset-names = "reset";
238 compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc";
239 reg = <0x1021c000 0x4000>;
240 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
243 clock-frequency = <37500000>;
244 max-frequency = <37500000>;
245 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
246 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
247 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
248 rockchip,default-sample-phase = <158>;
252 fifo-depth = <0x100>;
255 pinctrl-names = "default";
256 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
257 resets = <&cru SRST_EMMC>;
258 reset-names = "reset";
263 compatible = "rockchip,rk3036-i2s", "rockchip,rk3066-i2s";
264 reg = <0x10220000 0x4000>;
265 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
266 clock-names = "i2s_clk", "i2s_hclk";
267 clocks = <&cru SCLK_I2S>, <&cru HCLK_I2S>;
268 dmas = <&pdma 0>, <&pdma 1>;
269 dma-names = "tx", "rx";
270 pinctrl-names = "default";
271 pinctrl-0 = <&i2s_bus>;
272 #sound-dai-cells = <0>;
276 nfc: nand-controller@10500000 {
277 compatible = "rockchip,rk3036-nfc",
278 "rockchip,rk2928-nfc";
279 reg = <0x10500000 0x4000>;
280 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
281 clocks = <&cru HCLK_NANDC>, <&cru SCLK_NANDC>;
282 clock-names = "ahb", "nfc";
283 assigned-clocks = <&cru SCLK_NANDC>;
284 assigned-clock-rates = <150000000>;
285 pinctrl-0 = <&flash_ale &flash_bus8 &flash_cle &flash_csn0
286 &flash_rdn &flash_rdy &flash_wrn>;
287 pinctrl-names = "default";
291 cru: clock-controller@20000000 {
292 compatible = "rockchip,rk3036-cru";
293 reg = <0x20000000 0x1000>;
294 rockchip,grf = <&grf>;
297 assigned-clocks = <&cru PLL_GPLL>;
298 assigned-clock-rates = <594000000>;
301 grf: syscon@20008000 {
302 compatible = "rockchip,rk3036-grf", "syscon", "simple-mfd";
303 reg = <0x20008000 0x1000>;
306 compatible = "syscon-reboot-mode";
308 mode-normal = <BOOT_NORMAL>;
309 mode-recovery = <BOOT_RECOVERY>;
310 mode-bootloader = <BOOT_FASTBOOT>;
311 mode-loader = <BOOT_BL_DOWNLOAD>;
315 acodec: acodec-ana@20030000 {
316 compatible = "rk3036-codec";
317 reg = <0x20030000 0x4000>;
318 rockchip,grf = <&grf>;
319 clock-names = "acodec_pclk";
320 clocks = <&cru PCLK_ACODEC>;
324 hdmi: hdmi@20034000 {
325 compatible = "rockchip,rk3036-inno-hdmi";
326 reg = <0x20034000 0x4000>;
327 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
328 clocks = <&cru PCLK_HDMI>;
329 clock-names = "pclk";
330 rockchip,grf = <&grf>;
331 pinctrl-names = "default";
332 pinctrl-0 = <&hdmi_ctl>;
336 #address-cells = <1>;
338 hdmi_in_vop: endpoint@0 {
340 remote-endpoint = <&vop_out_hdmi>;
345 timer: timer@20044000 {
346 compatible = "rockchip,rk3036-timer", "rockchip,rk3288-timer";
347 reg = <0x20044000 0x20>;
348 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
349 clocks = <&xin24m>, <&cru PCLK_TIMER>;
350 clock-names = "timer", "pclk";
354 compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm";
355 reg = <0x20050000 0x10>;
357 clocks = <&cru PCLK_PWM>;
358 pinctrl-names = "default";
359 pinctrl-0 = <&pwm0_pin>;
364 compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm";
365 reg = <0x20050010 0x10>;
367 clocks = <&cru PCLK_PWM>;
368 pinctrl-names = "default";
369 pinctrl-0 = <&pwm1_pin>;
374 compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm";
375 reg = <0x20050020 0x10>;
377 clocks = <&cru PCLK_PWM>;
378 pinctrl-names = "default";
379 pinctrl-0 = <&pwm2_pin>;
384 compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm";
385 reg = <0x20050030 0x10>;
387 clocks = <&cru PCLK_PWM>;
388 pinctrl-names = "default";
389 pinctrl-0 = <&pwm3_pin>;
394 compatible = "rockchip,rk3036-i2c", "rockchip,rk3288-i2c";
395 reg = <0x20056000 0x1000>;
396 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
397 #address-cells = <1>;
400 clocks = <&cru PCLK_I2C1>;
401 pinctrl-names = "default";
402 pinctrl-0 = <&i2c1_xfer>;
407 compatible = "rockchip,rk3036-i2c", "rockchip,rk3288-i2c";
408 reg = <0x2005a000 0x1000>;
409 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
410 #address-cells = <1>;
413 clocks = <&cru PCLK_I2C2>;
414 pinctrl-names = "default";
415 pinctrl-0 = <&i2c2_xfer>;
419 uart0: serial@20060000 {
420 compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart";
421 reg = <0x20060000 0x100>;
422 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
425 clock-frequency = <24000000>;
426 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
427 clock-names = "baudclk", "apb_pclk";
428 pinctrl-names = "default";
429 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
433 uart1: serial@20064000 {
434 compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart";
435 reg = <0x20064000 0x100>;
436 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
439 clock-frequency = <24000000>;
440 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
441 clock-names = "baudclk", "apb_pclk";
442 pinctrl-names = "default";
443 pinctrl-0 = <&uart1_xfer>;
447 uart2: serial@20068000 {
448 compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart";
449 reg = <0x20068000 0x100>;
450 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
453 clock-frequency = <24000000>;
454 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
455 clock-names = "baudclk", "apb_pclk";
456 pinctrl-names = "default";
457 pinctrl-0 = <&uart2_xfer>;
462 compatible = "rockchip,rk3036-i2c", "rockchip,rk3288-i2c";
463 reg = <0x20072000 0x1000>;
464 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
465 #address-cells = <1>;
468 clocks = <&cru PCLK_I2C0>;
469 pinctrl-names = "default";
470 pinctrl-0 = <&i2c0_xfer>;
475 compatible = "rockchip,rockchip-spi";
476 reg = <0x20074000 0x1000>;
477 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
478 clocks = <&cru PCLK_SPI>, <&cru SCLK_SPI>;
479 clock-names = "apb-pclk","spi_pclk";
480 dmas = <&pdma 8>, <&pdma 9>;
481 dma-names = "tx", "rx";
482 pinctrl-names = "default";
483 pinctrl-0 = <&spi_txd &spi_rxd &spi_clk &spi_cs0>;
484 #address-cells = <1>;
489 pdma: pdma@20078000 {
490 compatible = "arm,pl330", "arm,primecell";
491 reg = <0x20078000 0x4000>;
492 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
493 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
495 arm,pl330-broken-no-flushp;
496 arm,pl330-periph-burst;
497 clocks = <&cru ACLK_DMAC2>;
498 clock-names = "apb_pclk";
502 compatible = "rockchip,rk3036-pinctrl";
503 rockchip,grf = <&grf>;
504 #address-cells = <1>;
508 gpio0: gpio0@2007c000 {
509 compatible = "rockchip,gpio-bank";
510 reg = <0x2007c000 0x100>;
511 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
512 clocks = <&cru PCLK_GPIO0>;
517 interrupt-controller;
518 #interrupt-cells = <2>;
521 gpio1: gpio1@20080000 {
522 compatible = "rockchip,gpio-bank";
523 reg = <0x20080000 0x100>;
524 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
525 clocks = <&cru PCLK_GPIO1>;
530 interrupt-controller;
531 #interrupt-cells = <2>;
534 gpio2: gpio2@20084000 {
535 compatible = "rockchip,gpio-bank";
536 reg = <0x20084000 0x100>;
537 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
538 clocks = <&cru PCLK_GPIO2>;
543 interrupt-controller;
544 #interrupt-cells = <2>;
547 pcfg_pull_default: pcfg_pull_default {
548 bias-pull-pin-default;
551 pcfg_pull_none: pcfg-pull-none {
557 rockchip,pins = <0 RK_PA0 2 &pcfg_pull_none>;
563 rockchip,pins = <0 RK_PA1 2 &pcfg_pull_none>;
569 rockchip,pins = <0 RK_PA1 2 &pcfg_pull_none>;
575 rockchip,pins = <0 RK_PD3 1 &pcfg_pull_none>;
580 sdmmc_clk: sdmmc-clk {
581 rockchip,pins = <1 RK_PC0 1 &pcfg_pull_none>;
584 sdmmc_cmd: sdmmc-cmd {
585 rockchip,pins = <1 RK_PB7 1 &pcfg_pull_default>;
589 rockchip,pins = <1 RK_PC1 1 &pcfg_pull_default>;
592 sdmmc_bus1: sdmmc-bus1 {
593 rockchip,pins = <1 RK_PC2 1 &pcfg_pull_default>;
596 sdmmc_bus4: sdmmc-bus4 {
597 rockchip,pins = <1 RK_PC2 1 &pcfg_pull_default>,
598 <1 RK_PC3 1 &pcfg_pull_default>,
599 <1 RK_PC4 1 &pcfg_pull_default>,
600 <1 RK_PC5 1 &pcfg_pull_default>;
605 sdio_bus1: sdio-bus1 {
606 rockchip,pins = <0 RK_PB3 1 &pcfg_pull_default>;
609 sdio_bus4: sdio-bus4 {
610 rockchip,pins = <0 RK_PB3 1 &pcfg_pull_default>,
611 <0 RK_PB4 1 &pcfg_pull_default>,
612 <0 RK_PB5 1 &pcfg_pull_default>,
613 <0 RK_PB6 1 &pcfg_pull_default>;
617 rockchip,pins = <0 RK_PB0 1 &pcfg_pull_default>;
621 rockchip,pins = <0 RK_PB1 1 &pcfg_pull_none>;
627 * We run eMMC at max speed; bump up drive strength.
628 * We also have external pulls, so disable the internal ones.
631 rockchip,pins = <2 RK_PA4 2 &pcfg_pull_none>;
635 rockchip,pins = <2 RK_PA1 2 &pcfg_pull_default>;
638 emmc_bus8: emmc-bus8 {
639 rockchip,pins = <1 RK_PD0 2 &pcfg_pull_default>,
640 <1 RK_PD1 2 &pcfg_pull_default>,
641 <1 RK_PD2 2 &pcfg_pull_default>,
642 <1 RK_PD3 2 &pcfg_pull_default>,
643 <1 RK_PD4 2 &pcfg_pull_default>,
644 <1 RK_PD5 2 &pcfg_pull_default>,
645 <1 RK_PD6 2 &pcfg_pull_default>,
646 <1 RK_PD7 2 &pcfg_pull_default>;
651 flash_ale: flash-ale {
652 rockchip,pins = <2 RK_PA0 1 &pcfg_pull_default>;
655 flash_bus8: flash-bus8 {
656 rockchip,pins = <1 RK_PD0 1 &pcfg_pull_default>,
657 <1 RK_PD1 1 &pcfg_pull_default>,
658 <1 RK_PD2 1 &pcfg_pull_default>,
659 <1 RK_PD3 1 &pcfg_pull_default>,
660 <1 RK_PD4 1 &pcfg_pull_default>,
661 <1 RK_PD5 1 &pcfg_pull_default>,
662 <1 RK_PD6 1 &pcfg_pull_default>,
663 <1 RK_PD7 1 &pcfg_pull_default>;
666 flash_cle: flash-cle {
667 rockchip,pins = <2 RK_PA1 1 &pcfg_pull_default>;
670 flash_csn0: flash-csn0 {
671 rockchip,pins = <2 RK_PA6 1 &pcfg_pull_default>;
674 flash_rdn: flash-rdn {
675 rockchip,pins = <2 RK_PA3 1 &pcfg_pull_default>;
678 flash_rdy: flash-rdy {
679 rockchip,pins = <2 RK_PA4 1 &pcfg_pull_default>;
682 flash_wrn: flash-wrn {
683 rockchip,pins = <2 RK_PA2 1 &pcfg_pull_default>;
688 emac_xfer: emac-xfer {
689 rockchip,pins = <2 RK_PB2 1 &pcfg_pull_default>, /* crs_dvalid */
690 <2 RK_PB5 1 &pcfg_pull_default>, /* tx_en */
691 <2 RK_PB6 1 &pcfg_pull_default>, /* mac_clk */
692 <2 RK_PB7 1 &pcfg_pull_default>, /* rx_err */
693 <2 RK_PC0 1 &pcfg_pull_default>, /* rxd1 */
694 <2 RK_PC1 1 &pcfg_pull_default>, /* rxd0 */
695 <2 RK_PC2 1 &pcfg_pull_default>, /* txd1 */
696 <2 RK_PC3 1 &pcfg_pull_default>; /* txd0 */
699 emac_mdio: emac-mdio {
700 rockchip,pins = <2 RK_PB4 1 &pcfg_pull_default>, /* mac_md */
701 <2 RK_PD1 1 &pcfg_pull_default>; /* mac_mdclk */
706 i2c0_xfer: i2c0-xfer {
707 rockchip,pins = <0 RK_PA0 1 &pcfg_pull_none>,
708 <0 RK_PA1 1 &pcfg_pull_none>;
713 i2c1_xfer: i2c1-xfer {
714 rockchip,pins = <0 RK_PA2 1 &pcfg_pull_none>,
715 <0 RK_PA3 1 &pcfg_pull_none>;
720 i2c2_xfer: i2c2-xfer {
721 rockchip,pins = <2 RK_PC4 1 &pcfg_pull_none>,
722 <2 RK_PC5 1 &pcfg_pull_none>;
728 rockchip,pins = <1 RK_PA0 1 &pcfg_pull_default>,
729 <1 RK_PA1 1 &pcfg_pull_default>,
730 <1 RK_PA2 1 &pcfg_pull_default>,
731 <1 RK_PA3 1 &pcfg_pull_default>,
732 <1 RK_PA4 1 &pcfg_pull_default>,
733 <1 RK_PA5 1 &pcfg_pull_default>;
739 rockchip,pins = <1 RK_PB0 1 &pcfg_pull_none>,
740 <1 RK_PB1 1 &pcfg_pull_none>,
741 <1 RK_PB2 1 &pcfg_pull_none>,
742 <1 RK_PB3 1 &pcfg_pull_none>;
747 uart0_xfer: uart0-xfer {
748 rockchip,pins = <0 RK_PC0 1 &pcfg_pull_default>,
749 <0 RK_PC1 1 &pcfg_pull_none>;
752 uart0_cts: uart0-cts {
753 rockchip,pins = <0 RK_PC2 1 &pcfg_pull_default>;
756 uart0_rts: uart0-rts {
757 rockchip,pins = <0 RK_PC3 1 &pcfg_pull_none>;
762 uart1_xfer: uart1-xfer {
763 rockchip,pins = <2 RK_PC6 1 &pcfg_pull_default>,
764 <2 RK_PC7 1 &pcfg_pull_none>;
766 /* no rts / cts for uart1 */
770 uart2_xfer: uart2-xfer {
771 rockchip,pins = <1 RK_PC2 2 &pcfg_pull_default>,
772 <1 RK_PC3 2 &pcfg_pull_none>;
774 /* no rts / cts for uart2 */
779 rockchip,pins = <1 RK_PD5 3 &pcfg_pull_default>;
783 rockchip,pins = <1 RK_PD4 3 &pcfg_pull_default>;
787 rockchip,pins = <2 RK_PA0 2 &pcfg_pull_default>;
791 rockchip,pins = <1 RK_PD6 3 &pcfg_pull_default>;
796 rockchip,pins = <1 RK_PD7 3 &pcfg_pull_default>;