1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 #include <dt-bindings/gpio/gpio.h>
4 #include <dt-bindings/interrupt-controller/irq.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/pinctrl/rockchip.h>
7 #include <dt-bindings/clock/rk3036-cru.h>
8 #include <dt-bindings/soc/rockchip,boot-mode.h>
14 compatible = "rockchip,rk3036";
16 interrupt-parent = <&gic>;
34 enable-method = "rockchip,rk3036-smp";
38 compatible = "arm,cortex-a7";
40 resets = <&cru SRST_CORE0>;
45 clock-latency = <40000>;
46 clocks = <&cru ARMCLK>;
51 compatible = "arm,cortex-a7";
53 resets = <&cru SRST_CORE1>;
58 compatible = "simple-bus";
64 compatible = "arm,pl330", "arm,primecell";
65 reg = <0x20078000 0x4000>;
66 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
67 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
69 arm,pl330-broken-no-flushp;
70 clocks = <&cru ACLK_DMAC2>;
71 clock-names = "apb_pclk";
76 compatible = "arm,cortex-a7-pmu";
77 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
78 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
79 interrupt-affinity = <&cpu0>, <&cpu1>;
83 compatible = "rockchip,display-subsystem";
88 compatible = "arm,armv7-timer";
89 arm,cpu-registers-not-fw-configured;
90 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
91 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
92 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
93 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
94 clock-frequency = <24000000>;
98 compatible = "fixed-clock";
99 clock-frequency = <24000000>;
100 clock-output-names = "xin24m";
104 bus_intmem: sram@10080000 {
105 compatible = "mmio-sram";
106 reg = <0x10080000 0x2000>;
107 #address-cells = <1>;
109 ranges = <0 0x10080000 0x2000>;
112 compatible = "rockchip,rk3066-smp-sram";
118 compatible = "rockchip,rk3036-mali", "arm,mali-400";
119 reg = <0x10090000 0x10000>;
120 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
121 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
122 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
123 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
124 interrupt-names = "gp",
128 assigned-clocks = <&cru SCLK_GPU>;
129 assigned-clock-rates = <100000000>;
130 clocks = <&cru SCLK_GPU>, <&cru SCLK_GPU>;
131 clock-names = "core", "bus";
132 resets = <&cru SRST_GPU>;
137 compatible = "rockchip,rk3036-vop";
138 reg = <0x10118000 0x19c>;
139 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
140 clocks = <&cru ACLK_LCDC>, <&cru SCLK_LCDC>, <&cru HCLK_LCDC>;
141 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
142 resets = <&cru SRST_LCDC1_A>, <&cru SRST_LCDC1_H>, <&cru SRST_LCDC1_D>;
143 reset-names = "axi", "ahb", "dclk";
148 #address-cells = <1>;
150 vop_out_hdmi: endpoint@0 {
152 remote-endpoint = <&hdmi_in_vop>;
157 vop_mmu: iommu@10118300 {
158 compatible = "rockchip,iommu";
159 reg = <0x10118300 0x100>;
160 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
161 interrupt-names = "vop_mmu";
162 clocks = <&cru ACLK_LCDC>, <&cru HCLK_LCDC>;
163 clock-names = "aclk", "iface";
168 gic: interrupt-controller@10139000 {
169 compatible = "arm,gic-400";
170 interrupt-controller;
171 #interrupt-cells = <3>;
172 #address-cells = <0>;
174 reg = <0x10139000 0x1000>,
178 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
181 usb_otg: usb@10180000 {
182 compatible = "rockchip,rk3036-usb", "rockchip,rk3066-usb",
184 reg = <0x10180000 0x40000>;
185 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
186 clocks = <&cru HCLK_OTG0>;
189 g-np-tx-fifo-size = <16>;
190 g-rx-fifo-size = <275>;
191 g-tx-fifo-size = <256 128 128 64 64 32>;
195 usb_host: usb@101c0000 {
196 compatible = "rockchip,rk3036-usb", "rockchip,rk3066-usb",
198 reg = <0x101c0000 0x40000>;
199 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
200 clocks = <&cru HCLK_OTG1>;
206 emac: ethernet@10200000 {
207 compatible = "rockchip,rk3036-emac", "snps,arc-emac";
208 reg = <0x10200000 0x4000>;
209 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
210 #address-cells = <1>;
212 rockchip,grf = <&grf>;
213 clocks = <&cru HCLK_MAC>, <&cru SCLK_MACREF>, <&cru SCLK_MAC>;
214 clock-names = "hclk", "macref", "macclk";
216 * Fix the emac parent clock is DPLL instead of APLL.
217 * since that will cause some unstable things if the cpufreq
218 * is working. (e.g: the accurate 50MHz what mac_ref need)
220 assigned-clocks = <&cru SCLK_MACPLL>;
221 assigned-clock-parents = <&cru PLL_DPLL>;
227 sdmmc: mmc@10214000 {
228 compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc";
229 reg = <0x10214000 0x4000>;
230 clock-frequency = <37500000>;
231 max-frequency = <37500000>;
232 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
233 clock-names = "biu", "ciu";
234 fifo-depth = <0x100>;
235 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
236 resets = <&cru SRST_MMC0>;
237 reset-names = "reset";
242 compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc";
243 reg = <0x10218000 0x4000>;
244 max-frequency = <37500000>;
245 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
246 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
247 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
248 fifo-depth = <0x100>;
249 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
250 resets = <&cru SRST_SDIO>;
251 reset-names = "reset";
256 compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc";
257 reg = <0x1021c000 0x4000>;
258 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
261 clock-frequency = <37500000>;
262 max-frequency = <37500000>;
263 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
264 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
265 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
266 rockchip,default-sample-phase = <158>;
270 fifo-depth = <0x100>;
273 pinctrl-names = "default";
274 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
275 resets = <&cru SRST_EMMC>;
276 reset-names = "reset";
281 compatible = "rockchip,rk3036-i2s", "rockchip,rk3066-i2s";
282 reg = <0x10220000 0x4000>;
283 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
284 clock-names = "i2s_clk", "i2s_hclk";
285 clocks = <&cru SCLK_I2S>, <&cru HCLK_I2S>;
286 dmas = <&pdma 0>, <&pdma 1>;
287 dma-names = "tx", "rx";
288 pinctrl-names = "default";
289 pinctrl-0 = <&i2s_bus>;
290 #sound-dai-cells = <0>;
294 cru: clock-controller@20000000 {
295 compatible = "rockchip,rk3036-cru";
296 reg = <0x20000000 0x1000>;
297 rockchip,grf = <&grf>;
300 assigned-clocks = <&cru PLL_GPLL>;
301 assigned-clock-rates = <594000000>;
304 grf: syscon@20008000 {
305 compatible = "rockchip,rk3036-grf", "syscon", "simple-mfd";
306 reg = <0x20008000 0x1000>;
309 compatible = "syscon-reboot-mode";
311 mode-normal = <BOOT_NORMAL>;
312 mode-recovery = <BOOT_RECOVERY>;
313 mode-bootloader = <BOOT_FASTBOOT>;
314 mode-loader = <BOOT_BL_DOWNLOAD>;
318 acodec: acodec-ana@20030000 {
319 compatible = "rk3036-codec";
320 reg = <0x20030000 0x4000>;
321 rockchip,grf = <&grf>;
322 clock-names = "acodec_pclk";
323 clocks = <&cru PCLK_ACODEC>;
327 hdmi: hdmi@20034000 {
328 compatible = "rockchip,rk3036-inno-hdmi";
329 reg = <0x20034000 0x4000>;
330 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
331 clocks = <&cru PCLK_HDMI>;
332 clock-names = "pclk";
333 rockchip,grf = <&grf>;
334 pinctrl-names = "default";
335 pinctrl-0 = <&hdmi_ctl>;
339 #address-cells = <1>;
341 hdmi_in_vop: endpoint@0 {
343 remote-endpoint = <&vop_out_hdmi>;
348 timer: timer@20044000 {
349 compatible = "rockchip,rk3036-timer", "rockchip,rk3288-timer";
350 reg = <0x20044000 0x20>;
351 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
352 clocks = <&xin24m>, <&cru PCLK_TIMER>;
353 clock-names = "timer", "pclk";
357 compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm";
358 reg = <0x20050000 0x10>;
360 clocks = <&cru PCLK_PWM>;
362 pinctrl-names = "default";
363 pinctrl-0 = <&pwm0_pin>;
368 compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm";
369 reg = <0x20050010 0x10>;
371 clocks = <&cru PCLK_PWM>;
373 pinctrl-names = "default";
374 pinctrl-0 = <&pwm1_pin>;
379 compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm";
380 reg = <0x20050020 0x10>;
382 clocks = <&cru PCLK_PWM>;
384 pinctrl-names = "default";
385 pinctrl-0 = <&pwm2_pin>;
390 compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm";
391 reg = <0x20050030 0x10>;
393 clocks = <&cru PCLK_PWM>;
395 pinctrl-names = "default";
396 pinctrl-0 = <&pwm3_pin>;
401 compatible = "rockchip,rk3036-i2c", "rockchip,rk3288-i2c";
402 reg = <0x20056000 0x1000>;
403 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
404 #address-cells = <1>;
407 clocks = <&cru PCLK_I2C1>;
408 pinctrl-names = "default";
409 pinctrl-0 = <&i2c1_xfer>;
414 compatible = "rockchip,rk3036-i2c", "rockchip,rk3288-i2c";
415 reg = <0x2005a000 0x1000>;
416 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
417 #address-cells = <1>;
420 clocks = <&cru PCLK_I2C2>;
421 pinctrl-names = "default";
422 pinctrl-0 = <&i2c2_xfer>;
426 uart0: serial@20060000 {
427 compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart";
428 reg = <0x20060000 0x100>;
429 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
432 clock-frequency = <24000000>;
433 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
434 clock-names = "baudclk", "apb_pclk";
435 pinctrl-names = "default";
436 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
440 uart1: serial@20064000 {
441 compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart";
442 reg = <0x20064000 0x100>;
443 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
446 clock-frequency = <24000000>;
447 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
448 clock-names = "baudclk", "apb_pclk";
449 pinctrl-names = "default";
450 pinctrl-0 = <&uart1_xfer>;
454 uart2: serial@20068000 {
455 compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart";
456 reg = <0x20068000 0x100>;
457 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
460 clock-frequency = <24000000>;
461 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
462 clock-names = "baudclk", "apb_pclk";
463 pinctrl-names = "default";
464 pinctrl-0 = <&uart2_xfer>;
469 compatible = "rockchip,rk3036-i2c", "rockchip,rk3288-i2c";
470 reg = <0x20072000 0x1000>;
471 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
472 #address-cells = <1>;
475 clocks = <&cru PCLK_I2C0>;
476 pinctrl-names = "default";
477 pinctrl-0 = <&i2c0_xfer>;
482 compatible = "rockchip,rockchip-spi";
483 reg = <0x20074000 0x1000>;
484 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
485 clocks = <&cru PCLK_SPI>, <&cru SCLK_SPI>;
486 clock-names = "apb-pclk","spi_pclk";
487 dmas = <&pdma 8>, <&pdma 9>;
488 dma-names = "tx", "rx";
489 pinctrl-names = "default";
490 pinctrl-0 = <&spi_txd &spi_rxd &spi_clk &spi_cs0>;
491 #address-cells = <1>;
497 compatible = "rockchip,rk3036-pinctrl";
498 rockchip,grf = <&grf>;
499 #address-cells = <1>;
503 gpio0: gpio0@2007c000 {
504 compatible = "rockchip,gpio-bank";
505 reg = <0x2007c000 0x100>;
506 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
507 clocks = <&cru PCLK_GPIO0>;
512 interrupt-controller;
513 #interrupt-cells = <2>;
516 gpio1: gpio1@20080000 {
517 compatible = "rockchip,gpio-bank";
518 reg = <0x20080000 0x100>;
519 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
520 clocks = <&cru PCLK_GPIO1>;
525 interrupt-controller;
526 #interrupt-cells = <2>;
529 gpio2: gpio2@20084000 {
530 compatible = "rockchip,gpio-bank";
531 reg = <0x20084000 0x100>;
532 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
533 clocks = <&cru PCLK_GPIO2>;
538 interrupt-controller;
539 #interrupt-cells = <2>;
542 pcfg_pull_default: pcfg_pull_default {
543 bias-pull-pin-default;
546 pcfg_pull_none: pcfg-pull-none {
552 rockchip,pins = <0 RK_PA0 2 &pcfg_pull_none>;
558 rockchip,pins = <0 RK_PA1 2 &pcfg_pull_none>;
564 rockchip,pins = <0 RK_PA1 2 &pcfg_pull_none>;
570 rockchip,pins = <0 RK_PD3 1 &pcfg_pull_none>;
575 sdmmc_clk: sdmmc-clk {
576 rockchip,pins = <1 RK_PC0 1 &pcfg_pull_none>;
579 sdmmc_cmd: sdmmc-cmd {
580 rockchip,pins = <1 RK_PB7 1 &pcfg_pull_default>;
584 rockchip,pins = <1 RK_PC1 1 &pcfg_pull_default>;
587 sdmmc_bus1: sdmmc-bus1 {
588 rockchip,pins = <1 RK_PC2 1 &pcfg_pull_default>;
591 sdmmc_bus4: sdmmc-bus4 {
592 rockchip,pins = <1 RK_PC2 1 &pcfg_pull_default>,
593 <1 RK_PC3 1 &pcfg_pull_default>,
594 <1 RK_PC4 1 &pcfg_pull_default>,
595 <1 RK_PC5 1 &pcfg_pull_default>;
600 sdio_bus1: sdio-bus1 {
601 rockchip,pins = <0 RK_PB3 1 &pcfg_pull_default>;
604 sdio_bus4: sdio-bus4 {
605 rockchip,pins = <0 RK_PB3 1 &pcfg_pull_default>,
606 <0 RK_PB4 1 &pcfg_pull_default>,
607 <0 RK_PB5 1 &pcfg_pull_default>,
608 <0 RK_PB6 1 &pcfg_pull_default>;
612 rockchip,pins = <0 RK_PB0 1 &pcfg_pull_default>;
616 rockchip,pins = <0 RK_PB1 1 &pcfg_pull_none>;
622 * We run eMMC at max speed; bump up drive strength.
623 * We also have external pulls, so disable the internal ones.
626 rockchip,pins = <2 RK_PA4 2 &pcfg_pull_none>;
630 rockchip,pins = <2 RK_PA1 2 &pcfg_pull_default>;
633 emmc_bus8: emmc-bus8 {
634 rockchip,pins = <1 RK_PD0 2 &pcfg_pull_default>,
635 <1 RK_PD1 2 &pcfg_pull_default>,
636 <1 RK_PD2 2 &pcfg_pull_default>,
637 <1 RK_PD3 2 &pcfg_pull_default>,
638 <1 RK_PD4 2 &pcfg_pull_default>,
639 <1 RK_PD5 2 &pcfg_pull_default>,
640 <1 RK_PD6 2 &pcfg_pull_default>,
641 <1 RK_PD7 2 &pcfg_pull_default>;
646 emac_xfer: emac-xfer {
647 rockchip,pins = <2 RK_PB2 1 &pcfg_pull_default>, /* crs_dvalid */
648 <2 RK_PB5 1 &pcfg_pull_default>, /* tx_en */
649 <2 RK_PB6 1 &pcfg_pull_default>, /* mac_clk */
650 <2 RK_PB7 1 &pcfg_pull_default>, /* rx_err */
651 <2 RK_PC0 1 &pcfg_pull_default>, /* rxd1 */
652 <2 RK_PC1 1 &pcfg_pull_default>, /* rxd0 */
653 <2 RK_PC2 1 &pcfg_pull_default>, /* txd1 */
654 <2 RK_PC3 1 &pcfg_pull_default>; /* txd0 */
657 emac_mdio: emac-mdio {
658 rockchip,pins = <2 RK_PB4 1 &pcfg_pull_default>, /* mac_md */
659 <2 RK_PD1 1 &pcfg_pull_default>; /* mac_mdclk */
664 i2c0_xfer: i2c0-xfer {
665 rockchip,pins = <0 RK_PA0 1 &pcfg_pull_none>,
666 <0 RK_PA1 1 &pcfg_pull_none>;
671 i2c1_xfer: i2c1-xfer {
672 rockchip,pins = <0 RK_PA2 1 &pcfg_pull_none>,
673 <0 RK_PA3 1 &pcfg_pull_none>;
678 i2c2_xfer: i2c2-xfer {
679 rockchip,pins = <2 RK_PC4 1 &pcfg_pull_none>,
680 <2 RK_PC5 1 &pcfg_pull_none>;
686 rockchip,pins = <1 RK_PA0 1 &pcfg_pull_default>,
687 <1 RK_PA1 1 &pcfg_pull_default>,
688 <1 RK_PA2 1 &pcfg_pull_default>,
689 <1 RK_PA3 1 &pcfg_pull_default>,
690 <1 RK_PA4 1 &pcfg_pull_default>,
691 <1 RK_PA5 1 &pcfg_pull_default>;
697 rockchip,pins = <1 RK_PB0 1 &pcfg_pull_none>,
698 <1 RK_PB1 1 &pcfg_pull_none>,
699 <1 RK_PB2 1 &pcfg_pull_none>,
700 <1 RK_PB3 1 &pcfg_pull_none>;
705 uart0_xfer: uart0-xfer {
706 rockchip,pins = <0 RK_PC0 1 &pcfg_pull_default>,
707 <0 RK_PC1 1 &pcfg_pull_none>;
710 uart0_cts: uart0-cts {
711 rockchip,pins = <0 RK_PC2 1 &pcfg_pull_default>;
714 uart0_rts: uart0-rts {
715 rockchip,pins = <0 RK_PC3 1 &pcfg_pull_none>;
720 uart1_xfer: uart1-xfer {
721 rockchip,pins = <2 RK_PC6 1 &pcfg_pull_default>,
722 <2 RK_PC7 1 &pcfg_pull_none>;
724 /* no rts / cts for uart1 */
728 uart2_xfer: uart2-xfer {
729 rockchip,pins = <1 RK_PC2 2 &pcfg_pull_default>,
730 <1 RK_PC3 2 &pcfg_pull_none>;
732 /* no rts / cts for uart2 */
737 rockchip,pins = <1 RK_PD5 3 &pcfg_pull_default>;
741 rockchip,pins = <1 RK_PD4 3 &pcfg_pull_default>;
745 rockchip,pins = <2 RK_PA0 2 &pcfg_pull_default>;
749 rockchip,pins = <1 RK_PD6 3 &pcfg_pull_default>;
754 rockchip,pins = <1 RK_PD7 3 &pcfg_pull_default>;