arch/arm/boot/dts/qcom-mdm9615.dtsi

   1 /*
   2  * Device Tree Source for Qualcomm MDM9615 SoC
   3  *
   4  * Copyright (C) 2016 BayLibre, SAS.
   5  * Author : Neil Armstrong <narmstrong@baylibre.com>
   6  *
   7  * This file is dual-licensed: you can use it either under the terms
   8  * of the GPL or the X11 license, at your option. Note that this dual
   9  * licensing only applies to this file, and not this project as a
  10  * whole.
  11  *
  12  *  a) This file is free software; you can redistribute it and/or
  13  *     modify it under the terms of the GNU General Public License as
  14  *     published by the Free Software Foundation; either version 2 of the
  15  *     License, or (at your option) any later version.
  16  *
  17  *     This file is distributed in the hope that it will be useful,
  18  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  19  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  20  *     GNU General Public License for more details.
  21  *
  22  * Or, alternatively,
  23  *
  24  *  b) Permission is hereby granted, free of charge, to any person
  25  *     obtaining a copy of this software and associated documentation
  26  *     files (the "Software"), to deal in the Software without
  27  *     restriction, including without limitation the rights to use,
  28  *     copy, modify, merge, publish, distribute, sublicense, and/or
  29  *     sell copies of the Software, and to permit persons to whom the
  30  *     Software is furnished to do so, subject to the following
  31  *     conditions:
  32  *
  33  *     The above copyright notice and this permission notice shall be
  34  *     included in all copies or substantial portions of the Software.
  35  *
  36  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  37  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  38  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  39  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  40  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  41  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  42  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  43  *     OTHER DEALINGS IN THE SOFTWARE.
  44  */
  45
  46 /dts-v1/;
  47
  48 #include <dt-bindings/interrupt-controller/arm-gic.h>
  49 #include <dt-bindings/clock/qcom,gcc-mdm9615.h>
  50 #include <dt-bindings/reset/qcom,gcc-mdm9615.h>
  51 #include <dt-bindings/mfd/qcom-rpm.h>
  52 #include <dt-bindings/soc/qcom,gsbi.h>
  53
  54 / {
  55         #address-cells = <1>;
  56         #size-cells = <1>;
  57         model = "Qualcomm MDM9615";
  58         compatible = "qcom,mdm9615";
  59         interrupt-parent = <&intc>;
  60
  61         cpus {
  62                 #address-cells = <1>;
  63                 #size-cells = <0>;
  64
  65                 cpu0: cpu@0 {
  66                         compatible = "arm,cortex-a5";
  67                         device_type = "cpu";
  68                         next-level-cache = <&L2>;
  69                 };
  70         };
  71
  72         cpu-pmu {
  73                 compatible = "arm,cortex-a5-pmu";
  74                 interrupts = <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
  75         };
  76
  77         clocks {
  78                 cxo_board {
  79                         compatible = "fixed-clock";
  80                         #clock-cells = <0>;
  81                         clock-frequency = <19200000>;
  82                 };
  83         };
  84
  85         regulators {
  86                 vsdcc_fixed: vsdcc-regulator {
  87                         compatible = "regulator-fixed";
  88                         regulator-name = "SDCC Power";
  89                         regulator-min-microvolt = <2700000>;
  90                         regulator-max-microvolt = <2700000>;
  91                         regulator-always-on;
  92                 };
  93         };
  94
  95         soc: soc {
  96                 #address-cells = <1>;
  97                 #size-cells = <1>;
  98                 ranges;
  99                 compatible = "simple-bus";
 100
 101                 L2: cache-controller@2040000 {
 102                         compatible = "arm,pl310-cache";
 103                         reg = <0x02040000 0x1000>;
 104                         arm,data-latency = <2 2 0>;
 105                         cache-unified;
 106                         cache-level = <2>;
 107                 };
 108
 109                 intc: interrupt-controller@2000000 {
 110                         compatible = "qcom,msm-qgic2";
 111                         interrupt-controller;
 112                         #interrupt-cells = <3>;
 113                         reg = <0x02000000 0x1000>,
 114                               <0x02002000 0x1000>;
 115                 };
 116
 117                 timer@200a000 {
 118                         compatible = "qcom,kpss-timer", "qcom,msm-timer";
 119                         interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_EDGE_RISING)>,
 120                                      <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_EDGE_RISING)>,
 121                                      <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_EDGE_RISING)>;
 122                         reg = <0x0200a000 0x100>;
 123                         clock-frequency = <27000000>,
 124                                           <32768>;
 125                         cpu-offset = <0x80000>;
 126                 };
 127
 128                 msmgpio: pinctrl@800000 {
 129                         compatible = "qcom,mdm9615-pinctrl";
 130                         gpio-controller;
 131                         gpio-ranges = <&msmgpio 0 0 88>;
 132                         #gpio-cells = <2>;
 133                         interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 134                         interrupt-controller;
 135                         #interrupt-cells = <2>;
 136                         reg = <0x800000 0x4000>;
 137                 };
 138
 139                 gcc: clock-controller@900000 {
 140                         compatible = "qcom,gcc-mdm9615";
 141                         #clock-cells = <1>;
 142                         #reset-cells = <1>;
 143                         reg = <0x900000 0x4000>;
 144                 };
 145
 146                 lcc: clock-controller@28000000 {
 147                         compatible = "qcom,lcc-mdm9615";
 148                         reg = <0x28000000 0x1000>;
 149                         #clock-cells = <1>;
 150                         #reset-cells = <1>;
 151                 };
 152
 153                 l2cc: clock-controller@2011000 {
 154                         compatible = "syscon";
 155                         reg = <0x02011000 0x1000>;
 156                 };
 157
 158                 rng@1a500000 {
 159                         compatible = "qcom,prng";
 160                         reg = <0x1a500000 0x200>;
 161                         clocks = <&gcc PRNG_CLK>;
 162                         clock-names = "core";
 163                         assigned-clocks = <&gcc PRNG_CLK>;
 164                         assigned-clock-rates = <32000000>;
 165                 };
 166
 167                 gsbi2: gsbi@16100000 {
 168                         compatible = "qcom,gsbi-v1.0.0";
 169                         cell-index = <2>;
 170                         reg = <0x16100000 0x100>;
 171                         clocks = <&gcc GSBI2_H_CLK>;
 172                         clock-names = "iface";
 173                         status = "disabled";
 174                         #address-cells = <1>;
 175                         #size-cells = <1>;
 176                         ranges;
 177
 178                         gsbi2_i2c: i2c@16180000 {
 179                                 compatible = "qcom,i2c-qup-v1.1.1";
 180                                 #address-cells = <1>;
 181                                 #size-cells = <0>;
 182                                 reg = <0x16180000 0x1000>;
 183                                 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
 184
 185                                 clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>;
 186                                 clock-names = "core", "iface";
 187                                 status = "disabled";
 188                         };
 189                 };
 190
 191                 gsbi3: gsbi@16200000 {
 192                         compatible = "qcom,gsbi-v1.0.0";
 193                         cell-index = <3>;
 194                         reg = <0x16200000 0x100>;
 195                         clocks = <&gcc GSBI3_H_CLK>;
 196                         clock-names = "iface";
 197                         status = "disabled";
 198                         #address-cells = <1>;
 199                         #size-cells = <1>;
 200                         ranges;
 201
 202                         gsbi3_spi: spi@16280000 {
 203                                 compatible = "qcom,spi-qup-v1.1.1";
 204                                 #address-cells = <1>;
 205                                 #size-cells = <0>;
 206                                 reg = <0x16280000 0x1000>;
 207                                 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
 208                                 spi-max-frequency = <24000000>;
 209
 210                                 clocks = <&gcc GSBI3_QUP_CLK>, <&gcc GSBI3_H_CLK>;
 211                                 clock-names = "core", "iface";
 212                                 status = "disabled";
 213                         };
 214                 };
 215
 216                 gsbi4: gsbi@16300000 {
 217                         compatible = "qcom,gsbi-v1.0.0";
 218                         cell-index = <4>;
 219                         reg = <0x16300000 0x100>;
 220                         clocks = <&gcc GSBI4_H_CLK>;
 221                         clock-names = "iface";
 222                         status = "disabled";
 223                         #address-cells = <1>;
 224                         #size-cells = <1>;
 225                         ranges;
 226
 227                         syscon-tcsr = <&tcsr>;
 228
 229                         gsbi4_serial: serial@16340000 {
 230                                 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
 231                                 reg = <0x16340000 0x1000>,
 232                                       <0x16300000 0x1000>;
 233                                 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
 234                                 clocks = <&gcc GSBI4_UART_CLK>, <&gcc GSBI4_H_CLK>;
 235                                 clock-names = "core", "iface";
 236                                 status = "disabled";
 237                         };
 238                 };
 239
 240                 gsbi5: gsbi@16400000 {
 241                         compatible = "qcom,gsbi-v1.0.0";
 242                         cell-index = <5>;
 243                         reg = <0x16400000 0x100>;
 244                         clocks = <&gcc GSBI5_H_CLK>;
 245                         clock-names = "iface";
 246                         status = "disabled";
 247                         #address-cells = <1>;
 248                         #size-cells = <1>;
 249                         ranges;
 250
 251                         syscon-tcsr = <&tcsr>;
 252
 253                         gsbi5_i2c: i2c@16480000 {
 254                                 compatible = "qcom,i2c-qup-v1.1.1";
 255                                 #address-cells = <1>;
 256                                 #size-cells = <0>;
 257                                 reg = <0x16480000 0x1000>;
 258                                 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
 259
 260                                 /* QUP clock is not initialized, set rate */
 261                                 assigned-clocks = <&gcc GSBI5_QUP_CLK>;
 262                                 assigned-clock-rates = <24000000>;
 263
 264                                 clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
 265                                 clock-names = "core", "iface";
 266                                 status = "disabled";
 267                         };
 268
 269                         gsbi5_serial: serial@16440000 {
 270                                 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
 271                                 reg = <0x16440000 0x1000>,
 272                                       <0x16400000 0x1000>;
 273                                 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
 274                                 clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
 275                                 clock-names = "core", "iface";
 276                                 status = "disabled";
 277                         };
 278                 };
 279
 280                 qcom,ssbi@500000 {
 281                         compatible = "qcom,ssbi";
 282                         reg = <0x500000 0x1000>;
 283                         qcom,controller-type = "pmic-arbiter";
 284
 285                         pmicintc: pmic@0 {
 286                                 compatible = "qcom,pm8018", "qcom,pm8921";
 287                                 interrupts = <GIC_PPI 226 IRQ_TYPE_LEVEL_HIGH>;
 288                                 #interrupt-cells = <2>;
 289                                 interrupt-controller;
 290                                 #address-cells = <1>;
 291                                 #size-cells = <0>;
 292
 293                                 pwrkey@1c {
 294                                         compatible = "qcom,pm8018-pwrkey", "qcom,pm8921-pwrkey";
 295                                         reg = <0x1c>;
 296                                         interrupt-parent = <&pmicintc>;
 297                                         interrupts = <50 IRQ_TYPE_EDGE_RISING>,
 298                                                      <51 IRQ_TYPE_EDGE_RISING>;
 299                                         debounce = <15625>;
 300                                         pull-up;
 301                                 };
 302
 303                                 pmicmpp: mpp@50 {
 304                                         compatible = "qcom,pm8018-mpp", "qcom,ssbi-mpp";
 305                                         interrupt-parent = <&pmicintc>;
 306                                         interrupts = <24 IRQ_TYPE_NONE>,
 307                                                      <25 IRQ_TYPE_NONE>,
 308                                                      <26 IRQ_TYPE_NONE>,
 309                                                      <27 IRQ_TYPE_NONE>,
 310                                                      <28 IRQ_TYPE_NONE>,
 311                                                      <29 IRQ_TYPE_NONE>;
 312                                         reg = <0x50>;
 313                                         gpio-controller;
 314                                         #gpio-cells = <2>;
 315                                 };
 316
 317                                 rtc@11d {
 318                                         compatible = "qcom,pm8018-rtc", "qcom,pm8921-rtc";
 319                                         interrupt-parent = <&pmicintc>;
 320                                         interrupts = <39 IRQ_TYPE_EDGE_RISING>;
 321                                         reg = <0x11d>;
 322                                         allow-set-time;
 323                                 };
 324
 325                                 pmicgpio: gpio@150 {
 326                                         compatible = "qcom,pm8018-gpio", "qcom,ssbi-gpio";
 327                                         interrupt-controller;
 328                                         #interrupt-cells = <2>;
 329                                         gpio-controller;
 330                                         gpio-ranges = <&pmicgpio 0 0 6>;
 331                                         #gpio-cells = <2>;
 332                                 };
 333                         };
 334                 };
 335
 336                 sdcc1bam: dma@12182000{
 337                         compatible = "qcom,bam-v1.3.0";
 338                         reg = <0x12182000 0x8000>;
 339                         interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
 340                         clocks = <&gcc SDC1_H_CLK>;
 341                         clock-names = "bam_clk";
 342                         #dma-cells = <1>;
 343                         qcom,ee = <0>;
 344                 };
 345
 346                 sdcc2bam: dma@12142000{
 347                         compatible = "qcom,bam-v1.3.0";
 348                         reg = <0x12142000 0x8000>;
 349                         interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 350                         clocks = <&gcc SDC2_H_CLK>;
 351                         clock-names = "bam_clk";
 352                         #dma-cells = <1>;
 353                         qcom,ee = <0>;
 354                 };
 355
 356                 amba {
 357                         compatible = "simple-bus";
 358                         #address-cells = <1>;
 359                         #size-cells = <1>;
 360                         ranges;
 361                         sdcc1: sdcc@12180000 {
 362                                 status = "disabled";
 363                                 compatible = "arm,pl18x", "arm,primecell";
 364                                 arm,primecell-periphid = <0x00051180>;
 365                                 reg = <0x12180000 0x2000>;
 366                                 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
 367                                 interrupt-names = "cmd_irq";
 368                                 clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
 369                                 clock-names = "mclk", "apb_pclk";
 370                                 bus-width = <8>;
 371                                 max-frequency = <48000000>;
 372                                 cap-sd-highspeed;
 373                                 cap-mmc-highspeed;
 374                                 vmmc-supply = <&vsdcc_fixed>;
 375                                 dmas = <&sdcc1bam 2>, <&sdcc1bam 1>;
 376                                 dma-names = "tx", "rx";
 377                                 assigned-clocks = <&gcc SDC1_CLK>;
 378                                 assigned-clock-rates = <400000>;
 379                         };
 380
 381                         sdcc2: sdcc@12140000 {
 382                                 compatible = "arm,pl18x", "arm,primecell";
 383                                 arm,primecell-periphid = <0x00051180>;
 384                                 status = "disabled";
 385                                 reg = <0x12140000 0x2000>;
 386                                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 387                                 interrupt-names = "cmd_irq";
 388                                 clocks = <&gcc SDC2_CLK>, <&gcc SDC2_H_CLK>;
 389                                 clock-names = "mclk", "apb_pclk";
 390                                 bus-width = <4>;
 391                                 cap-sd-highspeed;
 392                                 cap-mmc-highspeed;
 393                                 max-frequency = <48000000>;
 394                                 no-1-8-v;
 395                                 vmmc-supply = <&vsdcc_fixed>;
 396                                 dmas = <&sdcc2bam 2>, <&sdcc2bam 1>;
 397                                 dma-names = "tx", "rx";
 398                                 assigned-clocks = <&gcc SDC2_CLK>;
 399                                 assigned-clock-rates = <400000>;
 400                         };
 401                 };
 402
 403                 tcsr: syscon@1a400000 {
 404                         compatible = "qcom,tcsr-mdm9615", "syscon";
 405                         reg = <0x1a400000 0x100>;
 406                 };
 407
 408                 rpm: rpm@108000 {
 409                         compatible = "qcom,rpm-mdm9615";
 410                         reg = <0x108000 0x1000>;
 411
 412                         qcom,ipc = <&l2cc 0x8 2>;
 413
 414                         interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>,
 415                                      <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
 416                                      <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>;
 417                         interrupt-names = "ack", "err", "wakeup";
 418
 419                         regulators {
 420                                 compatible = "qcom,rpm-pm8018-regulators";
 421
 422                                 vin_lvs1-supply = <&pm8018_s3>;
 423
 424                                 vdd_l7-supply = <&pm8018_s4>;
 425                                 vdd_l8-supply = <&pm8018_s3>;
 426                                 vdd_l9_l10_l11_l12-supply = <&pm8018_s5>;
 427
 428                                 /* Buck SMPS */
 429                                 pm8018_s1: s1 {
 430                                         regulator-min-microvolt = <500000>;
 431                                         regulator-max-microvolt = <1150000>;
 432                                         qcom,switch-mode-frequency = <1600000>;
 433                                         bias-pull-down;
 434                                 };
 435
 436                                 pm8018_s2: s2 {
 437                                         regulator-min-microvolt = <1225000>;
 438                                         regulator-max-microvolt = <1300000>;
 439                                         qcom,switch-mode-frequency = <1600000>;
 440                                         bias-pull-down;
 441                                 };
 442
 443                                 pm8018_s3: s3 {
 444                                         regulator-always-on;
 445                                         regulator-min-microvolt = <1800000>;
 446                                         regulator-max-microvolt = <1800000>;
 447                                         qcom,switch-mode-frequency = <1600000>;
 448                                         bias-pull-down;
 449                                 };
 450
 451                                 pm8018_s4: s4 {
 452                                         regulator-min-microvolt = <2100000>;
 453                                         regulator-max-microvolt = <2200000>;
 454                                         qcom,switch-mode-frequency = <1600000>;
 455                                         bias-pull-down;
 456                                 };
 457
 458                                 pm8018_s5: s5 {
 459                                         regulator-always-on;
 460                                         regulator-min-microvolt = <1350000>;
 461                                         regulator-max-microvolt = <1350000>;
 462                                         qcom,switch-mode-frequency = <1600000>;
 463                                         bias-pull-down;
 464                                 };
 465
 466                                 /* PMOS LDO */
 467                                 pm8018_l2: l2 {
 468                                         regulator-always-on;
 469                                         regulator-min-microvolt = <1800000>;
 470                                         regulator-max-microvolt = <1800000>;
 471                                         bias-pull-down;
 472                                 };
 473
 474                                 pm8018_l3: l3 {
 475                                         regulator-always-on;
 476                                         regulator-min-microvolt = <1800000>;
 477                                         regulator-max-microvolt = <1800000>;
 478                                         bias-pull-down;
 479                                 };
 480
 481                                 pm8018_l4: l4 {
 482                                         regulator-min-microvolt = <3300000>;
 483                                         regulator-max-microvolt = <3300000>;
 484                                         bias-pull-down;
 485                                 };
 486
 487                                 pm8018_l5: l5 {
 488                                         regulator-min-microvolt = <2850000>;
 489                                         regulator-max-microvolt = <2850000>;
 490                                         bias-pull-down;
 491                                 };
 492
 493                                 pm8018_l6: l6 {
 494                                         regulator-min-microvolt = <1800000>;
 495                                         regulator-max-microvolt = <2850000>;
 496                                         bias-pull-down;
 497                                 };
 498
 499                                 pm8018_l7: l7 {
 500                                         regulator-min-microvolt = <1850000>;
 501                                         regulator-max-microvolt = <1900000>;
 502                                         bias-pull-down;
 503                                 };
 504
 505                                 pm8018_l8: l8 {
 506                                         regulator-min-microvolt = <1200000>;
 507                                         regulator-max-microvolt = <1200000>;
 508                                         bias-pull-down;
 509                                 };
 510
 511                                 pm8018_l9: l9 {
 512                                         regulator-min-microvolt = <750000>;
 513                                         regulator-max-microvolt = <1150000>;
 514                                         bias-pull-down;
 515                                 };
 516
 517                                 pm8018_l10: l10 {
 518                                         regulator-min-microvolt = <1050000>;
 519                                         regulator-max-microvolt = <1050000>;
 520                                         bias-pull-down;
 521                                 };
 522
 523                                 pm8018_l11: l11 {
 524                                         regulator-min-microvolt = <1050000>;
 525                                         regulator-max-microvolt = <1050000>;
 526                                         bias-pull-down;
 527                                 };
 528
 529                                 pm8018_l12: l12 {
 530                                         regulator-min-microvolt = <1050000>;
 531                                         regulator-max-microvolt = <1050000>;
 532                                         bias-pull-down;
 533                                 };
 534
 535                                 pm8018_l13: l13 {
 536                                         regulator-min-microvolt = <1850000>;
 537                                         regulator-max-microvolt = <2950000>;
 538                                         bias-pull-down;
 539                                 };
 540
 541                                 pm8018_l14: l14 {
 542                                         regulator-min-microvolt = <2850000>;
 543                                         regulator-max-microvolt = <2850000>;
 544                                         bias-pull-down;
 545                                 };
 546
 547                                 /* Low Voltage Switch */
 548                                 pm8018_lvs1: lvs1 {
 549                                         bias-pull-down;
 550                                 };
 551                         };
 552                 };
 553         };
 554 };