arch/arm/boot/dts/omap4-l4-abe.dtsi

   1 &l4_abe {                                               /* 0x40100000 */
   2         compatible = "ti,omap4-l4-abe", "simple-pm-bus";
   3         reg = <0x40100000 0x400>,
   4               <0x40100400 0x400>;
   5         reg-names = "la", "ap";
   6         power-domains = <&prm_abe>;
   7         /* OMAP4_L4_ABE_CLKCTRL is read-only */
   8         #address-cells = <1>;
   9         #size-cells = <1>;
  10         ranges = <0x00000000 0x40100000 0x100000>,      /* segment 0 */
  11                  <0x49000000 0x49000000 0x100000>;
  12         segment@0 {                                     /* 0x40100000 */
  13                 compatible = "simple-pm-bus";
  14                 #address-cells = <1>;
  15                 #size-cells = <1>;
  16                 ranges =
  17                          /* CPU to L4 ABE mapping */
  18                          <0x00000000 0x00000000 0x000400>,      /* ap 0 */
  19                          <0x00000400 0x00000400 0x000400>,      /* ap 1 */
  20                          <0x00022000 0x00022000 0x001000>,      /* ap 2 */
  21                          <0x00023000 0x00023000 0x001000>,      /* ap 3 */
  22                          <0x00024000 0x00024000 0x001000>,      /* ap 4 */
  23                          <0x00025000 0x00025000 0x001000>,      /* ap 5 */
  24                          <0x00026000 0x00026000 0x001000>,      /* ap 6 */
  25                          <0x00027000 0x00027000 0x001000>,      /* ap 7 */
  26                          <0x00028000 0x00028000 0x001000>,      /* ap 8 */
  27                          <0x00029000 0x00029000 0x001000>,      /* ap 9 */
  28                          <0x0002a000 0x0002a000 0x001000>,      /* ap 10 */
  29                          <0x0002b000 0x0002b000 0x001000>,      /* ap 11 */
  30                          <0x0002e000 0x0002e000 0x001000>,      /* ap 12 */
  31                          <0x0002f000 0x0002f000 0x001000>,      /* ap 13 */
  32                          <0x00030000 0x00030000 0x001000>,      /* ap 14 */
  33                          <0x00031000 0x00031000 0x001000>,      /* ap 15 */
  34                          <0x00032000 0x00032000 0x001000>,      /* ap 16 */
  35                          <0x00033000 0x00033000 0x001000>,      /* ap 17 */
  36                          <0x00038000 0x00038000 0x001000>,      /* ap 18 */
  37                          <0x00039000 0x00039000 0x001000>,      /* ap 19 */
  38                          <0x0003a000 0x0003a000 0x001000>,      /* ap 20 */
  39                          <0x0003b000 0x0003b000 0x001000>,      /* ap 21 */
  40                          <0x0003c000 0x0003c000 0x001000>,      /* ap 22 */
  41                          <0x0003d000 0x0003d000 0x001000>,      /* ap 23 */
  42                          <0x0003e000 0x0003e000 0x001000>,      /* ap 24 */
  43                          <0x0003f000 0x0003f000 0x001000>,      /* ap 25 */
  44                          <0x00080000 0x00080000 0x010000>,      /* ap 26 */
  45                          <0x00080000 0x00080000 0x001000>,      /* ap 27 */
  46                          <0x000a0000 0x000a0000 0x010000>,      /* ap 28 */
  47                          <0x000a0000 0x000a0000 0x001000>,      /* ap 29 */
  48                          <0x000c0000 0x000c0000 0x010000>,      /* ap 30 */
  49                          <0x000c0000 0x000c0000 0x001000>,      /* ap 31 */
  50                          <0x000f1000 0x000f1000 0x001000>,      /* ap 32 */
  51                          <0x000f2000 0x000f2000 0x001000>,      /* ap 33 */
  52
  53                          /* L3 to L4 ABE mapping */
  54                          <0x49000000 0x49000000 0x000400>,      /* ap 0 */
  55                          <0x49000400 0x49000400 0x000400>,      /* ap 1 */
  56                          <0x49022000 0x49022000 0x001000>,      /* ap 2 */
  57                          <0x49023000 0x49023000 0x001000>,      /* ap 3 */
  58                          <0x49024000 0x49024000 0x001000>,      /* ap 4 */
  59                          <0x49025000 0x49025000 0x001000>,      /* ap 5 */
  60                          <0x49026000 0x49026000 0x001000>,      /* ap 6 */
  61                          <0x49027000 0x49027000 0x001000>,      /* ap 7 */
  62                          <0x49028000 0x49028000 0x001000>,      /* ap 8 */
  63                          <0x49029000 0x49029000 0x001000>,      /* ap 9 */
  64                          <0x4902a000 0x4902a000 0x001000>,      /* ap 10 */
  65                          <0x4902b000 0x4902b000 0x001000>,      /* ap 11 */
  66                          <0x4902e000 0x4902e000 0x001000>,      /* ap 12 */
  67                          <0x4902f000 0x4902f000 0x001000>,      /* ap 13 */
  68                          <0x49030000 0x49030000 0x001000>,      /* ap 14 */
  69                          <0x49031000 0x49031000 0x001000>,      /* ap 15 */
  70                          <0x49032000 0x49032000 0x001000>,      /* ap 16 */
  71                          <0x49033000 0x49033000 0x001000>,      /* ap 17 */
  72                          <0x49038000 0x49038000 0x001000>,      /* ap 18 */
  73                          <0x49039000 0x49039000 0x001000>,      /* ap 19 */
  74                          <0x4903a000 0x4903a000 0x001000>,      /* ap 20 */
  75                          <0x4903b000 0x4903b000 0x001000>,      /* ap 21 */
  76                          <0x4903c000 0x4903c000 0x001000>,      /* ap 22 */
  77                          <0x4903d000 0x4903d000 0x001000>,      /* ap 23 */
  78                          <0x4903e000 0x4903e000 0x001000>,      /* ap 24 */
  79                          <0x4903f000 0x4903f000 0x001000>,      /* ap 25 */
  80                          <0x49080000 0x49080000 0x010000>,      /* ap 26 */
  81                          <0x49080000 0x49080000 0x001000>,      /* ap 27 */
  82                          <0x490a0000 0x490a0000 0x010000>,      /* ap 28 */
  83                          <0x490a0000 0x490a0000 0x001000>,      /* ap 29 */
  84                          <0x490c0000 0x490c0000 0x010000>,      /* ap 30 */
  85                          <0x490c0000 0x490c0000 0x001000>,      /* ap 31 */
  86                          <0x490f1000 0x490f1000 0x001000>,      /* ap 32 */
  87                          <0x490f2000 0x490f2000 0x001000>;      /* ap 33 */
  88
  89                 target-module@22000 {                   /* 0x40122000, ap 2 02.0 */
  90                         compatible = "ti,sysc-omap2", "ti,sysc";
  91                         reg = <0x2208c 0x4>;
  92                         reg-names = "sysc";
  93                         ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
  94                                          SYSC_OMAP2_ENAWAKEUP |
  95                                          SYSC_OMAP2_SOFTRESET)>;
  96                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
  97                                         <SYSC_IDLE_NO>,
  98                                         <SYSC_IDLE_SMART>;
  99                         /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */
 100                         clocks = <&abe_clkctrl OMAP4_MCBSP1_CLKCTRL 0>;
 101                         clock-names = "fck";
 102                         #address-cells = <1>;
 103                         #size-cells = <1>;
 104                         ranges = <0x0 0x22000 0x1000>,
 105                                  <0x49022000 0x49022000 0x1000>;
 106
 107                         mcbsp1: mcbsp@0 {
 108                                 compatible = "ti,omap4-mcbsp";
 109                                 reg = <0x0 0xff>, /* MPU private access */
 110                                       <0x49022000 0xff>; /* L3 Interconnect */
 111                                 reg-names = "mpu", "dma";
 112                                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 113                                 interrupt-names = "common";
 114                                 ti,buffer-size = <128>;
 115                                 dmas = <&sdma 33>,
 116                                        <&sdma 34>;
 117                                 dma-names = "tx", "rx";
 118                                 status = "disabled";
 119                         };
 120                 };
 121
 122                 target-module@24000 {                   /* 0x40124000, ap 4 04.0 */
 123                         compatible = "ti,sysc-omap2", "ti,sysc";
 124                         reg = <0x2408c 0x4>;
 125                         reg-names = "sysc";
 126                         ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
 127                                          SYSC_OMAP2_ENAWAKEUP |
 128                                          SYSC_OMAP2_SOFTRESET)>;
 129                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 130                                         <SYSC_IDLE_NO>,
 131                                         <SYSC_IDLE_SMART>;
 132                         /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */
 133                         clocks = <&abe_clkctrl OMAP4_MCBSP2_CLKCTRL 0>;
 134                         clock-names = "fck";
 135                         #address-cells = <1>;
 136                         #size-cells = <1>;
 137                         ranges = <0x0 0x24000 0x1000>,
 138                                  <0x49024000 0x49024000 0x1000>;
 139
 140                         mcbsp2: mcbsp@0 {
 141                                 compatible = "ti,omap4-mcbsp";
 142                                 reg = <0x0 0xff>, /* MPU private access */
 143                                       <0x49024000 0xff>; /* L3 Interconnect */
 144                                 reg-names = "mpu", "dma";
 145                                 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
 146                                 interrupt-names = "common";
 147                                 ti,buffer-size = <128>;
 148                                 dmas = <&sdma 17>,
 149                                        <&sdma 18>;
 150                                 dma-names = "tx", "rx";
 151                                 status = "disabled";
 152                         };
 153                 };
 154
 155                 target-module@26000 {                   /* 0x40126000, ap 6 06.0 */
 156                         compatible = "ti,sysc-omap2", "ti,sysc";
 157                         reg = <0x2608c 0x4>;
 158                         reg-names = "sysc";
 159                         ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
 160                                          SYSC_OMAP2_ENAWAKEUP |
 161                                          SYSC_OMAP2_SOFTRESET)>;
 162                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 163                                         <SYSC_IDLE_NO>,
 164                                         <SYSC_IDLE_SMART>;
 165                         /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */
 166                         clocks = <&abe_clkctrl OMAP4_MCBSP3_CLKCTRL 0>;
 167                         clock-names = "fck";
 168                         #address-cells = <1>;
 169                         #size-cells = <1>;
 170                         ranges = <0x0 0x26000 0x1000>,
 171                                  <0x49026000 0x49026000 0x1000>;
 172
 173                         mcbsp3: mcbsp@0 {
 174                                 compatible = "ti,omap4-mcbsp";
 175                                 reg = <0x0 0xff>, /* MPU private access */
 176                                       <0x49026000 0xff>; /* L3 Interconnect */
 177                                 reg-names = "mpu", "dma";
 178                                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 179                                 interrupt-names = "common";
 180                                 ti,buffer-size = <128>;
 181                                 dmas = <&sdma 19>,
 182                                        <&sdma 20>;
 183                                 dma-names = "tx", "rx";
 184                                 status = "disabled";
 185                         };
 186                 };
 187
 188                 target-module@28000 {                   /* 0x40128000, ap 8 08.0 */
 189                         compatible = "ti,sysc-mcasp", "ti,sysc";
 190                         reg = <0x28000 0x4>,
 191                               <0x28004 0x4>;
 192                         reg-names = "rev", "sysc";
 193                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 194                                         <SYSC_IDLE_NO>,
 195                                         <SYSC_IDLE_SMART>,
 196                                         <SYSC_IDLE_SMART_WKUP>;
 197                         /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */
 198                         clocks = <&abe_clkctrl OMAP4_MCASP_CLKCTRL 0>;
 199                         clock-names = "fck";
 200                         #address-cells = <1>;
 201                         #size-cells = <1>;
 202                         ranges = <0x0 0x28000 0x1000>,
 203                                  <0x49028000 0x49028000 0x1000>;
 204
 205                         /*
 206                          * Child device unsupported by davinci-mcasp. At least
 207                          * RX path is disabled for omap4, and only DIT mode
 208                          * works with no I2S. See also old Android kernel
 209                          * omap-mcasp driver for more information.
 210                          */
 211                 };
 212
 213                 target-module@2a000 {                   /* 0x4012a000, ap 10 0a.0 */
 214                         compatible = "ti,sysc";
 215                         status = "disabled";
 216                         #address-cells = <1>;
 217                         #size-cells = <1>;
 218                         ranges = <0x0 0x2a000 0x1000>,
 219                                  <0x4902a000 0x4902a000 0x1000>;
 220                 };
 221
 222                 target-module@2e000 {                   /* 0x4012e000, ap 12 0c.0 */
 223                         compatible = "ti,sysc-omap4", "ti,sysc";
 224                         reg = <0x2e000 0x4>,
 225                               <0x2e010 0x4>;
 226                         reg-names = "rev", "sysc";
 227                         ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
 228                                          SYSC_OMAP4_SOFTRESET)>;
 229                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 230                                         <SYSC_IDLE_NO>,
 231                                         <SYSC_IDLE_SMART>,
 232                                         <SYSC_IDLE_SMART_WKUP>;
 233                         /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */
 234                         clocks = <&abe_clkctrl OMAP4_DMIC_CLKCTRL 0>;
 235                         clock-names = "fck";
 236                         #address-cells = <1>;
 237                         #size-cells = <1>;
 238                         ranges = <0x0 0x2e000 0x1000>,
 239                                  <0x4902e000 0x4902e000 0x1000>;
 240
 241                         dmic: dmic@0 {
 242                                 compatible = "ti,omap4-dmic";
 243                                 reg = <0x0 0x7f>, /* MPU private access */
 244                                       <0x4902e000 0x7f>; /* L3 Interconnect */
 245                                 reg-names = "mpu", "dma";
 246                                 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
 247                                 dmas = <&sdma 67>;
 248                                 dma-names = "up_link";
 249                                 status = "disabled";
 250                         };
 251                 };
 252
 253                 target-module@30000 {                   /* 0x40130000, ap 14 0e.0 */
 254                         compatible = "ti,sysc-omap2", "ti,sysc";
 255                         reg = <0x30000 0x4>,
 256                               <0x30010 0x4>,
 257                               <0x30014 0x4>;
 258                         reg-names = "rev", "sysc", "syss";
 259                         ti,sysc-mask = <(SYSC_OMAP2_EMUFREE |
 260                                          SYSC_OMAP2_SOFTRESET)>;
 261                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 262                                         <SYSC_IDLE_NO>,
 263                                         <SYSC_IDLE_SMART>,
 264                                         <SYSC_IDLE_SMART_WKUP>;
 265                         ti,syss-mask = <1>;
 266                         /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */
 267                         clocks = <&abe_clkctrl OMAP4_WD_TIMER3_CLKCTRL 0>;
 268                         clock-names = "fck";
 269                         #address-cells = <1>;
 270                         #size-cells = <1>;
 271                         ranges = <0x0 0x30000 0x1000>,
 272                                  <0x49030000 0x49030000 0x1000>;
 273
 274                         wdt3: wdt@0 {
 275                                 compatible = "ti,omap4-wdt", "ti,omap3-wdt";
 276                                 reg = <0x0 0x80>;
 277                                 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
 278                         };
 279                 };
 280
 281                 mcpdm_module: target-module@32000 {     /* 0x40132000, ap 16 10.0 */
 282                         compatible = "ti,sysc-omap4", "ti,sysc";
 283                         reg = <0x32000 0x4>,
 284                               <0x32010 0x4>;
 285                         reg-names = "rev", "sysc";
 286                         ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
 287                                          SYSC_OMAP4_SOFTRESET)>;
 288                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 289                                         <SYSC_IDLE_NO>,
 290                                         <SYSC_IDLE_SMART>,
 291                                         <SYSC_IDLE_SMART_WKUP>;
 292                         /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */
 293                         clocks = <&abe_clkctrl OMAP4_MCPDM_CLKCTRL 0>;
 294                         clock-names = "fck";
 295                         #address-cells = <1>;
 296                         #size-cells = <1>;
 297                         ranges = <0x0 0x32000 0x1000>,
 298                                  <0x49032000 0x49032000 0x1000>;
 299
 300                         /* Must be only enabled for boards with pdmclk wired */
 301                         status = "disabled";
 302
 303                         mcpdm: mcpdm@0 {
 304                                 compatible = "ti,omap4-mcpdm";
 305                                 reg = <0x0 0x7f>, /* MPU private access */
 306                                       <0x49032000 0x7f>; /* L3 Interconnect */
 307                                 reg-names = "mpu", "dma";
 308                                 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
 309                                 dmas = <&sdma 65>,
 310                                        <&sdma 66>;
 311                                 dma-names = "up_link", "dn_link";
 312                         };
 313                 };
 314
 315                 target-module@38000 {                   /* 0x40138000, ap 18 12.0 */
 316                         compatible = "ti,sysc-omap4-timer", "ti,sysc";
 317                         reg = <0x38000 0x4>,
 318                               <0x38010 0x4>;
 319                         reg-names = "rev", "sysc";
 320                         ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
 321                                          SYSC_OMAP4_SOFTRESET)>;
 322                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 323                                         <SYSC_IDLE_NO>,
 324                                         <SYSC_IDLE_SMART>,
 325                                         <SYSC_IDLE_SMART_WKUP>;
 326                         /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */
 327                         clocks = <&abe_clkctrl OMAP4_TIMER5_CLKCTRL 0>;
 328                         clock-names = "fck";
 329                         #address-cells = <1>;
 330                         #size-cells = <1>;
 331                         ranges = <0x0 0x38000 0x1000>,
 332                                  <0x49038000 0x49038000 0x1000>;
 333
 334                         timer5: timer@0 {
 335                                 compatible = "ti,omap4430-timer";
 336                                 reg = <0x00000000 0x80>,
 337                                       <0x49038000 0x80>;
 338                                 clocks = <&abe_clkctrl OMAP4_TIMER5_CLKCTRL 24>,
 339                                          <&syc_clk_div_ck>;
 340                                 clock-names = "fck", "timer_sys_ck";
 341                                 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 342                                 ti,timer-dsp;
 343                         };
 344                 };
 345
 346                 target-module@3a000 {                   /* 0x4013a000, ap 20 14.0 */
 347                         compatible = "ti,sysc-omap4-timer", "ti,sysc";
 348                         reg = <0x3a000 0x4>,
 349                               <0x3a010 0x4>;
 350                         reg-names = "rev", "sysc";
 351                         ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
 352                                          SYSC_OMAP4_SOFTRESET)>;
 353                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 354                                         <SYSC_IDLE_NO>,
 355                                         <SYSC_IDLE_SMART>,
 356                                         <SYSC_IDLE_SMART_WKUP>;
 357                         /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */
 358                         clocks = <&abe_clkctrl OMAP4_TIMER6_CLKCTRL 0>;
 359                         clock-names = "fck";
 360                         #address-cells = <1>;
 361                         #size-cells = <1>;
 362                         ranges = <0x0 0x3a000 0x1000>,
 363                                  <0x4903a000 0x4903a000 0x1000>;
 364
 365                         timer6: timer@0 {
 366                                 compatible = "ti,omap4430-timer";
 367                                 reg = <0x00000000 0x80>,
 368                                       <0x4903a000 0x80>;
 369                                 clocks = <&abe_clkctrl OMAP4_TIMER6_CLKCTRL 24>,
 370                                          <&syc_clk_div_ck>;
 371                                 clock-names = "fck", "timer_sys_ck";
 372                                 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
 373                                 ti,timer-dsp;
 374                         };
 375                 };
 376
 377                 target-module@3c000 {                   /* 0x4013c000, ap 22 16.0 */
 378                         compatible = "ti,sysc-omap4-timer", "ti,sysc";
 379                         reg = <0x3c000 0x4>,
 380                               <0x3c010 0x4>;
 381                         reg-names = "rev", "sysc";
 382                         ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
 383                                          SYSC_OMAP4_SOFTRESET)>;
 384                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 385                                         <SYSC_IDLE_NO>,
 386                                         <SYSC_IDLE_SMART>,
 387                                         <SYSC_IDLE_SMART_WKUP>;
 388                         /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */
 389                         clocks = <&abe_clkctrl OMAP4_TIMER7_CLKCTRL 0>;
 390                         clock-names = "fck";
 391                         #address-cells = <1>;
 392                         #size-cells = <1>;
 393                         ranges = <0x0 0x3c000 0x1000>,
 394                                  <0x4903c000 0x4903c000 0x1000>;
 395
 396                         timer7: timer@0 {
 397                                 compatible = "ti,omap4430-timer";
 398                                 reg = <0x00000000 0x80>,
 399                                       <0x4903c000 0x80>;
 400                                 clocks = <&abe_clkctrl OMAP4_TIMER7_CLKCTRL 24>,
 401                                          <&syc_clk_div_ck>;
 402                                 clock-names = "fck", "timer_sys_ck";
 403                                 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
 404                                 ti,timer-dsp;
 405                         };
 406                 };
 407
 408                 target-module@3e000 {                   /* 0x4013e000, ap 24 18.0 */
 409                         compatible = "ti,sysc-omap4-timer", "ti,sysc";
 410                         reg = <0x3e000 0x4>,
 411                               <0x3e010 0x4>;
 412                         reg-names = "rev", "sysc";
 413                         ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
 414                                          SYSC_OMAP4_SOFTRESET)>;
 415                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 416                                         <SYSC_IDLE_NO>,
 417                                         <SYSC_IDLE_SMART>,
 418                                         <SYSC_IDLE_SMART_WKUP>;
 419                         /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */
 420                         clocks = <&abe_clkctrl OMAP4_TIMER8_CLKCTRL 0>;
 421                         clock-names = "fck";
 422                         #address-cells = <1>;
 423                         #size-cells = <1>;
 424                         ranges = <0x0 0x3e000 0x1000>,
 425                                  <0x4903e000 0x4903e000 0x1000>;
 426
 427                         timer8: timer@0 {
 428                                 compatible = "ti,omap4430-timer";
 429                                 reg = <0x00000000 0x80>,
 430                                       <0x4903e000 0x80>;
 431                                 clocks = <&abe_clkctrl OMAP4_TIMER8_CLKCTRL 24>,
 432                                          <&syc_clk_div_ck>;
 433                                 clock-names = "fck", "timer_sys_ck";
 434                                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 435                                 ti,timer-pwm;
 436                                 ti,timer-dsp;
 437                         };
 438                 };
 439
 440                 target-module@80000 {                   /* 0x40180000, ap 26 1a.0 */
 441                         compatible = "ti,sysc";
 442                         status = "disabled";
 443                         #address-cells = <1>;
 444                         #size-cells = <1>;
 445                         ranges = <0x0 0x80000 0x10000>,
 446                                  <0x49080000 0x49080000 0x10000>;
 447                 };
 448
 449                 target-module@a0000 {                   /* 0x401a0000, ap 28 1c.0 */
 450                         compatible = "ti,sysc";
 451                         status = "disabled";
 452                         #address-cells = <1>;
 453                         #size-cells = <1>;
 454                         ranges = <0x0 0xa0000 0x10000>,
 455                                  <0x490a0000 0x490a0000 0x10000>;
 456                 };
 457
 458                 target-module@c0000 {                   /* 0x401c0000, ap 30 1e.0 */
 459                         compatible = "ti,sysc";
 460                         status = "disabled";
 461                         #address-cells = <1>;
 462                         #size-cells = <1>;
 463                         ranges = <0x0 0xc0000 0x10000>,
 464                                  <0x490c0000 0x490c0000 0x10000>;
 465                 };
 466
 467                 target-module@f1000 {                   /* 0x401f1000, ap 32 20.0 */
 468                         compatible = "ti,sysc-omap4", "ti,sysc";
 469                         reg = <0xf1000 0x4>,
 470                               <0xf1010 0x4>;
 471                         reg-names = "rev", "sysc";
 472                         ti,sysc-midle = <SYSC_IDLE_FORCE>,
 473                                         <SYSC_IDLE_NO>,
 474                                         <SYSC_IDLE_SMART>,
 475                                         <SYSC_IDLE_SMART_WKUP>;
 476                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 477                                         <SYSC_IDLE_NO>,
 478                                         <SYSC_IDLE_SMART>;
 479                         /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */
 480                         clocks = <&abe_clkctrl OMAP4_AESS_CLKCTRL 0>;
 481                         clock-names = "fck";
 482                         #address-cells = <1>;
 483                         #size-cells = <1>;
 484                         ranges = <0x0 0xf1000 0x1000>,
 485                                  <0x490f1000 0x490f1000 0x1000>;
 486
 487                         /*
 488                          * No child device binding or driver in mainline.
 489                          * See Android tree and related upstreaming efforts
 490                          * for the old driver.
 491                          */
 492                 };
 493         };
 494 };
 495