arch/arm/boot/dts/omap3xxx-clocks.dtsi

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Device Tree Source for OMAP3 clock data
   4  *
   5  * Copyright (C) 2013 Texas Instruments, Inc.
   6  */
   7 &prm_clocks {
   8         virt_16_8m_ck: virt_16_8m_ck {
   9                 #clock-cells = <0>;
  10                 compatible = "fixed-clock";
  11                 clock-frequency = <16800000>;
  12         };
  13
  14         osc_sys_ck: osc_sys_ck@d40 {
  15                 #clock-cells = <0>;
  16                 compatible = "ti,mux-clock";
  17                 clocks = <&virt_12m_ck>, <&virt_13m_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_38_4m_ck>, <&virt_16_8m_ck>;
  18                 reg = <0x0d40>;
  19         };
  20
  21         sys_ck: sys_ck@1270 {
  22                 #clock-cells = <0>;
  23                 compatible = "ti,divider-clock";
  24                 clocks = <&osc_sys_ck>;
  25                 ti,bit-shift = <6>;
  26                 ti,max-div = <3>;
  27                 reg = <0x1270>;
  28                 ti,index-starts-at-one;
  29         };
  30
  31         sys_clkout1: sys_clkout1@d70 {
  32                 #clock-cells = <0>;
  33                 compatible = "ti,gate-clock";
  34                 clocks = <&osc_sys_ck>;
  35                 reg = <0x0d70>;
  36                 ti,bit-shift = <7>;
  37         };
  38
  39         dpll3_x2_ck: dpll3_x2_ck {
  40                 #clock-cells = <0>;
  41                 compatible = "fixed-factor-clock";
  42                 clocks = <&dpll3_ck>;
  43                 clock-mult = <2>;
  44                 clock-div = <1>;
  45         };
  46
  47         dpll3_m2x2_ck: dpll3_m2x2_ck {
  48                 #clock-cells = <0>;
  49                 compatible = "fixed-factor-clock";
  50                 clocks = <&dpll3_m2_ck>;
  51                 clock-mult = <2>;
  52                 clock-div = <1>;
  53         };
  54
  55         dpll4_x2_ck: dpll4_x2_ck {
  56                 #clock-cells = <0>;
  57                 compatible = "fixed-factor-clock";
  58                 clocks = <&dpll4_ck>;
  59                 clock-mult = <2>;
  60                 clock-div = <1>;
  61         };
  62
  63         corex2_fck: corex2_fck {
  64                 #clock-cells = <0>;
  65                 compatible = "fixed-factor-clock";
  66                 clocks = <&dpll3_m2x2_ck>;
  67                 clock-mult = <1>;
  68                 clock-div = <1>;
  69         };
  70
  71         wkup_l4_ick: wkup_l4_ick {
  72                 #clock-cells = <0>;
  73                 compatible = "fixed-factor-clock";
  74                 clocks = <&sys_ck>;
  75                 clock-mult = <1>;
  76                 clock-div = <1>;
  77         };
  78 };
  79
  80 &scm_clocks {
  81         /* CONTROL_DEVCONF1 */
  82         clock@68 {
  83                 compatible = "ti,clksel";
  84                 reg = <0x68>;
  85                 #clock-cells = <2>;
  86                 #address-cells = <0>;
  87
  88                 mcbsp5_mux_fck: clock-mcbsp5-mux-fck {
  89                         #clock-cells = <0>;
  90                         compatible = "ti,composite-mux-clock";
  91                         clock-output-names = "mcbsp5_mux_fck";
  92                         clocks = <&core_96m_fck>, <&mcbsp_clks>;
  93                         ti,bit-shift = <4>;
  94                 };
  95
  96                 mcbsp3_mux_fck: clock-mcbsp3-mux-fck {
  97                         #clock-cells = <0>;
  98                         compatible = "ti,composite-mux-clock";
  99                         clock-output-names = "mcbsp3_mux_fck";
 100                         clocks = <&per_96m_fck>, <&mcbsp_clks>;
 101                 };
 102
 103                 mcbsp4_mux_fck: clock-mcbsp4-mux-fck {
 104                         #clock-cells = <0>;
 105                         compatible = "ti,composite-mux-clock";
 106                         clock-output-names = "mcbsp4_mux_fck";
 107                         clocks = <&per_96m_fck>, <&mcbsp_clks>;
 108                         ti,bit-shift = <2>;
 109                 };
 110         };
 111
 112         mcbsp5_fck: mcbsp5_fck {
 113                 #clock-cells = <0>;
 114                 compatible = "ti,composite-clock";
 115                 clocks = <&mcbsp5_gate_fck>, <&mcbsp5_mux_fck>;
 116         };
 117
 118         /* CONTROL_DEVCONF0 */
 119         clock@4 {
 120                 compatible = "ti,clksel";
 121                 reg = <0x4>;
 122                 #clock-cells = <2>;
 123                 #address-cells = <0>;
 124
 125                 mcbsp1_mux_fck: clock-mcbsp1-mux-fck {
 126                         #clock-cells = <0>;
 127                         compatible = "ti,composite-mux-clock";
 128                         clock-output-names = "mcbsp1_mux_fck";
 129                         clocks = <&core_96m_fck>, <&mcbsp_clks>;
 130                         ti,bit-shift = <2>;
 131                 };
 132
 133                 mcbsp2_mux_fck: clock-mcbsp2-mux-fck {
 134                         #clock-cells = <0>;
 135                         compatible = "ti,composite-mux-clock";
 136                         clock-output-names = "mcbsp2_mux_fck";
 137                         clocks = <&per_96m_fck>, <&mcbsp_clks>;
 138                         ti,bit-shift = <6>;
 139                 };
 140         };
 141
 142         mcbsp1_fck: mcbsp1_fck {
 143                 #clock-cells = <0>;
 144                 compatible = "ti,composite-clock";
 145                 clocks = <&mcbsp1_gate_fck>, <&mcbsp1_mux_fck>;
 146         };
 147
 148         mcbsp2_fck: mcbsp2_fck {
 149                 #clock-cells = <0>;
 150                 compatible = "ti,composite-clock";
 151                 clocks = <&mcbsp2_gate_fck>, <&mcbsp2_mux_fck>;
 152         };
 153
 154         mcbsp3_fck: mcbsp3_fck {
 155                 #clock-cells = <0>;
 156                 compatible = "ti,composite-clock";
 157                 clocks = <&mcbsp3_gate_fck>, <&mcbsp3_mux_fck>;
 158         };
 159
 160         mcbsp4_fck: mcbsp4_fck {
 161                 #clock-cells = <0>;
 162                 compatible = "ti,composite-clock";
 163                 clocks = <&mcbsp4_gate_fck>, <&mcbsp4_mux_fck>;
 164         };
 165 };
 166 &cm_clocks {
 167         dummy_apb_pclk: dummy_apb_pclk {
 168                 #clock-cells = <0>;
 169                 compatible = "fixed-clock";
 170                 clock-frequency = <0x0>;
 171         };
 172
 173         omap_32k_fck: omap_32k_fck {
 174                 #clock-cells = <0>;
 175                 compatible = "fixed-clock";
 176                 clock-frequency = <32768>;
 177         };
 178
 179         virt_12m_ck: virt_12m_ck {
 180                 #clock-cells = <0>;
 181                 compatible = "fixed-clock";
 182                 clock-frequency = <12000000>;
 183         };
 184
 185         virt_13m_ck: virt_13m_ck {
 186                 #clock-cells = <0>;
 187                 compatible = "fixed-clock";
 188                 clock-frequency = <13000000>;
 189         };
 190
 191         virt_19200000_ck: virt_19200000_ck {
 192                 #clock-cells = <0>;
 193                 compatible = "fixed-clock";
 194                 clock-frequency = <19200000>;
 195         };
 196
 197         virt_26000000_ck: virt_26000000_ck {
 198                 #clock-cells = <0>;
 199                 compatible = "fixed-clock";
 200                 clock-frequency = <26000000>;
 201         };
 202
 203         virt_38_4m_ck: virt_38_4m_ck {
 204                 #clock-cells = <0>;
 205                 compatible = "fixed-clock";
 206                 clock-frequency = <38400000>;
 207         };
 208
 209         dpll4_ck: dpll4_ck@d00 {
 210                 #clock-cells = <0>;
 211                 compatible = "ti,omap3-dpll-per-clock";
 212                 clocks = <&sys_ck>, <&sys_ck>;
 213                 reg = <0x0d00>, <0x0d20>, <0x0d44>, <0x0d30>;
 214         };
 215
 216         dpll4_m2_ck: dpll4_m2_ck@d48 {
 217                 #clock-cells = <0>;
 218                 compatible = "ti,divider-clock";
 219                 clocks = <&dpll4_ck>;
 220                 ti,max-div = <63>;
 221                 reg = <0x0d48>;
 222                 ti,index-starts-at-one;
 223         };
 224
 225         dpll4_m2x2_mul_ck: dpll4_m2x2_mul_ck {
 226                 #clock-cells = <0>;
 227                 compatible = "fixed-factor-clock";
 228                 clocks = <&dpll4_m2_ck>;
 229                 clock-mult = <2>;
 230                 clock-div = <1>;
 231         };
 232
 233         dpll4_m2x2_ck: dpll4_m2x2_ck@d00 {
 234                 #clock-cells = <0>;
 235                 compatible = "ti,gate-clock";
 236                 clocks = <&dpll4_m2x2_mul_ck>;
 237                 ti,bit-shift = <0x1b>;
 238                 reg = <0x0d00>;
 239                 ti,set-bit-to-disable;
 240         };
 241
 242         omap_96m_alwon_fck: omap_96m_alwon_fck {
 243                 #clock-cells = <0>;
 244                 compatible = "fixed-factor-clock";
 245                 clocks = <&dpll4_m2x2_ck>;
 246                 clock-mult = <1>;
 247                 clock-div = <1>;
 248         };
 249
 250         dpll3_ck: dpll3_ck@d00 {
 251                 #clock-cells = <0>;
 252                 compatible = "ti,omap3-dpll-core-clock";
 253                 clocks = <&sys_ck>, <&sys_ck>;
 254                 reg = <0x0d00>, <0x0d20>, <0x0d40>, <0x0d30>;
 255         };
 256
 257         dpll3_m3_ck: dpll3_m3_ck@1140 {
 258                 #clock-cells = <0>;
 259                 compatible = "ti,divider-clock";
 260                 clocks = <&dpll3_ck>;
 261                 ti,bit-shift = <16>;
 262                 ti,max-div = <31>;
 263                 reg = <0x1140>;
 264                 ti,index-starts-at-one;
 265         };
 266
 267         dpll3_m3x2_mul_ck: dpll3_m3x2_mul_ck {
 268                 #clock-cells = <0>;
 269                 compatible = "fixed-factor-clock";
 270                 clocks = <&dpll3_m3_ck>;
 271                 clock-mult = <2>;
 272                 clock-div = <1>;
 273         };
 274
 275         dpll3_m3x2_ck: dpll3_m3x2_ck@d00 {
 276                 #clock-cells = <0>;
 277                 compatible = "ti,gate-clock";
 278                 clocks = <&dpll3_m3x2_mul_ck>;
 279                 ti,bit-shift = <0xc>;
 280                 reg = <0x0d00>;
 281                 ti,set-bit-to-disable;
 282         };
 283
 284         emu_core_alwon_ck: emu_core_alwon_ck {
 285                 #clock-cells = <0>;
 286                 compatible = "fixed-factor-clock";
 287                 clocks = <&dpll3_m3x2_ck>;
 288                 clock-mult = <1>;
 289                 clock-div = <1>;
 290         };
 291
 292         sys_altclk: sys_altclk {
 293                 #clock-cells = <0>;
 294                 compatible = "fixed-clock";
 295                 clock-frequency = <0x0>;
 296         };
 297
 298         mcbsp_clks: mcbsp_clks {
 299                 #clock-cells = <0>;
 300                 compatible = "fixed-clock";
 301                 clock-frequency = <0x0>;
 302         };
 303
 304         core_ck: core_ck {
 305                 #clock-cells = <0>;
 306                 compatible = "fixed-factor-clock";
 307                 clocks = <&dpll3_m2_ck>;
 308                 clock-mult = <1>;
 309                 clock-div = <1>;
 310         };
 311
 312         dpll1_fck: dpll1_fck@940 {
 313                 #clock-cells = <0>;
 314                 compatible = "ti,divider-clock";
 315                 clocks = <&core_ck>;
 316                 ti,bit-shift = <19>;
 317                 ti,max-div = <7>;
 318                 reg = <0x0940>;
 319                 ti,index-starts-at-one;
 320         };
 321
 322         dpll1_ck: dpll1_ck@904 {
 323                 #clock-cells = <0>;
 324                 compatible = "ti,omap3-dpll-clock";
 325                 clocks = <&sys_ck>, <&dpll1_fck>;
 326                 reg = <0x0904>, <0x0924>, <0x0940>, <0x0934>;
 327         };
 328
 329         dpll1_x2_ck: dpll1_x2_ck {
 330                 #clock-cells = <0>;
 331                 compatible = "fixed-factor-clock";
 332                 clocks = <&dpll1_ck>;
 333                 clock-mult = <2>;
 334                 clock-div = <1>;
 335         };
 336
 337         dpll1_x2m2_ck: dpll1_x2m2_ck@944 {
 338                 #clock-cells = <0>;
 339                 compatible = "ti,divider-clock";
 340                 clocks = <&dpll1_x2_ck>;
 341                 ti,max-div = <31>;
 342                 reg = <0x0944>;
 343                 ti,index-starts-at-one;
 344         };
 345
 346         cm_96m_fck: cm_96m_fck {
 347                 #clock-cells = <0>;
 348                 compatible = "fixed-factor-clock";
 349                 clocks = <&omap_96m_alwon_fck>;
 350                 clock-mult = <1>;
 351                 clock-div = <1>;
 352         };
 353
 354         /* CM_CLKSEL1_PLL */
 355         clock@d40 {
 356                 compatible = "ti,clksel";
 357                 reg = <0xd40>;
 358                 #clock-cells = <2>;
 359                 #address-cells = <0>;
 360
 361                 dpll3_m2_ck: clock-dpll3-m2 {
 362                         #clock-cells = <0>;
 363                         compatible = "ti,divider-clock";
 364                         clock-output-names = "dpll3_m2_ck";
 365                         clocks = <&dpll3_ck>;
 366                         ti,bit-shift = <27>;
 367                         ti,max-div = <31>;
 368                         ti,index-starts-at-one;
 369                 };
 370
 371                 omap_96m_fck: clock-omap-96m-fck {
 372                         #clock-cells = <0>;
 373                         compatible = "ti,mux-clock";
 374                         clock-output-names = "omap_96m_fck";
 375                         clocks = <&cm_96m_fck>, <&sys_ck>;
 376                         ti,bit-shift = <6>;
 377                 };
 378
 379                 omap_54m_fck: clock-omap-54m-fck {
 380                         #clock-cells = <0>;
 381                         compatible = "ti,mux-clock";
 382                         clock-output-names = "omap_54m_fck";
 383                         clocks = <&dpll4_m3x2_ck>, <&sys_altclk>;
 384                         ti,bit-shift = <5>;
 385                 };
 386
 387                 omap_48m_fck: clock-omap-48m-fck {
 388                         #clock-cells = <0>;
 389                         compatible = "ti,mux-clock";
 390                         clock-output-names = "omap_48m_fck";
 391                         clocks = <&cm_96m_d2_fck>, <&sys_altclk>;
 392                         ti,bit-shift = <3>;
 393                 };
 394         };
 395
 396         /* CM_CLKSEL_DSS */
 397         clock@e40 {
 398                 compatible = "ti,clksel";
 399                 reg = <0xe40>;
 400                 #clock-cells = <2>;
 401                 #address-cells = <0>;
 402
 403                 dpll4_m3_ck: clock-dpll4-m3 {
 404                         #clock-cells = <0>;
 405                         compatible = "ti,divider-clock";
 406                         clock-output-names = "dpll4_m3_ck";
 407                         clocks = <&dpll4_ck>;
 408                         ti,bit-shift = <8>;
 409                         ti,max-div = <32>;
 410                         ti,index-starts-at-one;
 411                 };
 412
 413                 dpll4_m4_ck: clock-dpll4-m4 {
 414                         #clock-cells = <0>;
 415                         compatible = "ti,divider-clock";
 416                         clock-output-names = "dpll4_m4_ck";
 417                         clocks = <&dpll4_ck>;
 418                         ti,max-div = <16>;
 419                         ti,index-starts-at-one;
 420                 };
 421         };
 422
 423         dpll4_m3x2_mul_ck: dpll4_m3x2_mul_ck {
 424                 #clock-cells = <0>;
 425                 compatible = "fixed-factor-clock";
 426                 clocks = <&dpll4_m3_ck>;
 427                 clock-mult = <2>;
 428                 clock-div = <1>;
 429         };
 430
 431         dpll4_m3x2_ck: dpll4_m3x2_ck@d00 {
 432                 #clock-cells = <0>;
 433                 compatible = "ti,gate-clock";
 434                 clocks = <&dpll4_m3x2_mul_ck>;
 435                 ti,bit-shift = <0x1c>;
 436                 reg = <0x0d00>;
 437                 ti,set-bit-to-disable;
 438         };
 439
 440         cm_96m_d2_fck: cm_96m_d2_fck {
 441                 #clock-cells = <0>;
 442                 compatible = "fixed-factor-clock";
 443                 clocks = <&cm_96m_fck>;
 444                 clock-mult = <1>;
 445                 clock-div = <2>;
 446         };
 447
 448         omap_12m_fck: omap_12m_fck {
 449                 #clock-cells = <0>;
 450                 compatible = "fixed-factor-clock";
 451                 clocks = <&omap_48m_fck>;
 452                 clock-mult = <1>;
 453                 clock-div = <4>;
 454         };
 455
 456         dpll4_m4x2_mul_ck: dpll4_m4x2_mul_ck {
 457                 #clock-cells = <0>;
 458                 compatible = "ti,fixed-factor-clock";
 459                 clocks = <&dpll4_m4_ck>;
 460                 ti,clock-mult = <2>;
 461                 ti,clock-div = <1>;
 462                 ti,set-rate-parent;
 463         };
 464
 465         dpll4_m4x2_ck: dpll4_m4x2_ck@d00 {
 466                 #clock-cells = <0>;
 467                 compatible = "ti,gate-clock";
 468                 clocks = <&dpll4_m4x2_mul_ck>;
 469                 ti,bit-shift = <0x1d>;
 470                 reg = <0x0d00>;
 471                 ti,set-bit-to-disable;
 472                 ti,set-rate-parent;
 473         };
 474
 475         dpll4_m5_ck: dpll4_m5_ck@f40 {
 476                 #clock-cells = <0>;
 477                 compatible = "ti,divider-clock";
 478                 clocks = <&dpll4_ck>;
 479                 ti,max-div = <63>;
 480                 reg = <0x0f40>;
 481                 ti,index-starts-at-one;
 482         };
 483
 484         dpll4_m5x2_mul_ck: dpll4_m5x2_mul_ck {
 485                 #clock-cells = <0>;
 486                 compatible = "ti,fixed-factor-clock";
 487                 clocks = <&dpll4_m5_ck>;
 488                 ti,clock-mult = <2>;
 489                 ti,clock-div = <1>;
 490                 ti,set-rate-parent;
 491         };
 492
 493         dpll4_m5x2_ck: dpll4_m5x2_ck@d00 {
 494                 #clock-cells = <0>;
 495                 compatible = "ti,gate-clock";
 496                 clocks = <&dpll4_m5x2_mul_ck>;
 497                 ti,bit-shift = <0x1e>;
 498                 reg = <0x0d00>;
 499                 ti,set-bit-to-disable;
 500                 ti,set-rate-parent;
 501         };
 502
 503         dpll4_m6_ck: dpll4_m6_ck@1140 {
 504                 #clock-cells = <0>;
 505                 compatible = "ti,divider-clock";
 506                 clocks = <&dpll4_ck>;
 507                 ti,bit-shift = <24>;
 508                 ti,max-div = <63>;
 509                 reg = <0x1140>;
 510                 ti,index-starts-at-one;
 511         };
 512
 513         dpll4_m6x2_mul_ck: dpll4_m6x2_mul_ck {
 514                 #clock-cells = <0>;
 515                 compatible = "fixed-factor-clock";
 516                 clocks = <&dpll4_m6_ck>;
 517                 clock-mult = <2>;
 518                 clock-div = <1>;
 519         };
 520
 521         dpll4_m6x2_ck: dpll4_m6x2_ck@d00 {
 522                 #clock-cells = <0>;
 523                 compatible = "ti,gate-clock";
 524                 clocks = <&dpll4_m6x2_mul_ck>;
 525                 ti,bit-shift = <0x1f>;
 526                 reg = <0x0d00>;
 527                 ti,set-bit-to-disable;
 528         };
 529
 530         emu_per_alwon_ck: emu_per_alwon_ck {
 531                 #clock-cells = <0>;
 532                 compatible = "fixed-factor-clock";
 533                 clocks = <&dpll4_m6x2_ck>;
 534                 clock-mult = <1>;
 535                 clock-div = <1>;
 536         };
 537
 538         /* CM_CLKOUT_CTRL */
 539         clock@d70 {
 540                 compatible = "ti,clksel";
 541                 reg = <0xd70>;
 542                 #clock-cells = <2>;
 543                 #address-cells = <0>;
 544
 545                 clkout2_src_gate_ck: clock-clkout2-src-gate {
 546                         #clock-cells = <0>;
 547                         compatible = "ti,composite-no-wait-gate-clock";
 548                         clock-output-names = "clkout2_src_gate_ck";
 549                         clocks = <&core_ck>;
 550                         ti,bit-shift = <7>;
 551                 };
 552
 553                 clkout2_src_mux_ck: clock-clkout2-src-mux {
 554                         #clock-cells = <0>;
 555                         compatible = "ti,composite-mux-clock";
 556                         clock-output-names = "clkout2_src_mux_ck";
 557                         clocks = <&core_ck>, <&sys_ck>, <&cm_96m_fck>, <&omap_54m_fck>;
 558                 };
 559
 560                 sys_clkout2: clock-sys-clkout2 {
 561                         #clock-cells = <0>;
 562                         compatible = "ti,divider-clock";
 563                         clock-output-names = "sys_clkout2";
 564                         clocks = <&clkout2_src_ck>;
 565                         ti,bit-shift = <3>;
 566                         ti,max-div = <64>;
 567                         ti,index-power-of-two;
 568                 };
 569         };
 570
 571         clkout2_src_ck: clkout2_src_ck {
 572                 #clock-cells = <0>;
 573                 compatible = "ti,composite-clock";
 574                 clocks = <&clkout2_src_gate_ck>, <&clkout2_src_mux_ck>;
 575         };
 576
 577         mpu_ck: mpu_ck {
 578                 #clock-cells = <0>;
 579                 compatible = "fixed-factor-clock";
 580                 clocks = <&dpll1_x2m2_ck>;
 581                 clock-mult = <1>;
 582                 clock-div = <1>;
 583         };
 584
 585         arm_fck: arm_fck@924 {
 586                 #clock-cells = <0>;
 587                 compatible = "ti,divider-clock";
 588                 clocks = <&mpu_ck>;
 589                 reg = <0x0924>;
 590                 ti,max-div = <2>;
 591         };
 592
 593         emu_mpu_alwon_ck: emu_mpu_alwon_ck {
 594                 #clock-cells = <0>;
 595                 compatible = "fixed-factor-clock";
 596                 clocks = <&mpu_ck>;
 597                 clock-mult = <1>;
 598                 clock-div = <1>;
 599         };
 600
 601         /* CM_CLKSEL_CORE */
 602         clock@a40 {
 603                 compatible = "ti,clksel";
 604                 reg = <0xa40>;
 605                 #clock-cells = <2>;
 606                 #address-cells = <0>;
 607
 608                 l3_ick: clock-l3-ick {
 609                         #clock-cells = <0>;
 610                         compatible = "ti,divider-clock";
 611                         clock-output-names = "l3_ick";
 612                         clocks = <&core_ck>;
 613                         ti,max-div = <3>;
 614                         ti,index-starts-at-one;
 615                 };
 616
 617                 l4_ick: clock-l4-ick {
 618                         #clock-cells = <0>;
 619                         compatible = "ti,divider-clock";
 620                         clock-output-names = "l4_ick";
 621                         clocks = <&l3_ick>;
 622                         ti,bit-shift = <2>;
 623                         ti,max-div = <3>;
 624                         ti,index-starts-at-one;
 625                 };
 626
 627                 gpt10_mux_fck: clock-gpt10-mux-fck {
 628                         #clock-cells = <0>;
 629                         compatible = "ti,composite-mux-clock";
 630                         clock-output-names = "gpt10_mux_fck";
 631                         clocks = <&omap_32k_fck>, <&sys_ck>;
 632                         ti,bit-shift = <6>;
 633                 };
 634
 635                 gpt11_mux_fck: clock-gpt11-mux-fck {
 636                         #clock-cells = <0>;
 637                         compatible = "ti,composite-mux-clock";
 638                         clock-output-names = "gpt11_mux_fck";
 639                         clocks = <&omap_32k_fck>, <&sys_ck>;
 640                         ti,bit-shift = <7>;
 641                 };
 642         };
 643
 644         /* CM_CLKSEL_WKUP */
 645         clock@c40 {
 646                 compatible = "ti,clksel";
 647                 reg = <0xc40>;
 648                 #clock-cells = <2>;
 649                 #address-cells = <0>;
 650
 651                 rm_ick: clock-rm-ick {
 652                         #clock-cells = <0>;
 653                         compatible = "ti,divider-clock";
 654                         clock-output-names = "rm_ick";
 655                         clocks = <&l4_ick>;
 656                         ti,bit-shift = <1>;
 657                         ti,max-div = <3>;
 658                         ti,index-starts-at-one;
 659                 };
 660
 661                 gpt1_mux_fck: clock-gpt1-mux-fck {
 662                         #clock-cells = <0>;
 663                         compatible = "ti,composite-mux-clock";
 664                         clock-output-names = "gpt1_mux_fck";
 665                         clocks = <&omap_32k_fck>, <&sys_ck>;
 666                 };
 667         };
 668
 669         /* CM_FCLKEN1_CORE */
 670         clock@a00 {
 671                 compatible = "ti,clksel";
 672                 reg = <0xa00>;
 673                 #clock-cells = <2>;
 674                 #address-cells = <0>;
 675
 676                 gpt10_gate_fck: clock-gpt10-gate-fck {
 677                         #clock-cells = <0>;
 678                         compatible = "ti,composite-gate-clock";
 679                         clock-output-names = "gpt10_gate_fck";
 680                         clocks = <&sys_ck>;
 681                         ti,bit-shift = <11>;
 682                 };
 683
 684                 gpt11_gate_fck: clock-gpt11-gate-fck {
 685                         #clock-cells = <0>;
 686                         compatible = "ti,composite-gate-clock";
 687                         clock-output-names = "gpt11_gate_fck";
 688                         clocks = <&sys_ck>;
 689                         ti,bit-shift = <12>;
 690                 };
 691
 692                 mmchs2_fck: clock-mmchs2-fck {
 693                         #clock-cells = <0>;
 694                         compatible = "ti,wait-gate-clock";
 695                         clock-output-names = "mmchs2_fck";
 696                         clocks = <&core_96m_fck>;
 697                         ti,bit-shift = <25>;
 698                 };
 699
 700                 mmchs1_fck: clock-mmchs1-fck {
 701                         #clock-cells = <0>;
 702                         compatible = "ti,wait-gate-clock";
 703                         clock-output-names = "mmchs1_fck";
 704                         clocks = <&core_96m_fck>;
 705                         ti,bit-shift = <24>;
 706                 };
 707
 708                 i2c3_fck: clock-i2c3-fck {
 709                         #clock-cells = <0>;
 710                         compatible = "ti,wait-gate-clock";
 711                         clock-output-names = "i2c3_fck";
 712                         clocks = <&core_96m_fck>;
 713                         ti,bit-shift = <17>;
 714                 };
 715
 716                 i2c2_fck: clock-i2c2-fck {
 717                         #clock-cells = <0>;
 718                         compatible = "ti,wait-gate-clock";
 719                         clock-output-names = "i2c2_fck";
 720                         clocks = <&core_96m_fck>;
 721                         ti,bit-shift = <16>;
 722                 };
 723
 724                 i2c1_fck: clock-i2c1-fck {
 725                         #clock-cells = <0>;
 726                         compatible = "ti,wait-gate-clock";
 727                         clock-output-names = "i2c1_fck";
 728                         clocks = <&core_96m_fck>;
 729                         ti,bit-shift = <15>;
 730                 };
 731
 732                 mcbsp5_gate_fck: clock-mcbsp5-gate-fck {
 733                         #clock-cells = <0>;
 734                         compatible = "ti,composite-gate-clock";
 735                         clock-output-names = "mcbsp5_gate_fck";
 736                         clocks = <&mcbsp_clks>;
 737                         ti,bit-shift = <10>;
 738                 };
 739
 740                 mcbsp1_gate_fck: clock-mcbsp1-gate-fck {
 741                         #clock-cells = <0>;
 742                         compatible = "ti,composite-gate-clock";
 743                         clock-output-names = "mcbsp1_gate_fck";
 744                         clocks = <&mcbsp_clks>;
 745                         ti,bit-shift = <9>;
 746                 };
 747
 748                 mcspi4_fck: clock-mcspi4-fck {
 749                         #clock-cells = <0>;
 750                         compatible = "ti,wait-gate-clock";
 751                         clock-output-names = "mcspi4_fck";
 752                         clocks = <&core_48m_fck>;
 753                         ti,bit-shift = <21>;
 754                 };
 755
 756                 mcspi3_fck: clock-mcspi3-fck {
 757                         #clock-cells = <0>;
 758                         compatible = "ti,wait-gate-clock";
 759                         clock-output-names = "mcspi3_fck";
 760                         clocks = <&core_48m_fck>;
 761                         ti,bit-shift = <20>;
 762                 };
 763
 764                 mcspi2_fck: clock-mcspi2-fck {
 765                         #clock-cells = <0>;
 766                         compatible = "ti,wait-gate-clock";
 767                         clock-output-names = "mcspi2_fck";
 768                         clocks = <&core_48m_fck>;
 769                         ti,bit-shift = <19>;
 770                 };
 771
 772                 mcspi1_fck: clock-mcspi1-fck {
 773                         #clock-cells = <0>;
 774                         compatible = "ti,wait-gate-clock";
 775                         clock-output-names = "mcspi1_fck";
 776                         clocks = <&core_48m_fck>;
 777                         ti,bit-shift = <18>;
 778                 };
 779
 780                 uart2_fck: clock-uart2-fck {
 781                         #clock-cells = <0>;
 782                         compatible = "ti,wait-gate-clock";
 783                         clock-output-names = "uart2_fck";
 784                         clocks = <&core_48m_fck>;
 785                         ti,bit-shift = <14>;
 786                 };
 787
 788                 uart1_fck: clock-uart1-fck {
 789                         #clock-cells = <0>;
 790                         compatible = "ti,wait-gate-clock";
 791                         clock-output-names = "uart1_fck";
 792                         clocks = <&core_48m_fck>;
 793                         ti,bit-shift = <13>;
 794                 };
 795
 796                 hdq_fck: clock-hdq-fck {
 797                         #clock-cells = <0>;
 798                         compatible = "ti,wait-gate-clock";
 799                         clock-output-names = "hdq_fck";
 800                         clocks = <&core_12m_fck>;
 801                         ti,bit-shift = <22>;
 802                 };
 803         };
 804
 805         gpt10_fck: gpt10_fck {
 806                 #clock-cells = <0>;
 807                 compatible = "ti,composite-clock";
 808                 clocks = <&gpt10_gate_fck>, <&gpt10_mux_fck>;
 809         };
 810
 811         gpt11_fck: gpt11_fck {
 812                 #clock-cells = <0>;
 813                 compatible = "ti,composite-clock";
 814                 clocks = <&gpt11_gate_fck>, <&gpt11_mux_fck>;
 815         };
 816
 817         core_96m_fck: core_96m_fck {
 818                 #clock-cells = <0>;
 819                 compatible = "fixed-factor-clock";
 820                 clocks = <&omap_96m_fck>;
 821                 clock-mult = <1>;
 822                 clock-div = <1>;
 823         };
 824
 825         core_48m_fck: core_48m_fck {
 826                 #clock-cells = <0>;
 827                 compatible = "fixed-factor-clock";
 828                 clocks = <&omap_48m_fck>;
 829                 clock-mult = <1>;
 830                 clock-div = <1>;
 831         };
 832
 833         core_12m_fck: core_12m_fck {
 834                 #clock-cells = <0>;
 835                 compatible = "fixed-factor-clock";
 836                 clocks = <&omap_12m_fck>;
 837                 clock-mult = <1>;
 838                 clock-div = <1>;
 839         };
 840
 841         core_l3_ick: core_l3_ick {
 842                 #clock-cells = <0>;
 843                 compatible = "fixed-factor-clock";
 844                 clocks = <&l3_ick>;
 845                 clock-mult = <1>;
 846                 clock-div = <1>;
 847         };
 848
 849         /* CM_ICLKEN1_CORE */
 850         clock@a10 {
 851                 compatible = "ti,clksel";
 852                 reg = <0xa10>;
 853                 #clock-cells = <2>;
 854                 #address-cells = <0>;
 855
 856                 sdrc_ick: clock-sdrc-ick {
 857                         #clock-cells = <0>;
 858                         compatible = "ti,wait-gate-clock";
 859                         clock-output-names = "sdrc_ick";
 860                         clocks = <&core_l3_ick>;
 861                         ti,bit-shift = <1>;
 862                 };
 863
 864                 mmchs2_ick: clock-mmchs2-ick {
 865                         #clock-cells = <0>;
 866                         compatible = "ti,omap3-interface-clock";
 867                         clock-output-names = "mmchs2_ick";
 868                         clocks = <&core_l4_ick>;
 869                         ti,bit-shift = <25>;
 870                 };
 871
 872                 mmchs1_ick: clock-mmchs1-ick {
 873                         #clock-cells = <0>;
 874                         compatible = "ti,omap3-interface-clock";
 875                         clock-output-names = "mmchs1_ick";
 876                         clocks = <&core_l4_ick>;
 877                         ti,bit-shift = <24>;
 878                 };
 879
 880                 hdq_ick: clock-hdq-ick {
 881                         #clock-cells = <0>;
 882                         compatible = "ti,omap3-interface-clock";
 883                         clock-output-names = "hdq_ick";
 884                         clocks = <&core_l4_ick>;
 885                         ti,bit-shift = <22>;
 886                 };
 887
 888                 mcspi4_ick: clock-mcspi4-ick {
 889                         #clock-cells = <0>;
 890                         compatible = "ti,omap3-interface-clock";
 891                         clock-output-names = "mcspi4_ick";
 892                         clocks = <&core_l4_ick>;
 893                         ti,bit-shift = <21>;
 894                 };
 895
 896                 mcspi3_ick: clock-mcspi3-ick {
 897                         #clock-cells = <0>;
 898                         compatible = "ti,omap3-interface-clock";
 899                         clock-output-names = "mcspi3_ick";
 900                         clocks = <&core_l4_ick>;
 901                         ti,bit-shift = <20>;
 902                 };
 903
 904                 mcspi2_ick: clock-mcspi2-ick {
 905                         #clock-cells = <0>;
 906                         compatible = "ti,omap3-interface-clock";
 907                         clock-output-names = "mcspi2_ick";
 908                         clocks = <&core_l4_ick>;
 909                         ti,bit-shift = <19>;
 910                 };
 911
 912                 mcspi1_ick: clock-mcspi1-ick {
 913                         #clock-cells = <0>;
 914                         compatible = "ti,omap3-interface-clock";
 915                         clock-output-names = "mcspi1_ick";
 916                         clocks = <&core_l4_ick>;
 917                         ti,bit-shift = <18>;
 918                 };
 919
 920                 i2c3_ick: clock-i2c3-ick {
 921                         #clock-cells = <0>;
 922                         compatible = "ti,omap3-interface-clock";
 923                         clock-output-names = "i2c3_ick";
 924                         clocks = <&core_l4_ick>;
 925                         ti,bit-shift = <17>;
 926                 };
 927
 928                 i2c2_ick: clock-i2c2-ick {
 929                         #clock-cells = <0>;
 930                         compatible = "ti,omap3-interface-clock";
 931                         clock-output-names = "i2c2_ick";
 932                         clocks = <&core_l4_ick>;
 933                         ti,bit-shift = <16>;
 934                 };
 935
 936                 i2c1_ick: clock-i2c1-ick {
 937                         #clock-cells = <0>;
 938                         compatible = "ti,omap3-interface-clock";
 939                         clock-output-names = "i2c1_ick";
 940                         clocks = <&core_l4_ick>;
 941                         ti,bit-shift = <15>;
 942                 };
 943
 944                 uart2_ick: clock-uart2-ick {
 945                         #clock-cells = <0>;
 946                         compatible = "ti,omap3-interface-clock";
 947                         clock-output-names = "uart2_ick";
 948                         clocks = <&core_l4_ick>;
 949                         ti,bit-shift = <14>;
 950                 };
 951
 952                 uart1_ick: clock-uart1-ick {
 953                         #clock-cells = <0>;
 954                         compatible = "ti,omap3-interface-clock";
 955                         clock-output-names = "uart1_ick";
 956                         clocks = <&core_l4_ick>;
 957                         ti,bit-shift = <13>;
 958                 };
 959
 960                 gpt11_ick: clock-gpt11-ick {
 961                         #clock-cells = <0>;
 962                         compatible = "ti,omap3-interface-clock";
 963                         clock-output-names = "gpt11_ick";
 964                         clocks = <&core_l4_ick>;
 965                         ti,bit-shift = <12>;
 966                 };
 967
 968                 gpt10_ick: clock-gpt10-ick {
 969                         #clock-cells = <0>;
 970                         compatible = "ti,omap3-interface-clock";
 971                         clock-output-names = "gpt10_ick";
 972                         clocks = <&core_l4_ick>;
 973                         ti,bit-shift = <11>;
 974                 };
 975
 976                 mcbsp5_ick: clock-mcbsp5-ick {
 977                         #clock-cells = <0>;
 978                         compatible = "ti,omap3-interface-clock";
 979                         clock-output-names = "mcbsp5_ick";
 980                         clocks = <&core_l4_ick>;
 981                         ti,bit-shift = <10>;
 982                 };
 983
 984                 mcbsp1_ick: clock-mcbsp1-ick {
 985                         #clock-cells = <0>;
 986                         compatible = "ti,omap3-interface-clock";
 987                         clock-output-names = "mcbsp1_ick";
 988                         clocks = <&core_l4_ick>;
 989                         ti,bit-shift = <9>;
 990                 };
 991
 992                 omapctrl_ick: clock-omapctrl-ick {
 993                         #clock-cells = <0>;
 994                         compatible = "ti,omap3-interface-clock";
 995                         clock-output-names = "omapctrl_ick";
 996                         clocks = <&core_l4_ick>;
 997                         ti,bit-shift = <6>;
 998                 };
 999
1000                 aes2_ick: clock-aes2-ick {
1001                         #clock-cells = <0>;
1002                         compatible = "ti,omap3-interface-clock";
1003                         clock-output-names = "aes2_ick";
1004                         clocks = <&core_l4_ick>;
1005                         ti,bit-shift = <28>;
1006                 };
1007
1008                 sha12_ick: clock-sha12-ick {
1009                         #clock-cells = <0>;
1010                         compatible = "ti,omap3-interface-clock";
1011                         clock-output-names = "sha12_ick";
1012                         clocks = <&core_l4_ick>;
1013                         ti,bit-shift = <27>;
1014                 };
1015         };
1016
1017         gpmc_fck: gpmc_fck {
1018                 #clock-cells = <0>;
1019                 compatible = "fixed-factor-clock";
1020                 clocks = <&core_l3_ick>;
1021                 clock-mult = <1>;
1022                 clock-div = <1>;
1023         };
1024
1025         core_l4_ick: core_l4_ick {
1026                 #clock-cells = <0>;
1027                 compatible = "fixed-factor-clock";
1028                 clocks = <&l4_ick>;
1029                 clock-mult = <1>;
1030                 clock-div = <1>;
1031         };
1032
1033         /* CM_FCLKEN_DSS */
1034         clock@e00 {
1035                 compatible = "ti,clksel";
1036                 reg = <0xe00>;
1037                 #clock-cells = <2>;
1038                 #address-cells = <0>;
1039
1040                 dss_tv_fck: clock-dss-tv-fck {
1041                         #clock-cells = <0>;
1042                         compatible = "ti,gate-clock";
1043                         clock-output-names = "dss_tv_fck";
1044                         clocks = <&omap_54m_fck>;
1045                         ti,bit-shift = <2>;
1046                 };
1047
1048                 dss_96m_fck: clock-dss-96m-fck {
1049                         #clock-cells = <0>;
1050                         compatible = "ti,gate-clock";
1051                         clock-output-names = "dss_96m_fck";
1052                         clocks = <&omap_96m_fck>;
1053                         ti,bit-shift = <2>;
1054                 };
1055
1056                 dss2_alwon_fck: clock-dss2-alwon-fck {
1057                         #clock-cells = <0>;
1058                         compatible = "ti,gate-clock";
1059                         clock-output-names = "dss2_alwon_fck";
1060                         clocks = <&sys_ck>;
1061                         ti,bit-shift = <1>;
1062                 };
1063         };
1064
1065         dummy_ck: dummy_ck {
1066                 #clock-cells = <0>;
1067                 compatible = "fixed-clock";
1068                 clock-frequency = <0>;
1069         };
1070
1071         /* CM_FCLKEN_WKUP */
1072         clock@c00 {
1073                 compatible = "ti,clksel";
1074                 reg = <0xc00>;
1075                 #clock-cells = <2>;
1076                 #address-cells = <0>;
1077
1078                 gpt1_gate_fck: clock-gpt1-gate-fck {
1079                         #clock-cells = <0>;
1080                         compatible = "ti,composite-gate-clock";
1081                         clock-output-names = "gpt1_gate_fck";
1082                         clocks = <&sys_ck>;
1083                         ti,bit-shift = <0>;
1084                 };
1085
1086                 gpio1_dbck: clock-gpio1-dbck {
1087                         #clock-cells = <0>;
1088                         compatible = "ti,gate-clock";
1089                         clock-output-names = "gpio1_dbck";
1090                         clocks = <&wkup_32k_fck>;
1091                         ti,bit-shift = <3>;
1092                 };
1093
1094                 wdt2_fck: clock-wdt2-fck {
1095                         #clock-cells = <0>;
1096                         compatible = "ti,wait-gate-clock";
1097                         clock-output-names = "wdt2_fck";
1098                         clocks = <&wkup_32k_fck>;
1099                         ti,bit-shift = <5>;
1100                 };
1101         };
1102
1103         gpt1_fck: gpt1_fck {
1104                 #clock-cells = <0>;
1105                 compatible = "ti,composite-clock";
1106                 clocks = <&gpt1_gate_fck>, <&gpt1_mux_fck>;
1107         };
1108
1109         wkup_32k_fck: wkup_32k_fck {
1110                 #clock-cells = <0>;
1111                 compatible = "fixed-factor-clock";
1112                 clocks = <&omap_32k_fck>;
1113                 clock-mult = <1>;
1114                 clock-div = <1>;
1115         };
1116
1117         /* CM_ICLKEN_WKUP */
1118         clock@c10 {
1119                 compatible = "ti,clksel";
1120                 reg = <0xc10>;
1121                 #clock-cells = <2>;
1122                 #address-cells = <0>;
1123
1124                 wdt2_ick: clock-wdt2-ick {
1125                         #clock-cells = <0>;
1126                         compatible = "ti,omap3-interface-clock";
1127                         clock-output-names = "wdt2_ick";
1128                         clocks = <&wkup_l4_ick>;
1129                         ti,bit-shift = <5>;
1130                 };
1131
1132                 wdt1_ick: clock-wdt1-ick {
1133                         #clock-cells = <0>;
1134                         compatible = "ti,omap3-interface-clock";
1135                         clock-output-names = "wdt1_ick";
1136                         clocks = <&wkup_l4_ick>;
1137                         ti,bit-shift = <4>;
1138                 };
1139
1140                 gpio1_ick: clock-gpio1-ick {
1141                         #clock-cells = <0>;
1142                         compatible = "ti,omap3-interface-clock";
1143                         clock-output-names = "gpio1_ick";
1144                         clocks = <&wkup_l4_ick>;
1145                         ti,bit-shift = <3>;
1146                 };
1147
1148                 omap_32ksync_ick: clock-omap-32ksync-ick {
1149                         #clock-cells = <0>;
1150                         compatible = "ti,omap3-interface-clock";
1151                         clock-output-names = "omap_32ksync_ick";
1152                         clocks = <&wkup_l4_ick>;
1153                         ti,bit-shift = <2>;
1154                 };
1155
1156                 gpt12_ick: clock-gpt12-ick {
1157                         #clock-cells = <0>;
1158                         compatible = "ti,omap3-interface-clock";
1159                         clock-output-names = "gpt12_ick";
1160                         clocks = <&wkup_l4_ick>;
1161                         ti,bit-shift = <1>;
1162                 };
1163
1164                 gpt1_ick: clock-gpt1-ick {
1165                         #clock-cells = <0>;
1166                         compatible = "ti,omap3-interface-clock";
1167                         clock-output-names = "gpt1_ick";
1168                         clocks = <&wkup_l4_ick>;
1169                         ti,bit-shift = <0>;
1170                 };
1171         };
1172
1173         per_96m_fck: per_96m_fck {
1174                 #clock-cells = <0>;
1175                 compatible = "fixed-factor-clock";
1176                 clocks = <&omap_96m_alwon_fck>;
1177                 clock-mult = <1>;
1178                 clock-div = <1>;
1179         };
1180
1181         per_48m_fck: per_48m_fck {
1182                 #clock-cells = <0>;
1183                 compatible = "fixed-factor-clock";
1184                 clocks = <&omap_48m_fck>;
1185                 clock-mult = <1>;
1186                 clock-div = <1>;
1187         };
1188
1189         uart3_fck: uart3_fck@1000 {
1190                 #clock-cells = <0>;
1191                 compatible = "ti,wait-gate-clock";
1192                 clocks = <&per_48m_fck>;
1193                 reg = <0x1000>;
1194                 ti,bit-shift = <11>;
1195         };
1196
1197         gpt2_gate_fck: gpt2_gate_fck@1000 {
1198                 #clock-cells = <0>;
1199                 compatible = "ti,composite-gate-clock";
1200                 clocks = <&sys_ck>;
1201                 ti,bit-shift = <3>;
1202                 reg = <0x1000>;
1203         };
1204
1205         gpt2_mux_fck: gpt2_mux_fck@1040 {
1206                 #clock-cells = <0>;
1207                 compatible = "ti,composite-mux-clock";
1208                 clocks = <&omap_32k_fck>, <&sys_ck>;
1209                 reg = <0x1040>;
1210         };
1211
1212         gpt2_fck: gpt2_fck {
1213                 #clock-cells = <0>;
1214                 compatible = "ti,composite-clock";
1215                 clocks = <&gpt2_gate_fck>, <&gpt2_mux_fck>;
1216         };
1217
1218         gpt3_gate_fck: gpt3_gate_fck@1000 {
1219                 #clock-cells = <0>;
1220                 compatible = "ti,composite-gate-clock";
1221                 clocks = <&sys_ck>;
1222                 ti,bit-shift = <4>;
1223                 reg = <0x1000>;
1224         };
1225
1226         gpt3_mux_fck: gpt3_mux_fck@1040 {
1227                 #clock-cells = <0>;
1228                 compatible = "ti,composite-mux-clock";
1229                 clocks = <&omap_32k_fck>, <&sys_ck>;
1230                 ti,bit-shift = <1>;
1231                 reg = <0x1040>;
1232         };
1233
1234         gpt3_fck: gpt3_fck {
1235                 #clock-cells = <0>;
1236                 compatible = "ti,composite-clock";
1237                 clocks = <&gpt3_gate_fck>, <&gpt3_mux_fck>;
1238         };
1239
1240         gpt4_gate_fck: gpt4_gate_fck@1000 {
1241                 #clock-cells = <0>;
1242                 compatible = "ti,composite-gate-clock";
1243                 clocks = <&sys_ck>;
1244                 ti,bit-shift = <5>;
1245                 reg = <0x1000>;
1246         };
1247
1248         gpt4_mux_fck: gpt4_mux_fck@1040 {
1249                 #clock-cells = <0>;
1250                 compatible = "ti,composite-mux-clock";
1251                 clocks = <&omap_32k_fck>, <&sys_ck>;
1252                 ti,bit-shift = <2>;
1253                 reg = <0x1040>;
1254         };
1255
1256         gpt4_fck: gpt4_fck {
1257                 #clock-cells = <0>;
1258                 compatible = "ti,composite-clock";
1259                 clocks = <&gpt4_gate_fck>, <&gpt4_mux_fck>;
1260         };
1261
1262         gpt5_gate_fck: gpt5_gate_fck@1000 {
1263                 #clock-cells = <0>;
1264                 compatible = "ti,composite-gate-clock";
1265                 clocks = <&sys_ck>;
1266                 ti,bit-shift = <6>;
1267                 reg = <0x1000>;
1268         };
1269
1270         gpt5_mux_fck: gpt5_mux_fck@1040 {
1271                 #clock-cells = <0>;
1272                 compatible = "ti,composite-mux-clock";
1273                 clocks = <&omap_32k_fck>, <&sys_ck>;
1274                 ti,bit-shift = <3>;
1275                 reg = <0x1040>;
1276         };
1277
1278         gpt5_fck: gpt5_fck {
1279                 #clock-cells = <0>;
1280                 compatible = "ti,composite-clock";
1281                 clocks = <&gpt5_gate_fck>, <&gpt5_mux_fck>;
1282         };
1283
1284         gpt6_gate_fck: gpt6_gate_fck@1000 {
1285                 #clock-cells = <0>;
1286                 compatible = "ti,composite-gate-clock";
1287                 clocks = <&sys_ck>;
1288                 ti,bit-shift = <7>;
1289                 reg = <0x1000>;
1290         };
1291
1292         gpt6_mux_fck: gpt6_mux_fck@1040 {
1293                 #clock-cells = <0>;
1294                 compatible = "ti,composite-mux-clock";
1295                 clocks = <&omap_32k_fck>, <&sys_ck>;
1296                 ti,bit-shift = <4>;
1297                 reg = <0x1040>;
1298         };
1299
1300         gpt6_fck: gpt6_fck {
1301                 #clock-cells = <0>;
1302                 compatible = "ti,composite-clock";
1303                 clocks = <&gpt6_gate_fck>, <&gpt6_mux_fck>;
1304         };
1305
1306         gpt7_gate_fck: gpt7_gate_fck@1000 {
1307                 #clock-cells = <0>;
1308                 compatible = "ti,composite-gate-clock";
1309                 clocks = <&sys_ck>;
1310                 ti,bit-shift = <8>;
1311                 reg = <0x1000>;
1312         };
1313
1314         gpt7_mux_fck: gpt7_mux_fck@1040 {
1315                 #clock-cells = <0>;
1316                 compatible = "ti,composite-mux-clock";
1317                 clocks = <&omap_32k_fck>, <&sys_ck>;
1318                 ti,bit-shift = <5>;
1319                 reg = <0x1040>;
1320         };
1321
1322         gpt7_fck: gpt7_fck {
1323                 #clock-cells = <0>;
1324                 compatible = "ti,composite-clock";
1325                 clocks = <&gpt7_gate_fck>, <&gpt7_mux_fck>;
1326         };
1327
1328         gpt8_gate_fck: gpt8_gate_fck@1000 {
1329                 #clock-cells = <0>;
1330                 compatible = "ti,composite-gate-clock";
1331                 clocks = <&sys_ck>;
1332                 ti,bit-shift = <9>;
1333                 reg = <0x1000>;
1334         };
1335
1336         gpt8_mux_fck: gpt8_mux_fck@1040 {
1337                 #clock-cells = <0>;
1338                 compatible = "ti,composite-mux-clock";
1339                 clocks = <&omap_32k_fck>, <&sys_ck>;
1340                 ti,bit-shift = <6>;
1341                 reg = <0x1040>;
1342         };
1343
1344         gpt8_fck: gpt8_fck {
1345                 #clock-cells = <0>;
1346                 compatible = "ti,composite-clock";
1347                 clocks = <&gpt8_gate_fck>, <&gpt8_mux_fck>;
1348         };
1349
1350         gpt9_gate_fck: gpt9_gate_fck@1000 {
1351                 #clock-cells = <0>;
1352                 compatible = "ti,composite-gate-clock";
1353                 clocks = <&sys_ck>;
1354                 ti,bit-shift = <10>;
1355                 reg = <0x1000>;
1356         };
1357
1358         gpt9_mux_fck: gpt9_mux_fck@1040 {
1359                 #clock-cells = <0>;
1360                 compatible = "ti,composite-mux-clock";
1361                 clocks = <&omap_32k_fck>, <&sys_ck>;
1362                 ti,bit-shift = <7>;
1363                 reg = <0x1040>;
1364         };
1365
1366         gpt9_fck: gpt9_fck {
1367                 #clock-cells = <0>;
1368                 compatible = "ti,composite-clock";
1369                 clocks = <&gpt9_gate_fck>, <&gpt9_mux_fck>;
1370         };
1371
1372         per_32k_alwon_fck: per_32k_alwon_fck {
1373                 #clock-cells = <0>;
1374                 compatible = "fixed-factor-clock";
1375                 clocks = <&omap_32k_fck>;
1376                 clock-mult = <1>;
1377                 clock-div = <1>;
1378         };
1379
1380         gpio6_dbck: gpio6_dbck@1000 {
1381                 #clock-cells = <0>;
1382                 compatible = "ti,gate-clock";
1383                 clocks = <&per_32k_alwon_fck>;
1384                 reg = <0x1000>;
1385                 ti,bit-shift = <17>;
1386         };
1387
1388         gpio5_dbck: gpio5_dbck@1000 {
1389                 #clock-cells = <0>;
1390                 compatible = "ti,gate-clock";
1391                 clocks = <&per_32k_alwon_fck>;
1392                 reg = <0x1000>;
1393                 ti,bit-shift = <16>;
1394         };
1395
1396         gpio4_dbck: gpio4_dbck@1000 {
1397                 #clock-cells = <0>;
1398                 compatible = "ti,gate-clock";
1399                 clocks = <&per_32k_alwon_fck>;
1400                 reg = <0x1000>;
1401                 ti,bit-shift = <15>;
1402         };
1403
1404         gpio3_dbck: gpio3_dbck@1000 {
1405                 #clock-cells = <0>;
1406                 compatible = "ti,gate-clock";
1407                 clocks = <&per_32k_alwon_fck>;
1408                 reg = <0x1000>;
1409                 ti,bit-shift = <14>;
1410         };
1411
1412         gpio2_dbck: gpio2_dbck@1000 {
1413                 #clock-cells = <0>;
1414                 compatible = "ti,gate-clock";
1415                 clocks = <&per_32k_alwon_fck>;
1416                 reg = <0x1000>;
1417                 ti,bit-shift = <13>;
1418         };
1419
1420         wdt3_fck: wdt3_fck@1000 {
1421                 #clock-cells = <0>;
1422                 compatible = "ti,wait-gate-clock";
1423                 clocks = <&per_32k_alwon_fck>;
1424                 reg = <0x1000>;
1425                 ti,bit-shift = <12>;
1426         };
1427
1428         per_l4_ick: per_l4_ick {
1429                 #clock-cells = <0>;
1430                 compatible = "fixed-factor-clock";
1431                 clocks = <&l4_ick>;
1432                 clock-mult = <1>;
1433                 clock-div = <1>;
1434         };
1435
1436         gpio6_ick: gpio6_ick@1010 {
1437                 #clock-cells = <0>;
1438                 compatible = "ti,omap3-interface-clock";
1439                 clocks = <&per_l4_ick>;
1440                 reg = <0x1010>;
1441                 ti,bit-shift = <17>;
1442         };
1443
1444         gpio5_ick: gpio5_ick@1010 {
1445                 #clock-cells = <0>;
1446                 compatible = "ti,omap3-interface-clock";
1447                 clocks = <&per_l4_ick>;
1448                 reg = <0x1010>;
1449                 ti,bit-shift = <16>;
1450         };
1451
1452         gpio4_ick: gpio4_ick@1010 {
1453                 #clock-cells = <0>;
1454                 compatible = "ti,omap3-interface-clock";
1455                 clocks = <&per_l4_ick>;
1456                 reg = <0x1010>;
1457                 ti,bit-shift = <15>;
1458         };
1459
1460         gpio3_ick: gpio3_ick@1010 {
1461                 #clock-cells = <0>;
1462                 compatible = "ti,omap3-interface-clock";
1463                 clocks = <&per_l4_ick>;
1464                 reg = <0x1010>;
1465                 ti,bit-shift = <14>;
1466         };
1467
1468         gpio2_ick: gpio2_ick@1010 {
1469                 #clock-cells = <0>;
1470                 compatible = "ti,omap3-interface-clock";
1471                 clocks = <&per_l4_ick>;
1472                 reg = <0x1010>;
1473                 ti,bit-shift = <13>;
1474         };
1475
1476         wdt3_ick: wdt3_ick@1010 {
1477                 #clock-cells = <0>;
1478                 compatible = "ti,omap3-interface-clock";
1479                 clocks = <&per_l4_ick>;
1480                 reg = <0x1010>;
1481                 ti,bit-shift = <12>;
1482         };
1483
1484         uart3_ick: uart3_ick@1010 {
1485                 #clock-cells = <0>;
1486                 compatible = "ti,omap3-interface-clock";
1487                 clocks = <&per_l4_ick>;
1488                 reg = <0x1010>;
1489                 ti,bit-shift = <11>;
1490         };
1491
1492         uart4_ick: uart4_ick@1010 {
1493                 #clock-cells = <0>;
1494                 compatible = "ti,omap3-interface-clock";
1495                 clocks = <&per_l4_ick>;
1496                 reg = <0x1010>;
1497                 ti,bit-shift = <18>;
1498         };
1499
1500         gpt9_ick: gpt9_ick@1010 {
1501                 #clock-cells = <0>;
1502                 compatible = "ti,omap3-interface-clock";
1503                 clocks = <&per_l4_ick>;
1504                 reg = <0x1010>;
1505                 ti,bit-shift = <10>;
1506         };
1507
1508         gpt8_ick: gpt8_ick@1010 {
1509                 #clock-cells = <0>;
1510                 compatible = "ti,omap3-interface-clock";
1511                 clocks = <&per_l4_ick>;
1512                 reg = <0x1010>;
1513                 ti,bit-shift = <9>;
1514         };
1515
1516         gpt7_ick: gpt7_ick@1010 {
1517                 #clock-cells = <0>;
1518                 compatible = "ti,omap3-interface-clock";
1519                 clocks = <&per_l4_ick>;
1520                 reg = <0x1010>;
1521                 ti,bit-shift = <8>;
1522         };
1523
1524         gpt6_ick: gpt6_ick@1010 {
1525                 #clock-cells = <0>;
1526                 compatible = "ti,omap3-interface-clock";
1527                 clocks = <&per_l4_ick>;
1528                 reg = <0x1010>;
1529                 ti,bit-shift = <7>;
1530         };
1531
1532         gpt5_ick: gpt5_ick@1010 {
1533                 #clock-cells = <0>;
1534                 compatible = "ti,omap3-interface-clock";
1535                 clocks = <&per_l4_ick>;
1536                 reg = <0x1010>;
1537                 ti,bit-shift = <6>;
1538         };
1539
1540         gpt4_ick: gpt4_ick@1010 {
1541                 #clock-cells = <0>;
1542                 compatible = "ti,omap3-interface-clock";
1543                 clocks = <&per_l4_ick>;
1544                 reg = <0x1010>;
1545                 ti,bit-shift = <5>;
1546         };
1547
1548         gpt3_ick: gpt3_ick@1010 {
1549                 #clock-cells = <0>;
1550                 compatible = "ti,omap3-interface-clock";
1551                 clocks = <&per_l4_ick>;
1552                 reg = <0x1010>;
1553                 ti,bit-shift = <4>;
1554         };
1555
1556         gpt2_ick: gpt2_ick@1010 {
1557                 #clock-cells = <0>;
1558                 compatible = "ti,omap3-interface-clock";
1559                 clocks = <&per_l4_ick>;
1560                 reg = <0x1010>;
1561                 ti,bit-shift = <3>;
1562         };
1563
1564         mcbsp2_ick: mcbsp2_ick@1010 {
1565                 #clock-cells = <0>;
1566                 compatible = "ti,omap3-interface-clock";
1567                 clocks = <&per_l4_ick>;
1568                 reg = <0x1010>;
1569                 ti,bit-shift = <0>;
1570         };
1571
1572         mcbsp3_ick: mcbsp3_ick@1010 {
1573                 #clock-cells = <0>;
1574                 compatible = "ti,omap3-interface-clock";
1575                 clocks = <&per_l4_ick>;
1576                 reg = <0x1010>;
1577                 ti,bit-shift = <1>;
1578         };
1579
1580         mcbsp4_ick: mcbsp4_ick@1010 {
1581                 #clock-cells = <0>;
1582                 compatible = "ti,omap3-interface-clock";
1583                 clocks = <&per_l4_ick>;
1584                 reg = <0x1010>;
1585                 ti,bit-shift = <2>;
1586         };
1587
1588         mcbsp2_gate_fck: mcbsp2_gate_fck@1000 {
1589                 #clock-cells = <0>;
1590                 compatible = "ti,composite-gate-clock";
1591                 clocks = <&mcbsp_clks>;
1592                 ti,bit-shift = <0>;
1593                 reg = <0x1000>;
1594         };
1595
1596         mcbsp3_gate_fck: mcbsp3_gate_fck@1000 {
1597                 #clock-cells = <0>;
1598                 compatible = "ti,composite-gate-clock";
1599                 clocks = <&mcbsp_clks>;
1600                 ti,bit-shift = <1>;
1601                 reg = <0x1000>;
1602         };
1603
1604         mcbsp4_gate_fck: mcbsp4_gate_fck@1000 {
1605                 #clock-cells = <0>;
1606                 compatible = "ti,composite-gate-clock";
1607                 clocks = <&mcbsp_clks>;
1608                 ti,bit-shift = <2>;
1609                 reg = <0x1000>;
1610         };
1611
1612         emu_src_mux_ck: emu_src_mux_ck@1140 {
1613                 #clock-cells = <0>;
1614                 compatible = "ti,mux-clock";
1615                 clocks = <&sys_ck>, <&emu_core_alwon_ck>, <&emu_per_alwon_ck>, <&emu_mpu_alwon_ck>;
1616                 reg = <0x1140>;
1617         };
1618
1619         emu_src_ck: emu_src_ck {
1620                 #clock-cells = <0>;
1621                 compatible = "ti,clkdm-gate-clock";
1622                 clocks = <&emu_src_mux_ck>;
1623         };
1624
1625         pclk_fck: pclk_fck@1140 {
1626                 #clock-cells = <0>;
1627                 compatible = "ti,divider-clock";
1628                 clocks = <&emu_src_ck>;
1629                 ti,bit-shift = <8>;
1630                 ti,max-div = <7>;
1631                 reg = <0x1140>;
1632                 ti,index-starts-at-one;
1633         };
1634
1635         pclkx2_fck: pclkx2_fck@1140 {
1636                 #clock-cells = <0>;
1637                 compatible = "ti,divider-clock";
1638                 clocks = <&emu_src_ck>;
1639                 ti,bit-shift = <6>;
1640                 ti,max-div = <3>;
1641                 reg = <0x1140>;
1642                 ti,index-starts-at-one;
1643         };
1644
1645         atclk_fck: atclk_fck@1140 {
1646                 #clock-cells = <0>;
1647                 compatible = "ti,divider-clock";
1648                 clocks = <&emu_src_ck>;
1649                 ti,bit-shift = <4>;
1650                 ti,max-div = <3>;
1651                 reg = <0x1140>;
1652                 ti,index-starts-at-one;
1653         };
1654
1655         traceclk_src_fck: traceclk_src_fck@1140 {
1656                 #clock-cells = <0>;
1657                 compatible = "ti,mux-clock";
1658                 clocks = <&sys_ck>, <&emu_core_alwon_ck>, <&emu_per_alwon_ck>, <&emu_mpu_alwon_ck>;
1659                 ti,bit-shift = <2>;
1660                 reg = <0x1140>;
1661         };
1662
1663         traceclk_fck: traceclk_fck@1140 {
1664                 #clock-cells = <0>;
1665                 compatible = "ti,divider-clock";
1666                 clocks = <&traceclk_src_fck>;
1667                 ti,bit-shift = <11>;
1668                 ti,max-div = <7>;
1669                 reg = <0x1140>;
1670                 ti,index-starts-at-one;
1671         };
1672
1673         secure_32k_fck: secure_32k_fck {
1674                 #clock-cells = <0>;
1675                 compatible = "fixed-clock";
1676                 clock-frequency = <32768>;
1677         };
1678
1679         gpt12_fck: gpt12_fck {
1680                 #clock-cells = <0>;
1681                 compatible = "fixed-factor-clock";
1682                 clocks = <&secure_32k_fck>;
1683                 clock-mult = <1>;
1684                 clock-div = <1>;
1685         };
1686
1687         wdt1_fck: wdt1_fck {
1688                 #clock-cells = <0>;
1689                 compatible = "fixed-factor-clock";
1690                 clocks = <&secure_32k_fck>;
1691                 clock-mult = <1>;
1692                 clock-div = <1>;
1693         };
1694 };
1695
1696 &cm_clockdomains {
1697         core_l3_clkdm: core_l3_clkdm {
1698                 compatible = "ti,clockdomain";
1699                 clocks = <&sdrc_ick>;
1700         };
1701
1702         dpll3_clkdm: dpll3_clkdm {
1703                 compatible = "ti,clockdomain";
1704                 clocks = <&dpll3_ck>;
1705         };
1706
1707         dpll1_clkdm: dpll1_clkdm {
1708                 compatible = "ti,clockdomain";
1709                 clocks = <&dpll1_ck>;
1710         };
1711
1712         per_clkdm: per_clkdm {
1713                 compatible = "ti,clockdomain";
1714                 clocks = <&uart3_fck>, <&gpio6_dbck>, <&gpio5_dbck>,
1715                          <&gpio4_dbck>, <&gpio3_dbck>, <&gpio2_dbck>,
1716                          <&wdt3_fck>, <&gpio6_ick>, <&gpio5_ick>, <&gpio4_ick>,
1717                          <&gpio3_ick>, <&gpio2_ick>, <&wdt3_ick>, <&uart3_ick>,
1718                          <&uart4_ick>, <&gpt9_ick>, <&gpt8_ick>, <&gpt7_ick>,
1719                          <&gpt6_ick>, <&gpt5_ick>, <&gpt4_ick>, <&gpt3_ick>,
1720                          <&gpt2_ick>, <&mcbsp2_ick>, <&mcbsp3_ick>,
1721                          <&mcbsp4_ick>;
1722         };
1723
1724         emu_clkdm: emu_clkdm {
1725                 compatible = "ti,clockdomain";
1726                 clocks = <&emu_src_ck>;
1727         };
1728
1729         dpll4_clkdm: dpll4_clkdm {
1730                 compatible = "ti,clockdomain";
1731                 clocks = <&dpll4_ck>;
1732         };
1733
1734         wkup_clkdm: wkup_clkdm {
1735                 compatible = "ti,clockdomain";
1736                 clocks = <&gpio1_dbck>, <&wdt2_fck>, <&wdt2_ick>, <&wdt1_ick>,
1737                          <&gpio1_ick>, <&omap_32ksync_ick>, <&gpt12_ick>,
1738                          <&gpt1_ick>;
1739         };
1740
1741         dss_clkdm: dss_clkdm {
1742                 compatible = "ti,clockdomain";
1743                 clocks = <&dss_tv_fck>, <&dss_96m_fck>, <&dss2_alwon_fck>;
1744         };
1745
1746         core_l4_clkdm: core_l4_clkdm {
1747                 compatible = "ti,clockdomain";
1748                 clocks = <&mmchs2_fck>, <&mmchs1_fck>, <&i2c3_fck>, <&i2c2_fck>,
1749                          <&i2c1_fck>, <&mcspi4_fck>, <&mcspi3_fck>,
1750                          <&mcspi2_fck>, <&mcspi1_fck>, <&uart2_fck>,
1751                          <&uart1_fck>, <&hdq_fck>, <&mmchs2_ick>, <&mmchs1_ick>,
1752                          <&hdq_ick>, <&mcspi4_ick>, <&mcspi3_ick>,
1753                          <&mcspi2_ick>, <&mcspi1_ick>, <&i2c3_ick>, <&i2c2_ick>,
1754                          <&i2c1_ick>, <&uart2_ick>, <&uart1_ick>, <&gpt11_ick>,
1755                          <&gpt10_ick>, <&mcbsp5_ick>, <&mcbsp1_ick>,
1756                          <&omapctrl_ick>, <&aes2_ick>, <&sha12_ick>;
1757         };
1758 };