arch/arm/boot/dts/omap36xx-omap3430es2plus-clocks.dtsi

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Device Tree Source for OMAP34xx/OMAP36xx clock data
   4  *
   5  * Copyright (C) 2013 Texas Instruments, Inc.
   6  */
   7 &cm_clocks {
   8         clock@a00 {
   9                 compatible = "ti,clksel";
  10                 reg = <0xa00>;
  11                 #clock-cells = <2>;
  12                 #address-cells = <0>;
  13
  14                 ssi_ssr_gate_fck_3430es2: clock-ssi-ssr-gate-fck-3430es2 {
  15                         #clock-cells = <0>;
  16                         compatible = "ti,composite-no-wait-gate-clock";
  17                         clock-output-names = "ssi_ssr_gate_fck_3430es2";
  18                         clocks = <&corex2_fck>;
  19                         ti,bit-shift = <0>;
  20                 };
  21         };
  22
  23         clock@a40 {
  24                 compatible = "ti,clksel";
  25                 reg = <0xa40>;
  26                 #clock-cells = <2>;
  27                 #address-cells = <0>;
  28
  29                 ssi_ssr_div_fck_3430es2: clock-ssi-ssr-div-fck-3430es2 {
  30                         #clock-cells = <0>;
  31                         compatible = "ti,composite-divider-clock";
  32                         clock-output-names = "ssi_ssr_div_fck_3430es2";
  33                         clocks = <&corex2_fck>;
  34                         ti,bit-shift = <8>;
  35                         ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>;
  36                 };
  37         };
  38
  39         ssi_ssr_fck: ssi_ssr_fck_3430es2 {
  40                 #clock-cells = <0>;
  41                 compatible = "ti,composite-clock";
  42                 clocks = <&ssi_ssr_gate_fck_3430es2>, <&ssi_ssr_div_fck_3430es2>;
  43         };
  44
  45         ssi_sst_fck: ssi_sst_fck_3430es2 {
  46                 #clock-cells = <0>;
  47                 compatible = "fixed-factor-clock";
  48                 clocks = <&ssi_ssr_fck>;
  49                 clock-mult = <1>;
  50                 clock-div = <2>;
  51         };
  52
  53         clock@a10 {
  54                 compatible = "ti,clksel";
  55                 reg = <0xa10>;
  56                 #clock-cells = <2>;
  57                 #address-cells = <0>;
  58
  59                 hsotgusb_ick_3430es2: clock-hsotgusb-ick-3430es2 {
  60                         #clock-cells = <0>;
  61                         compatible = "ti,omap3-hsotgusb-interface-clock";
  62                         clock-output-names = "hsotgusb_ick_3430es2";
  63                         clocks = <&core_l3_ick>;
  64                         ti,bit-shift = <4>;
  65                 };
  66
  67                 ssi_ick: clock-ssi-ick-3430es2 {
  68                         #clock-cells = <0>;
  69                         compatible = "ti,omap3-ssi-interface-clock";
  70                         clock-output-names = "ssi_ick_3430es2";
  71                         clocks = <&ssi_l4_ick>;
  72                         ti,bit-shift = <0>;
  73                 };
  74         };
  75
  76         ssi_l4_ick: ssi_l4_ick {
  77                 #clock-cells = <0>;
  78                 compatible = "fixed-factor-clock";
  79                 clocks = <&l4_ick>;
  80                 clock-mult = <1>;
  81                 clock-div = <1>;
  82         };
  83
  84         usim_gate_fck: usim_gate_fck@c00 {
  85                 #clock-cells = <0>;
  86                 compatible = "ti,composite-gate-clock";
  87                 clocks = <&omap_96m_fck>;
  88                 ti,bit-shift = <9>;
  89                 reg = <0x0c00>;
  90         };
  91
  92         sys_d2_ck: sys_d2_ck {
  93                 #clock-cells = <0>;
  94                 compatible = "fixed-factor-clock";
  95                 clocks = <&sys_ck>;
  96                 clock-mult = <1>;
  97                 clock-div = <2>;
  98         };
  99
 100         omap_96m_d2_fck: omap_96m_d2_fck {
 101                 #clock-cells = <0>;
 102                 compatible = "fixed-factor-clock";
 103                 clocks = <&omap_96m_fck>;
 104                 clock-mult = <1>;
 105                 clock-div = <2>;
 106         };
 107
 108         omap_96m_d4_fck: omap_96m_d4_fck {
 109                 #clock-cells = <0>;
 110                 compatible = "fixed-factor-clock";
 111                 clocks = <&omap_96m_fck>;
 112                 clock-mult = <1>;
 113                 clock-div = <4>;
 114         };
 115
 116         omap_96m_d8_fck: omap_96m_d8_fck {
 117                 #clock-cells = <0>;
 118                 compatible = "fixed-factor-clock";
 119                 clocks = <&omap_96m_fck>;
 120                 clock-mult = <1>;
 121                 clock-div = <8>;
 122         };
 123
 124         omap_96m_d10_fck: omap_96m_d10_fck {
 125                 #clock-cells = <0>;
 126                 compatible = "fixed-factor-clock";
 127                 clocks = <&omap_96m_fck>;
 128                 clock-mult = <1>;
 129                 clock-div = <10>;
 130         };
 131
 132         dpll5_m2_d4_ck: dpll5_m2_d4_ck {
 133                 #clock-cells = <0>;
 134                 compatible = "fixed-factor-clock";
 135                 clocks = <&dpll5_m2_ck>;
 136                 clock-mult = <1>;
 137                 clock-div = <4>;
 138         };
 139
 140         dpll5_m2_d8_ck: dpll5_m2_d8_ck {
 141                 #clock-cells = <0>;
 142                 compatible = "fixed-factor-clock";
 143                 clocks = <&dpll5_m2_ck>;
 144                 clock-mult = <1>;
 145                 clock-div = <8>;
 146         };
 147
 148         dpll5_m2_d16_ck: dpll5_m2_d16_ck {
 149                 #clock-cells = <0>;
 150                 compatible = "fixed-factor-clock";
 151                 clocks = <&dpll5_m2_ck>;
 152                 clock-mult = <1>;
 153                 clock-div = <16>;
 154         };
 155
 156         dpll5_m2_d20_ck: dpll5_m2_d20_ck {
 157                 #clock-cells = <0>;
 158                 compatible = "fixed-factor-clock";
 159                 clocks = <&dpll5_m2_ck>;
 160                 clock-mult = <1>;
 161                 clock-div = <20>;
 162         };
 163
 164         usim_mux_fck: usim_mux_fck@c40 {
 165                 #clock-cells = <0>;
 166                 compatible = "ti,composite-mux-clock";
 167                 clocks = <&sys_ck>, <&sys_d2_ck>, <&omap_96m_d2_fck>, <&omap_96m_d4_fck>, <&omap_96m_d8_fck>, <&omap_96m_d10_fck>, <&dpll5_m2_d4_ck>, <&dpll5_m2_d8_ck>, <&dpll5_m2_d16_ck>, <&dpll5_m2_d20_ck>;
 168                 ti,bit-shift = <3>;
 169                 reg = <0x0c40>;
 170                 ti,index-starts-at-one;
 171         };
 172
 173         usim_fck: usim_fck {
 174                 #clock-cells = <0>;
 175                 compatible = "ti,composite-clock";
 176                 clocks = <&usim_gate_fck>, <&usim_mux_fck>;
 177         };
 178
 179         usim_ick: usim_ick@c10 {
 180                 #clock-cells = <0>;
 181                 compatible = "ti,omap3-interface-clock";
 182                 clocks = <&wkup_l4_ick>;
 183                 reg = <0x0c10>;
 184                 ti,bit-shift = <9>;
 185         };
 186 };
 187
 188 &cm_clockdomains {
 189         core_l3_clkdm: core_l3_clkdm {
 190                 compatible = "ti,clockdomain";
 191                 clocks = <&sdrc_ick>, <&hsotgusb_ick_3430es2>;
 192         };
 193
 194         wkup_clkdm: wkup_clkdm {
 195                 compatible = "ti,clockdomain";
 196                 clocks = <&gpio1_dbck>, <&wdt2_fck>, <&wdt2_ick>, <&wdt1_ick>,
 197                          <&gpio1_ick>, <&omap_32ksync_ick>, <&gpt12_ick>,
 198                          <&gpt1_ick>, <&usim_ick>;
 199         };
 200
 201         core_l4_clkdm: core_l4_clkdm {
 202                 compatible = "ti,clockdomain";
 203                 clocks = <&cpefuse_fck>, <&ts_fck>, <&usbtll_fck>,
 204                          <&usbtll_ick>, <&mmchs3_ick>, <&mmchs3_fck>,
 205                          <&mmchs2_fck>, <&mmchs1_fck>, <&i2c3_fck>, <&i2c2_fck>,
 206                          <&i2c1_fck>, <&mcspi4_fck>, <&mcspi3_fck>,
 207                          <&mcspi2_fck>, <&mcspi1_fck>, <&uart2_fck>,
 208                          <&uart1_fck>, <&hdq_fck>, <&mmchs2_ick>, <&mmchs1_ick>,
 209                          <&hdq_ick>, <&mcspi4_ick>, <&mcspi3_ick>,
 210                          <&mcspi2_ick>, <&mcspi1_ick>, <&i2c3_ick>, <&i2c2_ick>,
 211                          <&i2c1_ick>, <&uart2_ick>, <&uart1_ick>, <&gpt11_ick>,
 212                          <&gpt10_ick>, <&mcbsp5_ick>, <&mcbsp1_ick>,
 213                          <&omapctrl_ick>, <&aes2_ick>, <&sha12_ick>,
 214                          <&ssi_ick>;
 215         };
 216 };