arch/arm/boot/dts/lpc18xx.dtsi

   1 /*
   2  * Common base for NXP LPC18xx and LPC43xx devices.
   3  *
   4  * Copyright 2015 Joachim Eastwood <manabian@gmail.com>
   5  *
   6  * This code is released using a dual license strategy: BSD/GPL
   7  * You can choose the licence that better fits your requirements.
   8  *
   9  * Released under the terms of 3-clause BSD License
  10  * Released under the terms of GNU General Public License Version 2.0
  11  *
  12  */
  13
  14 #include "armv7-m.dtsi"
  15
  16 #include "dt-bindings/clock/lpc18xx-cgu.h"
  17 #include "dt-bindings/clock/lpc18xx-ccu.h"
  18
  19 #define LPC_PIN(port, pin)      (0x##port * 32 + pin)
  20 #define LPC_GPIO(port, pin)     (port * 32 + pin)
  21
  22 / {
  23         #address-cells = <1>;
  24         #size-cells = <1>;
  25
  26         cpus {
  27                 #address-cells = <1>;
  28                 #size-cells = <0>;
  29
  30                 cpu@0 {
  31                         compatible = "arm,cortex-m3";
  32                         device_type = "cpu";
  33                         reg = <0x0>;
  34                         clocks = <&ccu1 CLK_CPU_CORE>;
  35                 };
  36         };
  37
  38         clocks {
  39                 xtal: xtal {
  40                         compatible = "fixed-clock";
  41                         #clock-cells = <0>;
  42                         clock-frequency = <12000000>;
  43                 };
  44
  45                 xtal32: xtal32 {
  46                         compatible = "fixed-clock";
  47                         #clock-cells = <0>;
  48                         clock-frequency = <32768>;
  49                 };
  50
  51                 enet_rx_clk: enet_rx_clk {
  52                         compatible = "fixed-clock";
  53                         #clock-cells = <0>;
  54                         clock-frequency = <0>;
  55                         clock-output-names = "enet_rx_clk";
  56                 };
  57
  58                 enet_tx_clk: enet_tx_clk {
  59                         compatible = "fixed-clock";
  60                         #clock-cells = <0>;
  61                         clock-frequency = <0>;
  62                         clock-output-names = "enet_tx_clk";
  63                 };
  64
  65                 gp_clkin: gp_clkin {
  66                         compatible = "fixed-clock";
  67                         #clock-cells = <0>;
  68                         clock-frequency = <0>;
  69                         clock-output-names = "gp_clkin";
  70                 };
  71         };
  72
  73         soc {
  74                 sct_pwm: pwm@40000000 {
  75                         compatible = "nxp,lpc1850-sct-pwm";
  76                         reg = <0x40000000 0x1000>;
  77                         clocks =<&ccu1 CLK_CPU_SCT>;
  78                         clock-names = "pwm";
  79                         resets = <&rgu 37>;
  80                         #pwm-cells = <3>;
  81                         status = "disabled";
  82                 };
  83
  84                 dmac: dma-controller@40002000 {
  85                         compatible = "arm,pl080", "arm,primecell";
  86                         arm,primecell-periphid = <0x00041080>;
  87                         reg = <0x40002000 0x1000>;
  88                         interrupts = <2>;
  89                         clocks = <&ccu1 CLK_CPU_DMA>;
  90                         clock-names = "apb_pclk";
  91                         resets = <&rgu 19>;
  92                         #dma-cells = <2>;
  93                         dma-channels = <8>;
  94                         dma-requests = <16>;
  95                         lli-bus-interface-ahb1;
  96                         lli-bus-interface-ahb2;
  97                         mem-bus-interface-ahb1;
  98                         mem-bus-interface-ahb2;
  99                         memcpy-burst-size = <256>;
 100                         memcpy-bus-width = <32>;
 101                 };
 102
 103                 spifi: flash-controller@40003000 {
 104                         compatible = "nxp,lpc1773-spifi";
 105                         reg = <0x40003000 0x1000>, <0x14000000 0x4000000>;
 106                         reg-names = "spifi", "flash";
 107                         interrupts = <30>;
 108                         clocks = <&ccu1 CLK_SPIFI>, <&ccu1 CLK_CPU_SPIFI>;
 109                         clock-names = "spifi", "reg";
 110                         resets = <&rgu 53>;
 111                         status = "disabled";
 112                 };
 113
 114                 mmcsd: mmcsd@40004000 {
 115                         compatible = "snps,dw-mshc";
 116                         reg = <0x40004000 0x1000>;
 117                         interrupts = <6>;
 118                         clocks = <&ccu2 CLK_SDIO>, <&ccu1 CLK_CPU_SDIO>;
 119                         clock-names = "ciu", "biu";
 120                         resets = <&rgu 20>;
 121                         status = "disabled";
 122                 };
 123
 124                 usb0: ehci@40006100 {
 125                         compatible = "nxp,lpc1850-ehci", "generic-ehci";
 126                         reg = <0x40006100 0x100>;
 127                         interrupts = <8>;
 128                         clocks = <&ccu1 CLK_CPU_USB0>;
 129                         resets = <&rgu 17>;
 130                         phys = <&usb0_otg_phy>;
 131                         phy-names = "usb";
 132                         has-transaction-translator;
 133                         status = "disabled";
 134                 };
 135
 136                 usb1: ehci@40007100 {
 137                         compatible = "nxp,lpc1850-ehci", "generic-ehci";
 138                         reg = <0x40007100 0x100>;
 139                         interrupts = <9>;
 140                         clocks = <&ccu1 CLK_CPU_USB1>;
 141                         resets = <&rgu 18>;
 142                         status = "disabled";
 143                 };
 144
 145                 emc: memory-controller@40005000 {
 146                         compatible = "arm,pl172", "arm,primecell";
 147                         reg = <0x40005000 0x1000>;
 148                         clocks = <&ccu1 CLK_CPU_EMCDIV>, <&ccu1 CLK_CPU_EMC>;
 149                         clock-names = "mpmcclk", "apb_pclk";
 150                         resets = <&rgu 21>;
 151                         #address-cells = <2>;
 152                         #size-cells = <1>;
 153                         ranges = <0 0 0x1c000000 0x1000000
 154                                   1 0 0x1d000000 0x1000000
 155                                   2 0 0x1e000000 0x1000000
 156                                   3 0 0x1f000000 0x1000000>;
 157                         status = "disabled";
 158                 };
 159
 160                 lcdc: lcd-controller@40008000 {
 161                         compatible = "arm,pl111", "arm,primecell";
 162                         reg = <0x40008000 0x1000>;
 163                         interrupts = <7>;
 164                         interrupt-names = "combined";
 165                         clocks = <&cgu BASE_LCD_CLK>, <&ccu1 CLK_CPU_LCD>;
 166                         clock-names = "clcdclk", "apb_pclk";
 167                         resets = <&rgu 16>;
 168                         status = "disabled";
 169                 };
 170
 171                 eeprom: eeprom@4000e000 {
 172                         compatible = "nxp,lpc1857-eeprom";
 173                         reg = <0x4000e000 0x1000>, <0x20040000 0x4000>;
 174                         reg-names = "reg", "mem";
 175                         clocks = <&ccu1 CLK_CPU_EEPROM>;
 176                         clock-names = "eeprom";
 177                         resets = <&rgu 27>;
 178                         interrupts = <4>;
 179                         status = "disabled";
 180                 };
 181
 182                 mac: ethernet@40010000 {
 183                         compatible = "nxp,lpc1850-dwmac", "snps,dwmac-3.611", "snps,dwmac";
 184                         reg = <0x40010000 0x2000>;
 185                         interrupts = <5>;
 186                         interrupt-names = "macirq";
 187                         clocks = <&ccu1 CLK_CPU_ETHERNET>;
 188                         clock-names = "stmmaceth";
 189                         resets = <&rgu 22>;
 190                         reset-names = "stmmaceth";
 191                         rx-fifo-depth = <256>;
 192                         tx-fifo-depth = <256>;
 193                         snps,pbl = <4>; /* 32 (8x mode) */
 194                         snps,force_thresh_dma_mode;
 195                         status = "disabled";
 196                 };
 197
 198                 creg: syscon@40043000 {
 199                         compatible = "nxp,lpc1850-creg", "syscon", "simple-mfd";
 200                         reg = <0x40043000 0x1000>;
 201                         clocks = <&ccu1 CLK_CPU_CREG>;
 202                         resets = <&rgu 5>;
 203
 204                         creg_clk: clock-controller {
 205                                 compatible = "nxp,lpc1850-creg-clk";
 206                                 clocks = <&xtal32>;
 207                                 #clock-cells = <1>;
 208                         };
 209
 210                         usb0_otg_phy: phy {
 211                                 compatible = "nxp,lpc1850-usb-otg-phy";
 212                                 clocks = <&ccu1 CLK_USB0>;
 213                                 #phy-cells = <0>;
 214                         };
 215
 216                         dmamux: dma-mux {
 217                                 compatible = "nxp,lpc1850-dmamux";
 218                                 #dma-cells = <3>;
 219                                 dma-requests = <64>;
 220                                 dma-masters = <&dmac>;
 221                         };
 222                 };
 223
 224                 rtc: rtc@40046000 {
 225                         compatible = "nxp,lpc1850-rtc", "nxp,lpc1788-rtc";
 226                         reg = <0x40046000 0x1000>;
 227                         interrupts = <47>;
 228                         clocks = <&creg_clk 0>, <&ccu1 CLK_CPU_BUS>;
 229                         clock-names = "rtc", "reg";
 230                 };
 231
 232                 cgu: clock-controller@40050000 {
 233                         compatible = "nxp,lpc1850-cgu";
 234                         reg = <0x40050000 0x1000>;
 235                         #clock-cells = <1>;
 236                         clocks = <&xtal>, <&creg_clk 1>, <&enet_rx_clk>, <&enet_tx_clk>, <&gp_clkin>;
 237                 };
 238
 239                 ccu1: clock-controller@40051000 {
 240                         compatible = "nxp,lpc1850-ccu";
 241                         reg = <0x40051000 0x1000>;
 242                         #clock-cells = <1>;
 243                         clocks = <&cgu BASE_APB3_CLK>,   <&cgu BASE_APB1_CLK>,
 244                                  <&cgu BASE_SPIFI_CLK>,  <&cgu BASE_CPU_CLK>,
 245                                  <&cgu BASE_PERIPH_CLK>, <&cgu BASE_USB0_CLK>,
 246                                  <&cgu BASE_USB1_CLK>,   <&cgu BASE_SPI_CLK>;
 247                         clock-names = "base_apb3_clk",   "base_apb1_clk",
 248                                       "base_spifi_clk",  "base_cpu_clk",
 249                                       "base_periph_clk", "base_usb0_clk",
 250                                       "base_usb1_clk",   "base_spi_clk";
 251                 };
 252
 253                 ccu2: clock-controller@40052000 {
 254                         compatible = "nxp,lpc1850-ccu";
 255                         reg = <0x40052000 0x1000>;
 256                         #clock-cells = <1>;
 257                         clocks = <&cgu BASE_AUDIO_CLK>, <&cgu BASE_UART3_CLK>,
 258                                  <&cgu BASE_UART2_CLK>, <&cgu BASE_UART1_CLK>,
 259                                  <&cgu BASE_UART0_CLK>, <&cgu BASE_SSP1_CLK>,
 260                                  <&cgu BASE_SSP0_CLK>,  <&cgu BASE_SDIO_CLK>;
 261                         clock-names = "base_audio_clk", "base_uart3_clk",
 262                                       "base_uart2_clk", "base_uart1_clk",
 263                                       "base_uart0_clk", "base_ssp1_clk",
 264                                       "base_ssp0_clk",  "base_sdio_clk";
 265                 };
 266
 267                 rgu: reset-controller@40053000 {
 268                         compatible = "nxp,lpc1850-rgu";
 269                         reg = <0x40053000 0x1000>;
 270                         clocks = <&cgu BASE_SAFE_CLK>, <&ccu1 CLK_CPU_BUS>;
 271                         clock-names = "delay", "reg";
 272                         #reset-cells = <1>;
 273                 };
 274
 275                 watchdog@40080000 {
 276                         compatible = "nxp,lpc1850-wwdt";
 277                         reg = <0x40080000 0x24>;
 278                         interrupts = <49>;
 279                         clocks = <&cgu BASE_SAFE_CLK>, <&ccu1 CLK_CPU_WWDT>;
 280                         clock-names = "wdtclk", "reg";
 281                 };
 282
 283                 uart0: serial@40081000 {
 284                         compatible = "nxp,lpc1850-uart", "ns16550a";
 285                         reg = <0x40081000 0x1000>;
 286                         reg-shift = <2>;
 287                         interrupts = <24>;
 288                         clocks = <&ccu2 CLK_APB0_UART0>, <&ccu1 CLK_CPU_UART0>;
 289                         clock-names = "uartclk", "reg";
 290                         resets = <&rgu 44>;
 291                         dmas = <&dmamux  1 1 2
 292                                 &dmamux  2 1 2
 293                                 &dmamux 11 2 2
 294                                 &dmamux 12 2 2>;
 295                         dma-names = "tx", "rx", "tx", "rx";
 296                         status = "disabled";
 297                 };
 298
 299                 uart1: serial@40082000 {
 300                         compatible = "nxp,lpc1850-uart", "ns16550a";
 301                         reg = <0x40082000 0x1000>;
 302                         reg-shift = <2>;
 303                         interrupts = <25>;
 304                         clocks = <&ccu2 CLK_APB0_UART1>, <&ccu1 CLK_CPU_UART1>;
 305                         clock-names = "uartclk", "reg";
 306                         resets = <&rgu 45>;
 307                         dmas = <&dmamux 3 1 2
 308                                 &dmamux 4 1 2>;
 309                         dma-names = "tx", "rx";
 310                         status = "disabled";
 311                 };
 312
 313                 ssp0: spi@40083000 {
 314                         compatible = "arm,pl022", "arm,primecell";
 315                         reg = <0x40083000 0x1000>;
 316                         interrupts = <22>;
 317                         clocks = <&ccu2 CLK_APB0_SSP0>, <&ccu1 CLK_CPU_SSP0>;
 318                         clock-names = "sspclk", "apb_pclk";
 319                         resets = <&rgu 50>;
 320                         dmas = <&dmamux  9 0 2
 321                                 &dmamux 10 0 2>;
 322                         dma-names = "rx", "tx";
 323                         #address-cells = <1>;
 324                         #size-cells = <0>;
 325                         status = "disabled";
 326                 };
 327
 328                 timer0: timer@40084000 {
 329                         compatible = "nxp,lpc3220-timer";
 330                         reg = <0x40084000 0x1000>;
 331                         interrupts = <12>;
 332                         clocks = <&ccu1 CLK_CPU_TIMER0>;
 333                         clock-names = "timerclk";
 334                         resets = <&rgu 32>;
 335                 };
 336
 337                 timer1: timer@40085000 {
 338                         compatible = "nxp,lpc3220-timer";
 339                         reg = <0x40085000 0x1000>;
 340                         interrupts = <13>;
 341                         clocks = <&ccu1 CLK_CPU_TIMER1>;
 342                         clock-names = "timerclk";
 343                         resets = <&rgu 33>;
 344                 };
 345
 346                 pinctrl: pinctrl@40086000 {
 347                         compatible = "nxp,lpc1850-scu";
 348                         reg = <0x40086000 0x1000>;
 349                         clocks = <&ccu1 CLK_CPU_SCU>;
 350                 };
 351
 352                 i2c0: i2c@400a1000 {
 353                         compatible = "nxp,lpc1788-i2c";
 354                         reg = <0x400a1000 0x1000>;
 355                         interrupts = <18>;
 356                         clocks = <&ccu1 CLK_APB1_I2C0>;
 357                         resets = <&rgu 48>;
 358                         #address-cells = <1>;
 359                         #size-cells = <0>;
 360                         status = "disabled";
 361                 };
 362
 363                 can1: can@400a4000 {
 364                         compatible = "bosch,c_can";
 365                         reg = <0x400a4000 0x1000>;
 366                         interrupts = <43>;
 367                         clocks = <&ccu1 CLK_APB1_CAN1>;
 368                         resets = <&rgu 54>;
 369                         status = "disabled";
 370                 };
 371
 372                 uart2: serial@400c1000 {
 373                         compatible = "nxp,lpc1850-uart", "ns16550a";
 374                         reg = <0x400c1000 0x1000>;
 375                         reg-shift = <2>;
 376                         interrupts = <26>;
 377                         clocks = <&ccu2 CLK_APB2_UART2>, <&ccu1 CLK_CPU_UART2>;
 378                         clock-names = "uartclk", "reg";
 379                         resets = <&rgu 46>;
 380                         dmas = <&dmamux 5 1 2
 381                                 &dmamux 6 1 2>;
 382                         dma-names = "tx", "rx";
 383                         status = "disabled";
 384                 };
 385
 386                 uart3: serial@400c2000 {
 387                         compatible = "nxp,lpc1850-uart", "ns16550a";
 388                         reg = <0x400c2000 0x1000>;
 389                         reg-shift = <2>;
 390                         interrupts = <27>;
 391                         clocks = <&ccu2 CLK_APB2_UART3>, <&ccu1 CLK_CPU_UART3>;
 392                         clock-names = "uartclk", "reg";
 393                         resets = <&rgu 47>;
 394                         dmas = <&dmamux  7 1 2
 395                                 &dmamux  8 1 2
 396                                 &dmamux 13 3 2
 397                                 &dmamux 14 3 2>;
 398                         dma-names = "tx", "rx", "rx", "tx";
 399                         status = "disabled";
 400                 };
 401
 402                 timer2: timer@400c3000 {
 403                         compatible = "nxp,lpc3220-timer";
 404                         reg = <0x400c3000 0x1000>;
 405                         interrupts = <14>;
 406                         clocks = <&ccu1 CLK_CPU_TIMER2>;
 407                         clock-names = "timerclk";
 408                         resets = <&rgu 34>;
 409                 };
 410
 411                 timer3: timer@400c4000 {
 412                         compatible = "nxp,lpc3220-timer";
 413                         reg = <0x400c4000 0x1000>;
 414                         interrupts = <15>;
 415                         clocks = <&ccu1 CLK_CPU_TIMER3>;
 416                         clock-names = "timerclk";
 417                         resets = <&rgu 35>;
 418                 };
 419
 420                 ssp1: spi@400c5000 {
 421                         compatible = "arm,pl022", "arm,primecell";
 422                         reg = <0x400c5000 0x1000>;
 423                         interrupts = <23>;
 424                         clocks = <&ccu2 CLK_APB2_SSP1>, <&ccu1 CLK_CPU_SSP1>;
 425                         clock-names = "sspclk", "apb_pclk";
 426                         resets = <&rgu 51>;
 427                         dmas = <&dmamux 11 2 2
 428                                 &dmamux 12 2 2
 429                                 &dmamux  3 3 2
 430                                 &dmamux  4 3 2
 431                                 &dmamux  5 2 2
 432                                 &dmamux  6 2 2
 433                                 &dmamux 13 2 2
 434                                 &dmamux 14 2 2>;
 435                         dma-names = "rx", "tx", "tx", "rx",
 436                                     "tx", "rx", "rx", "tx";
 437                         #address-cells = <1>;
 438                         #size-cells = <0>;
 439                         status = "disabled";
 440                 };
 441
 442                 i2c1: i2c@400e0000 {
 443                         compatible = "nxp,lpc1788-i2c";
 444                         reg = <0x400e0000 0x1000>;
 445                         interrupts = <19>;
 446                         clocks = <&ccu1 CLK_APB3_I2C1>;
 447                         resets = <&rgu 49>;
 448                         #address-cells = <1>;
 449                         #size-cells = <0>;
 450                         status = "disabled";
 451                 };
 452
 453                 dac: dac@400e1000 {
 454                         compatible = "nxp,lpc1850-dac";
 455                         reg = <0x400e1000 0x1000>;
 456                         interrupts = <0>;
 457                         clocks = <&ccu1 CLK_APB3_DAC>;
 458                         resets = <&rgu 42>;
 459                         status = "disabled";
 460                 };
 461
 462                 can0: can@400e2000 {
 463                         compatible = "bosch,c_can";
 464                         reg = <0x400e2000 0x1000>;
 465                         interrupts = <51>;
 466                         clocks = <&ccu1 CLK_APB3_CAN0>;
 467                         resets = <&rgu 55>;
 468                         status = "disabled";
 469                 };
 470
 471                 adc0: adc@400e3000 {
 472                         compatible = "nxp,lpc1850-adc";
 473                         reg = <0x400e3000 0x1000>;
 474                         interrupts = <17>;
 475                         clocks = <&ccu1 CLK_APB3_ADC0>;
 476                         resets = <&rgu 40>;
 477                         status = "disabled";
 478                 };
 479
 480                 adc1: adc@400e4000 {
 481                         compatible = "nxp,lpc1850-adc";
 482                         reg = <0x400e4000 0x1000>;
 483                         interrupts = <21>;
 484                         clocks = <&ccu1 CLK_APB3_ADC1>;
 485                         resets = <&rgu 41>;
 486                         status = "disabled";
 487                 };
 488
 489                 gpio: gpio@400f4000 {
 490                         compatible = "nxp,lpc1850-gpio";
 491                         reg = <0x400f4000 0x4000>;
 492                         clocks = <&ccu1 CLK_CPU_GPIO>;
 493                         gpio-controller;
 494                         #gpio-cells = <2>;
 495                         gpio-ranges =   <&pinctrl LPC_GPIO(0,0)  LPC_PIN(0,0)  2>,
 496                                         <&pinctrl LPC_GPIO(0,4)  LPC_PIN(1,0)  1>,
 497                                         <&pinctrl LPC_GPIO(0,8)  LPC_PIN(1,1)  4>,
 498                                         <&pinctrl LPC_GPIO(1,8)  LPC_PIN(1,5)  2>,
 499                                         <&pinctrl LPC_GPIO(1,0)  LPC_PIN(1,7)  8>,
 500                                         <&pinctrl LPC_GPIO(0,2)  LPC_PIN(1,15) 2>,
 501                                         <&pinctrl LPC_GPIO(0,12) LPC_PIN(1,17) 2>,
 502                                         <&pinctrl LPC_GPIO(0,15) LPC_PIN(1,20) 1>,
 503                                         <&pinctrl LPC_GPIO(5,0)  LPC_PIN(2,0)  7>,
 504                                         <&pinctrl LPC_GPIO(0,7)  LPC_PIN(2,7)  1>,
 505                                         <&pinctrl LPC_GPIO(5,7)  LPC_PIN(2,8)  1>,
 506                                         <&pinctrl LPC_GPIO(1,10) LPC_PIN(2,9)  1>,
 507                                         <&pinctrl LPC_GPIO(0,14) LPC_PIN(2,10) 1>,
 508                                         <&pinctrl LPC_GPIO(1,11) LPC_PIN(2,11) 3>,
 509                                         <&pinctrl LPC_GPIO(5,8)  LPC_PIN(3,1)  2>,
 510                                         <&pinctrl LPC_GPIO(1,14) LPC_PIN(3,4)  2>,
 511                                         <&pinctrl LPC_GPIO(0,6)  LPC_PIN(3,6)  1>,
 512                                         <&pinctrl LPC_GPIO(5,10) LPC_PIN(3,7)  2>,
 513                                         <&pinctrl LPC_GPIO(2,0)  LPC_PIN(4,0)  7>,
 514                                         <&pinctrl LPC_GPIO(5,12) LPC_PIN(4,8)  3>,
 515                                         <&pinctrl LPC_GPIO(2,9)  LPC_PIN(5,0)  7>,
 516                                         <&pinctrl LPC_GPIO(2,7)  LPC_PIN(5,7)  1>,
 517                                         <&pinctrl LPC_GPIO(3,0)  LPC_PIN(6,1)  5>,
 518                                         <&pinctrl LPC_GPIO(0,5)  LPC_PIN(6,6)  1>,
 519                                         <&pinctrl LPC_GPIO(5,15) LPC_PIN(6,7)  2>,
 520                                         <&pinctrl LPC_GPIO(3,5)  LPC_PIN(6,9)  3>,
 521                                         <&pinctrl LPC_GPIO(2,8)  LPC_PIN(6,12) 1>,
 522                                         <&pinctrl LPC_GPIO(3,8)  LPC_PIN(7,0)  8>,
 523                                         <&pinctrl LPC_GPIO(4,0)  LPC_PIN(8,0)  8>,
 524                                         <&pinctrl LPC_GPIO(4,12) LPC_PIN(9,0)  4>,
 525                                         <&pinctrl LPC_GPIO(5,17) LPC_PIN(9,4)  2>,
 526                                         <&pinctrl LPC_GPIO(4,11) LPC_PIN(9,6)  1>,
 527                                         <&pinctrl LPC_GPIO(4,8)  LPC_PIN(a,1)  3>,
 528                                         <&pinctrl LPC_GPIO(5,19) LPC_PIN(a,4)  1>,
 529                                         <&pinctrl LPC_GPIO(5,20) LPC_PIN(b,0)  7>,
 530                                         <&pinctrl LPC_GPIO(6,0)  LPC_PIN(c,1) 14>,
 531                                         <&pinctrl LPC_GPIO(6,14) LPC_PIN(d,0) 17>,
 532                                         <&pinctrl LPC_GPIO(7,0)  LPC_PIN(e,0) 16>,
 533                                         <&pinctrl LPC_GPIO(7,16) LPC_PIN(f,1)  3>,
 534                                         <&pinctrl LPC_GPIO(7,19) LPC_PIN(f,5)  7>;
 535                 };
 536         };
 537 };